JPH05115136A - Instantaneous voltage drop compensator - Google Patents

Instantaneous voltage drop compensator

Info

Publication number
JPH05115136A
JPH05115136A JP3302263A JP30226391A JPH05115136A JP H05115136 A JPH05115136 A JP H05115136A JP 3302263 A JP3302263 A JP 3302263A JP 30226391 A JP30226391 A JP 30226391A JP H05115136 A JPH05115136 A JP H05115136A
Authority
JP
Japan
Prior art keywords
reverse bias
voltage
period
power supply
instantaneous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3302263A
Other languages
Japanese (ja)
Other versions
JP3070192B2 (en
Inventor
Koichi Sano
耕市 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP3302263A priority Critical patent/JP3070192B2/en
Publication of JPH05115136A publication Critical patent/JPH05115136A/en
Application granted granted Critical
Publication of JP3070192B2 publication Critical patent/JP3070192B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent unnecessary backward bias voltage from being supplied to the load by controlling the generation period of the backward voltage for forced extinction of arc of a thyristor switch to the minimum necessary one at the time of detection of an instantaneous voltage drop, in a serial- compensating instantaneous voltage drop compensator wherein an inverter device is used. CONSTITUTION:This equipment is provided with an instantaneous value detecting circuit 26 which sample-holds an instantaneous value of a conduction current of a thyristor switch 2 at the time of detection of an instantaneous voltage drop of an AC power supply 1, a backward bias period setting circuit 32 which variably sets a backward bias voltage supplying period according to the magnitude of the instantaneous value and which generates a control signal for forced extinction of arc during the backward bias period, and a control switching circuit 34 which controls an inverter device 18 to the output of the backward bias voltage while the control signal is generated and controls the inverter device 18 to the output of a compensating AC when the generation of the control signal is finished.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、負荷に供給される交流
電源の瞬時電圧低下の発生時、インバータ装置を駆動
し、常給電路を形成するサイリスタスイッチを強制消弧
した後、インバータ装置の補償交流により負荷電圧の低
下を直列補償する瞬時電圧補償装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an inverter device when an AC voltage supplied to a load is momentarily dropped and forcibly extinguishing a thyristor switch forming a constant power supply path, and then The present invention relates to an instantaneous voltage compensator that serially compensates for a decrease in load voltage by compensating AC.

【0002】[0002]

【従来の技術】従来、この種直列補償型の瞬時電圧低下
補償装置は、例えば特願昭61−196216号の出願
の明細書及び図面に記載されているように、ほぼ図3に
示すように構成されている。そして、系統電源等の交流
電源1の電圧(以下電源電圧という)の正常時は、電源
電圧に同期して常給電路用のサイリスタスイッチ2の逆
並列のサイリスタ2a,2bが交互にトリガされ、スイ
ッチ2を介した交流電源1が負荷3に供給される。
2. Description of the Related Art Conventionally, this type of series compensation type instantaneous voltage drop compensating device is generally shown in FIG. 3 as described in the specification and drawings of the application of Japanese Patent Application No. 61-196216. It is configured. Then, when the voltage of the AC power supply 1 such as a system power supply (hereinafter referred to as power supply voltage) is normal, the antiparallel thyristors 2a and 2b of the thyristor switch 2 for the normal power supply path are alternately triggered in synchronization with the power supply voltage, The AC power supply 1 is supplied to the load 3 via the switch 2.

【0003】また、交流電源1が電源トランス4を介し
て整流器5に入力され、この整流器5の整流出力により
エネルギ蓄積コンデンサ6が充電される。さらに、電源
電圧が電圧検出トランス7で検出され、このトランス7
の2次側の検出電圧Viに同期して位相同期回路8が同
期パルスを形成し、このパルスに基づき基準正弦波発生
回路9が定格電源電圧に相当する振幅の基準正弦波電圧
Vsを電源電圧に同期して発生する。
Further, the AC power source 1 is input to the rectifier 5 via the power transformer 4, and the rectified output of the rectifier 5 charges the energy storage capacitor 6. Further, the power supply voltage is detected by the voltage detection transformer 7, and this transformer 7
The phase synchronization circuit 8 forms a synchronization pulse in synchronism with the secondary side detection voltage Vi, and the reference sine wave generation circuit 9 supplies a reference sine wave voltage Vs having an amplitude corresponding to the rated power supply voltage based on this pulse. Occurs in synchronization with.

【0004】さらに、電圧低下検出回路10により電圧
Vi,Vsの差の例えば1/4サイクルの積分がくり返
されるとともに積分値と低下検出の基準値とが比較さ
れ、比較結果に基づいて電源電圧の瞬時電圧低下(以下
瞬低という)の発生が検出される。また、検出回路10
の低下検出信号aが入力される切換制御回路11は、電
源電圧の正常時、サイリスタ駆動回路12に後述のタイ
マ信号bを出力せず、その結果、駆動回路12がサイリ
スタ2a,2bを交互にオントリガする。
Further, the voltage drop detection circuit 10 repeats integration of, for example, 1/4 cycle of the difference between the voltages Vi and Vs, compares the integrated value with a reference value for voltage drop detection, and based on the comparison result, the power supply voltage. Occurrence of a momentary voltage drop (hereinafter referred to as a momentary voltage drop) is detected. In addition, the detection circuit 10
When the power supply voltage is normal, the switching control circuit 11 to which the drop detection signal a is input does not output a timer signal b described later to the thyristor drive circuit 12, and as a result, the drive circuit 12 alternately switches the thyristors 2a and 2b. Trigger on.

【0005】つぎに、雷害等の瞬低により電源電圧が図
4(a)に示すようにt0 に低下し、t1 に同図(b)
の低下検出信号aが出力されると、切換制御回路によ
り、検出信号aの立上りに同期した同図(d)のタイマ
信号b,同図(e)の逆バイアス指令信号cが形成され
るとともに、この信号cの立下りに同期した同図(f)
の補償出力期間のゲート信号dが形成される。
Next, the power source voltage is reduced to t 0 as shown in FIG. 4 (a) due to an instantaneous drop such as lightning damage, and at t 1 (b) in FIG.
When the decrease detection signal a is output, the switching control circuit forms the timer signal b shown in FIG. 6D and the reverse bias command signal c shown in FIG. 7E in synchronization with the rise of the detection signal a. , (F) in the figure, which is synchronized with the trailing edge of this signal c.
The gate signal d in the compensation output period of is formed.

【0006】そして、タイマ信号bは瞬時電圧低下の発
生期間より長い2秒程度の幅に設定され、この信号bの
発生により駆動回路12がサイリスタ2a,2bのトリ
ガ(サイリスタ駆動)を停止する。
Then, the timer signal b is set to a width of about 2 seconds, which is longer than the occurrence period of the instantaneous voltage drop, and the drive circuit 12 stops the trigger (thyristor drive) of the thyristors 2a and 2b by the generation of the signal b.

【0007】このとき、オン状態のサイリスタ2a又は
2bは、後述の逆バイアス電圧で強制消弧されるまで電
源電流を負荷3に供給し、サイリスタスイッチ2の通電
電流(以下サイリスタ電流という)は図4(c)に示す
ように変化する。また、指令信号cは強制消弧用の所定
の逆バイアス期間τ0 (t1 〜t2 )のモノマルチパル
スからなり、ゲート信号dはタイマ信号bに同期して立
下る。
At this time, the thyristor 2a or 2b in the ON state supplies the power supply current to the load 3 until it is forcibly extinguished by the reverse bias voltage described later, and the current flowing through the thyristor switch 2 (hereinafter referred to as thyristor current) is 4 (c). The command signal c is composed of a mono-multi pulse of a predetermined reverse bias period τ 0 (t 1 to t 2 ) for forced arc extinction, and the gate signal d falls in synchronization with the timer signal b.

【0008】そして、指令信号cによって逆バイアス発
生回路13が動作し、この発生回路13から加算器14
を介してインバータ駆動回路15に、図4(g)に示す
スイッチ2の強制消弧用の制御信号eが供給される。
Then, the reverse bias generation circuit 13 operates in response to the command signal c, and the generation circuit 13 causes the adder 14 to operate.
The inverter drive circuit 15 is supplied with the control signal e for forced extinction of the switch 2 shown in FIG.

【0009】すなわち、交流電流1とスイッチ2との間
の給電路に設けられた電流検出トランス16の検出電流
に基づき、極性検出回路17から発生回路13に交流電
源1の電流(以下電源電流という)の極性検出信号fが
供給され、指令信号cが入力されると、発生回路13は
サイリスタ2a,2bを確実に転流消弧するように設定
された強制消弧の逆バイアス期間τ0 、電源電流に応じ
た極性の制御信号eを発生する。
That is, based on the detection current of the current detection transformer 16 provided in the power supply path between the AC current 1 and the switch 2, the polarity detection circuit 17 supplies the current to the generation circuit 13 of the AC power supply 1 (hereinafter referred to as power supply current). When the polarity detection signal f of) is supplied and the command signal c is input, the generating circuit 13 sets the reverse bias period τ 0 of forced extinction set to surely extinguish the commutation of the thyristors 2a and 2b. A control signal e having a polarity corresponding to the power supply current is generated.

【0010】そして、制御信号eに基づく駆動回路15
の制御により、インバータ装置18がコンデンサ6の蓄
積エネルギで動作し、注入トランス19の1次側19a
を介してスイッチ2に並列に設けられた2次側19a
に、ほぼ電源電圧のピーク値に相当する逆バイアス電圧
が発生し、この電圧でスイッチ2がtx (t1 <ty
2 )に強制消弧されてオフする。なお、逆バイアス電
圧の極性も制御信号eによって定まり、スイッチ2を介
して負荷3に図3の矢印Iの向きに負荷電流が流れると
きは、サイリスタ2bをオフするために逆バイアス電圧
が同図の矢印Vhの向きに発生する。
The drive circuit 15 based on the control signal e
The inverter device 18 operates by the energy stored in the capacitor 6 under the control of the
Secondary side 19a provided in parallel with the switch 2 via
, A reverse bias voltage substantially corresponding to the peak value of the power supply voltage is generated, and at this voltage, the switch 2 is t x (t 1 <t y
It is extinguished by force at t 2 ) and turns off. The polarity of the reverse bias voltage is also determined by the control signal e, and when the load current flows through the switch 2 in the direction of arrow I in FIG. 3, the reverse bias voltage is turned off to turn off the thyristor 2b. Occurs in the direction of arrow Vh.

【0011】さらに、逆バイアス期間τ0 が終了して指
令信号cが出力されなくなると、ゲート信号dによって
駆動制御用のゲート回路20がオンし、電圧Vi,Vs
の差に基づく減算器21の出力信号,すなわち電源電圧
の低下量に相当する補償量の制御信号gがゲート回路2
0,加算器14を介して駆動回路15に供給され、イン
バータ装置18の制御入力がt2 に制御信号eからgに
切換わる。
Furthermore, when the reverse bias period τ 0 ends and the command signal c is no longer output, the gate signal d turns on the gate circuit 20 for drive control, and the voltages Vi and Vs.
The output signal of the subtracter 21 based on the difference between the two, that is, the control signal g of the compensation amount corresponding to the decrease amount of the power supply voltage is
0, supplied to the drive circuit 15 via the adder 14, and the control input of the inverter device 18 is switched from the control signal e to g at t 2 .

【0012】そして、制御信号gに基づきt2 以降のイ
ンバータ装置18の出力は、図4(h)に示すように電
源電圧の低下量に相当する補償交流になり、この補償交
流が交流電源1に直列合成されて負荷3に供給され、同
図(i)に示す負荷電圧は低下が直列補償される。
Based on the control signal g, the output of the inverter device 18 after t 2 becomes a compensating AC corresponding to the amount of decrease in the power supply voltage as shown in FIG. 4 (h), and this compensating AC is the AC power supply 1 Are serially combined and supplied to the load 3, and the drop of the load voltage shown in FIG.

【0013】なお、図3の22,23は高調波除去フイ
ルタを構成するコンデンサ,抵抗であり、注入トランス
19の出力の高調波を除去する。また、検出信号aが終
了するt3 以降にゲート回路20がオフして制御信号g
が遮断されると、制御回路11はゲート信号bをオフし
て駆動回路12を動作し、正常時の動作状態に戻る。
Reference numerals 22 and 23 in FIG. 3 denote capacitors and resistors that form a harmonic elimination filter, and eliminate the harmonics of the output of the injection transformer 19. Further, after t 3 when the detection signal a ends, the gate circuit 20 is turned off and the control signal g
Is cut off, the control circuit 11 turns off the gate signal b, operates the drive circuit 12, and returns to the normal operating state.

【0014】[0014]

【発明が解決しょうとする課題】前記従来の補償装置の
場合、逆バイアス期間τ0 は、サイリスタ2a,2bの
電流が定格ピーク値であってもスイッチ2を確実にオフ
するように、十分に長い期間に設定される。
In the case of the above-mentioned conventional compensator, the reverse bias period τ 0 is sufficient to surely turn off the switch 2 even if the currents of the thyristors 2a and 2b have the rated peak values. Set for a long period.

【0015】すなわち、サイリスタ2a,2bが逆バイ
アス電圧で消弧される際、サイリスタ電流が減少してオ
フするまでの消弧時間ΔTは、図5(a)に示すよう
に、ほぼΔI/ΔT=E/L(ΔIは電流、Eは逆バイ
アス電圧、Lは注入トランス19の漏れインダクタン
ス)で決まり、そのときのサイリスタスイッチ2の通流
電流(サイリスタ電流)に比例して長くなる。
That is, when the thyristors 2a and 2b are extinguished by the reverse bias voltage, the extinction time ΔT until the thyristor current decreases and turns off is approximately ΔI / ΔT as shown in FIG. 5 (a). = E / L (ΔI is the current, E is the reverse bias voltage, L is the leakage inductance of the injection transformer 19) and becomes longer in proportion to the current flowing through the thyristor switch 2 (thyristor current) at that time.

【0016】したっがて、逆バイアス期間τ0 は予想さ
れるほぼ最長の消弧時間ΔTに設定される。
Therefore, the reverse bias period τ 0 is set to the substantially longest expected extinction time ΔT.

【0017】この場合、負荷3の状態,電流位相等に基
づき、強制消弧時のサイリスタ電流が定格ピーク値より
小であれば、図5(b)に示すように逆バイアス期間τ
0 より十分短い時間でサイリスタ2a,2bがオフし、
その後、インバータ装置18の出力が補償交流に切換わ
るまで、逆バイアス電圧が交流電源1に直列合成されて
負荷3に供給される。
In this case, if the thyristor current during forced extinction is smaller than the rated peak value based on the state of the load 3, the current phase, etc., as shown in FIG.
The thyristors 2a and 2b turn off in a time sufficiently shorter than 0 ,
After that, the reverse bias voltage is combined in series with the AC power supply 1 and supplied to the load 3 until the output of the inverter device 18 is switched to the compensation AC.

【0018】そして、例えば図4(h)のt1 〜t2
逆バイアス電圧により、同図のtx にサイリスタ2a又
は2bがオフすると、その後のtx 〜t2 には逆バイア
ス電圧が負荷3に供給される。そして、tx 〜t2 の逆
バイアス電圧により負荷電圧は図4(i)に示すように
大きく乱れ、安定な補償が行えない問題点があり、例え
ば負荷3が位相制御を行うサイリスタ変換器であれば、
負荷3の誤動作等が生じる。
[0018] Then, for example, by a reverse bias voltage t 1 ~t 2 in FIG. 4 (h), the thyristor 2a or 2b in the figure t x is turned off, the subsequent reverse bias voltage to the t x ~t 2 It is supplied to the load 3. Then, the load voltage by the reverse bias voltage of t x ~t 2 is greatly disturbed as shown in FIG. 4 (i), there is a problem that can not be performed stably compensation, for example, the load 3 is in a thyristor converter for performing phase control if there is,
A malfunction of the load 3 occurs.

【0019】本発明は、瞬低検出時のサイリスタスイッ
チの通電電流の大きさに応じて逆バイアス期間を可変設
定し、不要な逆バイアス電圧の供給を防止するようにし
た瞬時電圧低下補償装置を提供することを目的とする。
The present invention provides an instantaneous voltage drop compensating device for preventing the supply of unnecessary reverse bias voltage by variably setting the reverse bias period according to the magnitude of the current flowing through the thyristor switch at the time of detecting a voltage sag. The purpose is to provide.

【0020】[0020]

【課題を解決するための手段】前記の目的を達成するた
めに、本発明の瞬時電圧低下補償装置においては、瞬低
検出時のサイリスタスイッチの通電電流の瞬時値をサン
プルホールドして検出する瞬時値検出回路と、前記瞬時
値の大,小により逆バイアス電圧を供給する逆バイアス
期間を長,短に可変調整して設定し,この逆バイアス期
間に強制消弧用の制御信号を発生する逆バイアス期間設
定回路と、前記制御信号の発生期間にインバータ装置を
前記逆バイアス電圧の出力に制御し,前記制御信号の発
生終了によりインバータ装置を補償交流の出力に制御す
る制御切換回路とを備える。
In order to achieve the above-mentioned object, in the instantaneous voltage drop compensating device of the present invention, the instantaneous value for sampling and holding the instantaneous value of the energizing current of the thyristor switch at the time of detecting the voltage sag is detected. A value detection circuit and a reverse bias period for supplying a reverse bias voltage depending on the magnitude of the instantaneous value are variably adjusted to long and short, and a reverse bias period is generated to generate a control signal for forced arc extinction. A bias period setting circuit and a control switching circuit that controls the inverter device to output the reverse bias voltage during the generation period of the control signal and controls the inverter device to output the compensation AC when the generation of the control signal ends.

【0021】[0021]

【作用】前記のように構成された本発明の瞬時電圧低下
補償装置の場合、瞬低が検出されると、瞬時値検出回路
によりそのときのサイリスタスイッチの通電電流(サイ
リスタ電流)の大きさが瞬時値として検出される。さら
に、検出された瞬時値に基づき、逆バイアス期間設定回
路により逆バイアス期間が瞬時値の大きさに適した長さ
に可変設定され、設定された逆バイアス期間に強制消弧
用の制御信号が発生する。
In the momentary voltage drop compensating device of the present invention constructed as described above, when a voltage sag is detected, the instantaneous value detection circuit determines the magnitude of the current (thyristor current) flowing through the thyristor switch at that time. It is detected as an instantaneous value. Furthermore, based on the detected instantaneous value, the reverse bias period setting circuit variably sets the reverse bias period to a length suitable for the magnitude of the instantaneous value, and the control signal for forced extinction is set during the set reverse bias period. Occur.

【0022】そして、制御切換回路によりインバータ装
置は前記強制消弧の制御信号の発生期間だけ逆バイアス
電圧の出力に制御され、その後補償交流の出力に制御さ
れる。このとき、逆バイアス期間がサイリスタスイッチ
の強制消弧の必要最小限の期間になるため、不要な逆バ
イアス電圧が負荷に供給されなくなる。
Then, the control switching circuit controls the inverter device to output the reverse bias voltage only during the generation period of the control signal for the forced extinction, and then to the output of the compensation AC. At this time, the reverse bias period becomes the minimum necessary period for forcibly extinguishing the thyristor switch, so that unnecessary reverse bias voltage is not supplied to the load.

【0023】[0023]

【実施例】1実施例において、図1及び図2を参照して
説明する。図1において、図3と同一符号は同一もしく
は相当するものを示し、図3の従来装置と異なる点は、
全波整流器24,サンプルホールド回路25が形成する
瞬時値検出回路26と、可変抵抗27,積分器28,比
較器29,インバータ30,期間調整用のゲート回路3
1が形成する逆バイアス期間設定回路32と、切換制御
回路11の補償制御期間のゲート信号dを比較器29の
出力信号γで加算補正するオアゲート33とを付加した
点である。
EXAMPLE One example will be described with reference to FIGS. 1, the same reference numerals as those in FIG. 3 indicate the same or corresponding ones, and the difference from the conventional apparatus in FIG.
Instantaneous value detection circuit 26 formed by full wave rectifier 24 and sample hold circuit 25, variable resistor 27, integrator 28, comparator 29, inverter 30, gate circuit 3 for period adjustment
The reverse bias period setting circuit 32 formed by 1 and the OR gate 33 that adds and corrects the gate signal d in the compensation control period of the switching control circuit 11 with the output signal γ of the comparator 29 are added.

【0024】なお、加算器14,ゲート回路20,オア
ゲート33によりインバータ駆動の制御切換回路34が
形成されている。また、可変抵抗27は直流電源端子3
5の直流電圧が印加され、この電圧の分圧が積分基準電
圧として切換片に発生する。
An inverter-driven control switching circuit 34 is formed by the adder 14, the gate circuit 20, and the OR gate 33. The variable resistor 27 is connected to the DC power supply terminal 3
A DC voltage of 5 is applied, and the divided voltage of this voltage is generated in the switching piece as an integral reference voltage.

【0025】そして、図4の場合と同様t0 に瞬低が発
生すると、この瞬低の検出に基づき図2(a)に示すよ
うにt1 に検出回路10から低下検出信号aが出力さ
れ、この検出信号aに基づき切換回路11は従来と同
様、t1 に立上るタイマ信号b及び同図(c)の一定期
間τ0 (=t1 〜t2 )の逆バイアス指令信号c,t2
に立上る同図(d)の補正出力期間のゲート信号dを形
成する。また、指令信号cに基づき発生回路13は図2
(e)に示す従来と同様の一定期間τ0 の強制消弧用の
制御信号eを形成し、この信号eをゲート回路31に供
給する。
[0025] Then, when the voltage sag occurs in the same manner t0 the case of FIG. 4, drop detection signal a from detecting circuit 10 to t 1 as shown in Figure based on the detection of the instantaneous drop 2 (a) is outputted, On the basis of this detection signal a, the switching circuit 11 causes the timer signal b rising to t 1 and the reverse bias command signals c and t 2 of the constant period τ 0 (= t 1 to t 2 ) of FIG.
The gate signal d in the correction output period shown in FIG. Further, based on the command signal c, the generation circuit 13 is shown in FIG.
A control signal e for forced extinction for a fixed period τ 0 similar to the conventional one shown in (e) is formed, and this signal e is supplied to the gate circuit 31.

【0026】一方、整流器24はトランス16の検出電
流を全波整流し、図2(b)のサイリスタスイッチ2の
通電電流(サイリスタ電流)の全波整流信号を形成し、
この整流信号をサンプルホールド回路25に供給する。
On the other hand, the rectifier 24 full-wave rectifies the detected current of the transformer 16 to form a full-wave rectified signal of the current (thyristor current) of the thyristor switch 2 shown in FIG.
This rectified signal is supplied to the sample hold circuit 25.

【0027】このサンプルホールド回路25は検出信号
aの立上りによりトリガされて前記全波整流信号をサン
プルホールドし、図2(f)に示す瞬低検出時t1 のサ
イリスタ電流の瞬時値のホールド信号αを比較器29に
供給する。また、逆バイアス指令信号cにより積分器2
8はこの指令信号cの期間τ0 に動作し、可変抵抗27
の定電圧化された前記積分基準電圧を積分する。
This sample-hold circuit 25 is triggered by the rising edge of the detection signal a to sample-hold the full-wave rectified signal, and the hold signal of the instantaneous value of the thyristor current at the time t 1 shown in FIG. α is supplied to the comparator 29. In addition, the integrator 2 receives the reverse bias command signal c.
8 operates during the period τ 0 of this command signal c, and the variable resistor 27
The integrated reference voltage, which has been converted to a constant voltage, is integrated.

【0028】このとき、積分時定数は逆バイアス電圧,
注入トランス19の漏れインダクタンスLに基づいてE
/Lに設定され、積分器28の出力信号βは図2(g)
に示すようにE/Lの傾きで線形増加する。そして、比
較器29は出力信号βを参照信号(基準信号)としてホ
ールド信号αと出力信号βとを比較し、β≧αのtx
2 に図2(h)の補正用の比較信号γを出力する。
At this time, the integration time constant is the reverse bias voltage,
E based on the leakage inductance L of the injection transformer 19
/ L, and the output signal β of the integrator 28 is shown in FIG.
As shown in, the linear increase is made with the slope of E / L. Then, the comparator 29 compares the hold signal α with the output signal β by using the output signal β as a reference signal (reference signal), and t x ~ of β ≧ α
At t 2 , the correction comparison signal γ shown in FIG. 2 (h) is output.

【0029】ところで、図5の(a),(b)で説明し
たようにE/L=ΔI/ΔTの関係があり、この関係式
から導かれるΔI=(E/L)ΔTの式において、瞬時
値ΔIはホールド信号αとして検出され、(E/L)Δ
Tは消弧期間ΔTの大きさに応じて出力信号βに沿って
変化する。そこで、信号α,βの比較に基づき、期間τ
0 のうち必要な消弧期間ΔTがt1 からα=βに達する
x までの期間τx として求まる。
By the way, there is a relation of E / L = ΔI / ΔT as explained in FIGS. 5A and 5B, and in the equation of ΔI = (E / L) ΔT derived from this relational expression, The instantaneous value ΔI is detected as the hold signal α, and (E / L) Δ
T changes along the output signal β according to the magnitude of the extinguishing period ΔT. Therefore, based on the comparison of the signals α and β, the period τ
Of 0 , the required extinction period ΔT is obtained as a period τ x from t 1 to t x when α = β.

【0030】そして、比較器29が期間τ0 のうちの不
要な期間tx 〜t2 に比較信号γを出力し、この信号γ
を反転した図2(i)のインバータ30の反転信号γ*
がゲート回路31に供給される。この出力信号γ* の供
給期間にゲート回路31はゲート信号eの出力を停止
し、期間τ0 の制御信号eを図2(j)の期間τx の制
御信号εに可変調整して加算器14に出力する。
Then, the comparator 29 outputs the comparison signal γ during an unnecessary period t x to t 2 of the period τ 0 , and this signal γ
The inverted signal γ * of the inverter 30 of FIG.
Are supplied to the gate circuit 31. Gate circuit 31 to the output signal gamma * supply period of the stops output of the gate signal e, variable adjustment to the adder control signal e period tau 0 to the control signal ε period tau x in FIG. 2 (j) It outputs to 14.

【0031】したがって、設定回路32はサイリスタ電
流の瞬時値ΔIの大,小によりサイリスタスイッチ2の
強制消弧用の逆バイアス期間を長,短に可変調整して必
要な強制消弧期間τx に設定し、この期間τx の制御信
号εを制御信号eの代わりに制御回路34の加算器14
を介して駆動回路15に供給する。
Therefore, the setting circuit 32 variably adjusts the reverse bias period for forcibly extinguishing the thyristor switch 2 to long or short depending on the magnitude of the instantaneous value ΔI of the thyristor current to obtain the required forcible extinguishing period τ x . The control signal ε of this period τ x is set and the adder 14 of the control circuit 34 is used instead of the control signal e.
Is supplied to the drive circuit 15 via.

【0032】この供給により駆動回路15はt1 〜tx
の期間τx にインバータ装置18を逆バイアス電圧の出
力に制御し、この逆バイアス電圧によりサイリスタスイ
ッチ2が過不足のない適切な電圧印加で強制消弧されて
オフする。
Due to this supply, the drive circuit 15 is t 1 to t x.
In the period τ x , the inverter device 18 is controlled to output a reverse bias voltage, and the reverse bias voltage turns off the thyristor switch 2 by forcibly extinguishing it by applying a proper voltage without excess or deficiency.

【0033】また、比較信号γが制御回路34のオアゲ
ート33に供給され、このゲート33によりゲート信号
dが比較信号γで加算補正され、図2(k)に示すよう
に立上りをtx に補正したゲート信号δ(=d+γ)が
ゲート信号dの代わりにゲート回路20に供給される。
Further, the comparison signal γ is supplied to the OR gate 33 of the control circuit 34, the gate signal d is added and corrected by the comparison signal γ by the gate 33, and the rising edge is corrected to t x as shown in FIG. 2 (k). The gate signal δ (= d + γ) is supplied to the gate circuit 20 instead of the gate signal d.

【0034】そして、ゲート回路20はゲート信号δが
立上るtx にオンし、制御信号εの代わりに制御信号g
を加算器14を介して駆動回路15に供給し、サイリス
タスイッチ2がオフすると同時に、インバータ装置18
を補償交流の出力に切換えて制御する。
Then, the gate circuit 20 turns on at t x when the gate signal δ rises, and instead of the control signal ε, the control signal g
Is supplied to the drive circuit 15 via the adder 14 and the thyristor switch 2 is turned off, and at the same time, the inverter device 18
Is switched to the output of compensation AC to control.

【0035】したがって、tx 〜t2 に従来装置のよう
な不安な逆バイアス電圧の負荷3への印加が防止され、
負荷電圧は図2(l)の実線に示すように破線の従来装
置の負荷電圧のような逆バイアス電圧での乱れが生じな
い。
Therefore, the application of the undesired reverse bias voltage to the load 3 as in the conventional device is prevented from t x to t 2 ,
As shown by the solid line in FIG. 2 (l), the load voltage is free from the disturbance caused by the reverse bias voltage as in the load voltage of the conventional device indicated by the broken line.

【0036】[0036]

【発明の効果】本発明は以上説明したように構成されて
いるため、以下に記載する効果を奏する。瞬時電圧低下
の検出時、瞬時値検出回路26によりサイリスタスイッ
チ2の通電電流(サイリスタ電流)の大きさを瞬時値と
して検出し、逆バイアス期間回路32により前記瞬時値
の大,小に応じてスイッチ2の強制消弧用の逆バイアス
期間を長,短に可変調整して設定し、必要な期間τx
強制消弧用の制御信号εを発生し、制御切換回路34に
より制御信号εの発生期間τx だけインバータ装置18
を逆バイアス電圧の出力に制御し、発生期間τx の終了
と同時にインバータ装置18を補償交流の出力に切換え
て制御したため、瞬時電圧低下が発生したとともに、ス
イッチ2のオフ後にインバータ装置18から逆バイアス
電圧が出力されず、不要な逆バイアス電圧の負荷3への
供給が防止されて負荷電圧の乱れが防止され、安定な補
償を行うことができる。
Since the present invention is constructed as described above, it has the following effects. When an instantaneous voltage drop is detected, the instantaneous value detection circuit 26 detects the magnitude of the energizing current (thyristor current) of the thyristor switch 2 as an instantaneous value, and the reverse bias period circuit 32 switches depending on whether the instantaneous value is large or small. The reverse bias period for forced arc extinguishing of No. 2 is variably adjusted to be long or short, and the control signal ε for forced extinction of the required period τ x is generated, and the control switching circuit 34 generates the control signal ε. Inverter device 18 only for period τ x
Is controlled to the output of the reverse bias voltage, and the inverter device 18 is switched to the output of the compensation AC at the same time as the generation period τ x ends, so that the instantaneous voltage drop occurs and the inverter device 18 reverses the voltage after the switch 2 is turned off. Since the bias voltage is not output, unnecessary reverse bias voltage is prevented from being supplied to the load 3, disturbance of the load voltage is prevented, and stable compensation can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の瞬時電圧低下補償装置の1実施例のブ
ロック図である。
FIG. 1 is a block diagram of an embodiment of an instantaneous voltage drop compensating device of the present invention.

【図2】(a)〜(l)は図1の動作説明用のタイミン
グチャートである。
2 (a) to (l) are timing charts for explaining the operation of FIG.

【図3】従来装置のブロック図である。FIG. 3 is a block diagram of a conventional device.

【図4】(a)〜(j)は図3の動作説明用のタイミン
グチャートである。
4A to 4J are timing charts for explaining the operation of FIG.

【図5】(a),(b)はサイリスタスイッチの消弧説
明図である。
5A and 5B are explanatory diagrams of extinguishing an arc of a thyristor switch.

【符号の説明】[Explanation of symbols]

1 交流電源 2 サイリスタスイッチ 3 負荷 18 インバータ装置 19 注入トランス 26 瞬時値検出回路 32 逆バイアス期間設定回路 34 制御切換回路 1 AC power supply 2 Thyristor switch 3 Load 18 Inverter device 19 Injection transformer 26 Instantaneous value detection circuit 32 Reverse bias period setting circuit 34 Control switching circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 交流電源の瞬時電圧低下の検出時、前記
電源と負荷との間の常給電路用のサイリスタスイッチの
オントリガを停止し、前記電源から前記負荷に供給され
る電流の極性検出にもとづくインバータ装置の強制消弧
用の逆バイアス電圧を前記スイッチに並列に設けられた
注入トランスに供給して前記スイッチをオフした後、前
記インバータ装置の出力を前記電源の電圧低下量に相当
する補償交流に制御し、負荷電圧の低下を前記補償交流
で直列補償する瞬時電圧低下補償装置において、 前記検出時の前記サイリスタスイッチの通電電流の瞬時
値をサンプルホールドして検出する瞬時値検出回路と、 前記瞬時値の大,小により前記逆バイアス電圧を供給す
る逆バイアス期間を長,短に可変調整して設定し,前記
逆バイアス期間に強制消弧用の制御信号を発生する逆バ
イアス期間設定回路と、 前記制御信号の発生期間に前記インバータ装置を前記逆
バイアス電圧の出力に制御し,前記制御信号の発生終了
により前記インバータ装置を前記補償交流の出力に制御
する制御切換回路とを備えたことを特徴とする瞬時電圧
低下補償装置。
1. When detecting an instantaneous voltage drop of an AC power supply, the on-triggering of a thyristor switch for a constant power supply path between the power supply and the load is stopped to detect the polarity of the current supplied from the power supply to the load. A reverse bias voltage for forcibly extinguishing the original inverter device is supplied to an injection transformer provided in parallel with the switch to turn off the switch, and then the output of the inverter device is compensated corresponding to the voltage drop amount of the power supply. In an instantaneous voltage drop compensating device that controls the alternating current and serially compensates the decrease of the load voltage with the compensating alternating current, an instantaneous value detection circuit that samples and holds the instantaneous value of the energizing current of the thyristor switch at the time of the detection, The reverse bias period for supplying the reverse bias voltage is variably adjusted to be long or short according to the magnitude of the instantaneous value, and the reverse bias period is forcibly turned off during the reverse bias period. And a reverse bias period setting circuit for generating a control signal for controlling the inverter device to output the reverse bias voltage during the generation period of the control signal. An instantaneous voltage drop compensating device comprising: a control switching circuit for controlling the output.
JP3302263A 1991-10-21 1991-10-21 Instantaneous voltage drop compensator Expired - Fee Related JP3070192B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3302263A JP3070192B2 (en) 1991-10-21 1991-10-21 Instantaneous voltage drop compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3302263A JP3070192B2 (en) 1991-10-21 1991-10-21 Instantaneous voltage drop compensator

Publications (2)

Publication Number Publication Date
JPH05115136A true JPH05115136A (en) 1993-05-07
JP3070192B2 JP3070192B2 (en) 2000-07-24

Family

ID=17906910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3302263A Expired - Fee Related JP3070192B2 (en) 1991-10-21 1991-10-21 Instantaneous voltage drop compensator

Country Status (1)

Country Link
JP (1) JP3070192B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012162457A2 (en) * 2011-05-25 2012-11-29 Symcom, Inc. Intelligent high speed automatic transfer switch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012162457A2 (en) * 2011-05-25 2012-11-29 Symcom, Inc. Intelligent high speed automatic transfer switch
WO2012162457A3 (en) * 2011-05-25 2013-04-04 Symcom, Inc. Intelligent high speed automatic transfer switch
US9048684B2 (en) 2011-05-25 2015-06-02 Littelfuse, Inc. Intelligent high speed automatic transfer switch

Also Published As

Publication number Publication date
JP3070192B2 (en) 2000-07-24

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