JPH05114826A - Differential amplifying circuit - Google Patents

Abstract

PURPOSE:To obtain the MOS type transistor differential amplifying circuit which uses no source follower. CONSTITUTION:The differential amplifying circuit consists of load MOSFETs QL1 and QL2 which are connected to the drains of differential input stage MOSFETs QI1 and QI2 through diodes, load MOSFETs QL3 and QL4 which are connected to the drains of the differential input stage MOSFETs QI1 and QI2 and operate as a constant current source, and positive feedback MOSFETs QL5 and QL6 which are connected to the drains of the differential input stage MOSFETs QI1 and QI2 and have their gates and drains connected in crossing relation. This circuit is therefore fast and excellent in noise resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit,
In particular, the present invention relates to a differential amplifier circuit used in a differential voltage comparator that compares two voltages.

[0002]

2. Description of the Related Art A conventional differential amplifier circuit, for example, "Th
e Journal of Solid-State
Circuits, Vol. 25, No. 1, FEB
RUARY 1990; pp173-182 "shows an example shown in FIG.
1, Q2 are differential input stages, MOSFETs Q3 and Q4 are diode-connected load circuits, MOSFETs Q7 and Q8 are positive feedback circuits, MOSFET Q9 is a constant current circuit, and MOSF.
ETQ30, Q31 and Q40, Q41 are source follower circuits.

The operation of this circuit will be described. IN +, IN
First, a constant bias voltage is applied to the negative input terminals to the differential input stages Q1 and Q2 for a certain period of time to bring them into a reset state. Next, when two voltages to be compared are applied to the differential input stages Q1 and Q2, the difference between the two input voltages is amplified by the load circuits Q3 and Q4 and the positive feedback circuits Q7 and Q8. This voltage is Q3
It is further amplified by the source follower circuits of 0, Q31 and Q40, Q41, and output from the OUT + and OUT- terminals. The normal voltage comparator is configured by connecting a plurality of such differential amplifier circuits in series.

[0004]

However, in order to operate at high speed and further reduce power consumption, it is necessary to increase the gain per differential amplifier circuit and reduce the number of circuits to be used. .. However, if the positive feedback of this differential amplifier circuit is increased in order to increase the gain, it takes time to reset the circuit, and high-speed operation becomes impossible.
Further, source follower circuits such as Q30, Q31 and Q40, Q41 are greatly affected by power supply noise.

Therefore, it is an object of the present invention to provide a differential amplifier circuit which has a large gain, can operate at high speed, and is less affected by power supply noise.

[0006]

SUMMARY OF THE INVENTION Therefore, the present invention provides a differential input stage MOSFET with two voltages whose voltage difference is to be amplified.
In a differential amplifier circuit for inputting to Q1, Q2 for amplification and comparison, a load MOS diode-connected to each drain of the differential input stage MOSFETs QI1, QI2.
FETs QL1 and QL2 and the differential input stage MOSFET
Positive feedbacks connected to the drains of QI1 and QI2 and connected to the drains of the differential input stage MOSFETs QI1 and QI2, respectively, and load MOSFETs QL3 and QL4 that function as constant current sources, and the gates and drains of which are cross-connected. The problem is solved by including the MOSFETs QL5 and QL6.

[0007]

In the present invention, the differential input stage MOSFE is provided.
Gains are obtained by removing loads of the MOSFETs QL1 and QL2 diode-connected to the drains of the TQI1 and QI2, respectively, and common mode noise is removed. The gains are connected to the drains of the differential input stage MOSFETs QI1 and QI2 and the MOSFETs QL3 and QL4 are connected. Gain is further improved by the load acting as a constant current source, and weak positive feedback is performed by the MOSFETs QL5 and QL6 connected to the drains of the differential input stage MOSFETs QI1 and QI2, and the gates and drains of the MOSFETs are cross-connected to obtain a gain. Larger size, MOSFET QL3, QL4
The constant current can reduce the reset time.

[0008]

EXAMPLE FIG. 1 shows an example of the present invention. Differential input stage N
Channel MOSFET (hereinafter simply referred to as NMOS)
The sources of QI1 and QI2 are short-circuited. P-channel MOSFET (hereinafter simply referred to as PMOS) QL1,
QL2 is a load circuit in which the drain and the gate are connected to the drains of the NMOSs QI1 and QI2, respectively, and the power supply voltage is applied to the sources. PMOS QL3, Q
L4 is a load circuit that works as a constant current source, and NMOSQ
The drains of I1 and QI2 are connected to each other, the bias voltage Vp is applied to the gate, and the power supply voltage is applied to the source. PMOS QL5 and QL6 are
A positive feedback circuit is configured, and the drains of the NMOSs QI1 and QI2 are connected to their drains, their gates and drains are cross-connected, and the power supply voltage is applied to their sources. The short-circuited sources of the NMOS QI1 and QI2 are connected to the drain of the NMOS QS9 as a constant current circuit,
A bias voltage Vn is applied to the gate of the NMOS QS9, and the substrate potential is applied to the source.

The drain of the NMOSQI1 is an NMOSQ
N via a switch circuit consisting of F1 and PMOS QF2
It is connected to the gate of the MOSQI1 and the capacitor C1.
The drain of the NMOS QI2 is connected to the NMOS QF4 and the PMO.
NMOSQI2 via a switch circuit composed of SQF3
Is connected to the gate and the capacitor C2. Further, Vref is applied to the other terminal of the capacitor C1 through a switch circuit composed of an NMOS QT1,
Vin is applied through a switch circuit composed of QT3 and PMOS QT4. The other terminal of the capacitor C2 is N
Vref is applied via the switch circuit composed of MOSQT2, and further Vref is applied via the switch circuit composed of NMOSQT6 and PMOSQT5.

NMOS QT1, QT2, QF1, QF4
Timing gate PH1 is applied to the gate of
Timing pulse PH is applied to the gates of OSQF2 and QF3.
PH1 # which is an inversion pulse of 1 is given. As a result, the switch circuits NMOSQT1, QT2,
The QF1, QF4, the PMOS QF2, and the QF3 are in the ON state while the timing pulse PH1 is at the high level. A timing pulse PH2 is applied to the gates of the NMOS QT3 and QT6, and a timing pulse PH2 inversion pulse PH2 is applied to the gates of the PMOS QT4 and QT5.
# Is given. As a result, the switch circuits NMOSQT3, QT6, PMOSQT4, QT5 are turned on while the timing pulse PH2 is at the high level.

The operation of the circuit of this embodiment will be described with reference to the input / output waveform chart shown in FIG. Timing pulse PH
1 and PH2 have no overlap pulses. When the timing pulse PH1 is at high level, the switch circuits NMOSQF1, QF4, PMOSQF2, Q
F3 is in the ON state, the drains of the NMOS QI1 and QI2 are short-circuited with the gates, and the differential circuit is in the reset state. The terminals of the capacitors C1 and C2 connected to the gates of the NMOS QI1 and QI2 are connected to the NMOS.
The drain voltage of QI1 and QI2 is given. further,
Since the switch circuits NMOSQT1 and QT2 are also in the ON state, Vref is applied to the other terminals of the capacitors C1 and C2. At this time, a potential difference corresponding to the offset of the differential circuit appears in the capacitors C1 and C2. Further, at this time, the outputs of the differential circuits quickly settle to the potentials corresponding to the offsets of the differential circuits due to the functions of the PMOS QL3 and QL4 as constant current sources.

When the timing pulse PH2 becomes high level, the switch circuits NMOSQT3, QT6, PMOS
QT4 and QT5 are turned on, and Vin is applied to the terminal of the capacitor C1 instead of Vref. Also C
Further, Vref is given to 2. At this time NMO
The offset of the differential circuit and | Vref-Vin | are connected to the gates of SQI1 and QI2 via capacitors C1 and C2.
And a potential difference between the gates of the NMOS QI1 and QI2 is generated at the drains of the NMOS QI1 and QI2.
PMOS QL1, QL2, QL3, QL4, QL5, Q
It appears after being amplified by the action of L6.

[0013]

According to the present invention, a differential amplifier circuit which operates at high speed and has a large gain can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is an input / output waveform diagram for showing an example of the operation.

FIG. 3 Conventional circuit diagram

[Explanation of symbols]

Q1, Q2, QI1, QI2 ... Differential input stage Q3, Q4, QL1, QL2, QL3, QL4 ... Load circuit Q7, Q8, QL5, QL6 ... Positive feedback circuit Q9, QS9 ... Constant current circuit QF1, QF2, QF3, QF4, QT1, QT2, Q
T3, QT4, QT5, QT6 ...... Switch circuit Q30, Q31, Q40, Q41 ...... MOSFETs forming source follower circuit, Vi, Vref …… Input voltage PH1, PH2 …… Timing pulse Vo1, Vo2 …… Output voltage

Claims (1)

[Claims] 1. A differential amplifier circuit in which two voltages whose voltage differences are to be amplified are input to differential input stage MOS transistors (hereinafter referred to as "MOSFETs") QI1 and QI2 for amplification and comparison. Dynamic input stage MOSFET QI
Load MOSFETs QL1 and QL2 diode-connected to the respective drains of the Q1 and QI2, and load MOSFETs QL3 connected to the respective drains of the differential input stage MOSFETs QI1 and QI2 and acting as a constant current source,
QL4 and the differential input stage MOSFETs QI1 and QI2
Of the positive feedback MOSFETs QL5 and Q, which are connected to the respective drains of the
A differential amplifier circuit comprising: L6.