JPH05114608A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration of element characteristics by so forming a low concentration diffused layer containing an N-type impurity on a region having a high electrolytic strength at a drain end as to overlap a gate electrode. CONSTITUTION:A gate electrode 105 containing an N-type impurity is formed on a semiconductor substrate 101 containing a low concentration P-type impurity through a gate oxide film 104. Then, photoresists 106, 110 are formed on parts isolated at a predetermined distance from the end of the electrode 105 on a part except a drain region and a source region. Then, the N-type impurity is ion implanted from a direction inclined at 30-60 degrees from a perpendicular direction to a wafer, the wafer is then rotated by a predetermined angle, this is repeated a plurality timed, and a first ion implantation 107 is conducted on a part directly under the drain end of the electrode 105 and the source.drain region. Thereafter, a sidewall 109 is formed on a silicon oxide film at the side of the electrode 105. Then, a second ion implantation 111 is conducted on the source.drain region directly under the electrode 105 and the sidewall 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a source / drain region.

[0002]

2. Description of the Related Art A conventional MOS type semiconductor device manufacturing method is described in Takashi Hori, 1 / 4-μm LATID.
TECHNOROGY FOR 3.3V OPER
Ation, in IEDM Tech. Dig. , P
777,1989.

FIG. 2 is a sectional view of each main step of a conventional semiconductor device manufacturing method. That is, in the step of forming the source / drain region of the MOS type semiconductor device, 1) N type impurities are included via the gate oxide film 204 on the semiconductor substrate 201 on which the diffusion layer 202 containing low concentration P type impurities is formed. Step of forming gate electrode 205 {FIG. 2 (a)}
And 2) a step of forming the photoresist 206 in a portion other than the source / drain regions, and 3) ion implantation of N-type impurities from a direction inclined by 30 to 60 degrees with respect to the vertical direction to the wafer, and then the wafer. Is rotated by a certain angle, and this is repeated a plurality of times.
7 is performed to form a diffusion layer 208 containing a low concentration of N-type impurity immediately below both ends of the gate electrode and in the source / drain region {FIG. 2 (b)}, and 4) a sidewall 209 of silicon oxide beside the gate electrode. And 5) forming a photoresist 210 on a portion other than the source / drain region, and 6) forming a photoresist on the source / drain region other than directly below the gate electrode and a sidewall formed of silicon oxide on the side of the gate electrode. A step of forming a diffusion layer 212 containing a high concentration of N-type impurities by performing the second ion implantation 211 (FIG. 2).
(C)}.

When the source / drain region of the MOS semiconductor device is formed by such a method, a low concentration diffusion layer 202 containing P-type impurities is formed on the semiconductor substrate immediately below the central portion of the gate electrode 205, and the gate electrode 205 is formed. A low-concentration diffusion layer 208 containing N-type impurities is formed by first ion implantation on the semiconductor substrate immediately below the sidewalls 209 formed of silicon oxide on both ends of the gate electrode and on the side of the gate electrode. A high-concentration diffusion layer 212 containing an N-type impurity is formed by the second ion implantation on the semiconductor substrate other than immediately below the side wall 209 formed of silicon oxide on the side of. In such a structure, when the voltage is applied to the MOS type semiconductor device, the electric field strength at the drain end is relaxed to prevent the deterioration of the element characteristics due to the hot carrier phenomenon which occurs with the miniaturization. It is possible to suppress the leak current of the drain, which is caused by the tunnel current generated at the drain end under the influence of the electric field of the gate electrode.

[0005]

However, the conventional M
In the structure of the OS type semiconductor device, there is no effect in alleviating the electric field strength at the drain end and reducing the leak current of the drain generated by the influence of the electric field at the gate electrode. The diffusion layer 208 having a type impurity was formed on the semiconductor substrate immediately below the end of the gate electrode so as to overlap the gate electrode. Therefore, the effective channel length is shortened by the amount that the diffusion layer having a low concentration N-type impurity on the source side is formed so as to overlap the gate electrode. There is a problem that miniaturization becomes difficult and the delay time increases. Further, the diffusion layer 20 having a low concentration of N-type impurities formed on the lower portion of the sidewall and both ends of the channel portion.
Since 8 has a higher impurity concentration than the diffusion layer 202 having a low concentration of P-type impurities formed in the semiconductor substrate immediately below the central portion of the gate electrode, the diffusion layer 208 having a low concentration of N-type impurities on the source side is a gate electrode. However, there is a problem that the gate delay time becomes long because the electric capacitance of the gate electrode increases more than necessary due to the overlap.

[0006]

[Means for Solving the Problems] (Claim 1) In a step of forming a source / drain region of a MOS type semiconductor device, an N type is formed on a semiconductor substrate containing a low concentration of P type impurities through a gate oxide film. A step of forming a gate electrode containing impurities,
A step of forming a photoresist on a portion other than the drain region and a portion apart from the gate electrode end in the source region by a certain distance, and tilting the N-type impurity with respect to the wafer by about 30 to 60 degrees from the vertical direction. The ion implantation from the opposite direction, the wafer is rotated by a certain angle, and this is repeated a plurality of times to perform the first ion implantation just below the drain end of the gate electrode and the source / drain region. A step of forming a side wall with a silicon oxide film on the side and a second ion implantation to the source / drain region except immediately below the side wall formed of silicon oxide on the side of the gate electrode and the gate electrode have an N-type impurity. And a step of forming a source / drain region.

(Item 2) In the method of manufacturing a semiconductor device according to item 1, in a portion other than the drain region and a portion apart from the gate electrode end by about 0.2 μm to 1.2 μm in the source region. The first ion implantation is performed after the photoresist is formed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of each of the main steps of a method for manufacturing a semiconductor device according to the present invention.

The details will be described below by following the steps.
First, a thin thermal oxide film is formed as an ion-implanted permeable film on the surface of a semiconductor substrate 101 containing silicon as a main component, and then a P-type impurity such as boron is implanted with an implantation energy of 60 keV and a dose amount of 5 × 10 ¹² cm ⁻² to 2 ×. Ion implantation of about 10 ¹³ cm ^-2 is performed and thermal diffusion is performed to form a diffusion layer 102 containing a low concentration of P-type impurities. Next, a silicon nitride film is formed to a thickness of about 20 nm on the entire surface of the wafer by a CVD method, and the photo-etching is performed to pattern the nitride film at a predetermined location, and an element isolation oxide film 103 is formed by a thermal oxidation method. Remove. Next, a gate oxide film 104 having a thickness of about 15 nm is formed on the exposed portion of silicon in the wafer surface by a thermal oxidation method, and a P-type impurity such as boron is injected from above to an implantation energy of 30 keV to 60 keV.
The dose is about 1 × 10 ¹² cm ^-2 to 5 × 10 ¹³ cm
^The threshold voltage is adjusted by adjusting the impurity concentration on the silicon surface by performing ion implantation of about ^-2 . Then CV
A polycrystalline silicon film is formed on the entire surface of the wafer by the D method to a film thickness of about 3
The gate electrode 105 is formed by forming it to a thickness of 0 nm and performing photo-etching to form a polycrystalline silicon film at a predetermined location {FIG. 1 (a)}. Next, in the source region, a film thickness of 1.0 μ is separated from the gate electrode end by about 0.2 to 1.2 μm.
A photoresist 106 having a thickness of about m to 1.5 μm is formed. Next, the total dose amount is 1 × 10 ¹² cm ⁻² to 5 × 10 ^{14 with an} implantation energy of about 30 keV to 100 keV from a direction in which an N-type impurity such as phosphorus is inclined about 30 ° to 60 ° with respect to the vertical direction with respect to the wafer. The first ion implantation 107 is performed four times in four directions on the wafer surface so as to be about cm ⁻² (FIG. 1B). That is, the first ion implantation is performed by repeating the operation of rotating the wafer by 90 degrees after implanting a quarter of the dose amount in one ion implantation. At this time, on the drain side, the diffusion layer 108 containing N-type impurities is formed by overlapping the gate electrode end by about 0.05 μm to 0.3 μm, and on the source side, the N-type impurity is injected from the direction overlapping the gate electrode. By adjusting the distance between the photoresist and the gate electrode and the film thickness of the photoresist so that the impurities are absorbed by the photoresist formed on the side of the gate electrode, heat is applied in the subsequent process to move laterally. A low-concentration diffusion layer 108 containing N-type impurities can be formed without overlapping with the gate electrode, except for the diffusion element. As a result, the low-concentration diffusion layer 108 containing N-type impurities can be formed with the drain side overlapping with the gate electrode and the source side almost overlapping with the gate electrode. Next, a silicon oxide film having a thickness of 100 nm to 50 is formed on the entire surface of the wafer by the CVD method.
Then, the side wall 109 formed of silicon oxide is formed on the side of the gate electrode by anisotropically etching the silicon oxide film with a thickness of 0 nm.
The side wall 109 formed of silicon oxide on the side of the gate electrode is called a side wall. The sidewall formed here is 0.05 μm to 0.2 μm from the gate end.
It is formed with a width of about μm. Next, a photoresist 110 is formed in a region other than the source / drain region, and an N-type impurity such as arsenic or phosphorus is implanted with an energy of about 30.
By performing the second ion implantation 111 with a dose amount of about 5 × 10 ¹⁴ cm ⁻² to 6 × 10 ¹⁵ cm ⁻² at keV to 80 keV, N-type is formed in the source / drain region of the semiconductor substrate except immediately below the gate electrode and the sidewall. A high-concentration diffusion layer 112 containing impurities is formed {FIG. 1C}. Next, after activating the impurities implanted so far by the thermal diffusion method,
A silicon oxide film with a film thickness of 5 is formed on the entire surface of the wafer by the CVD method.
The silicon oxide film is etched by photoetching to have a thickness of about 00 nm, and a contact hole is opened. Then, a metal material containing aluminum as a main component is formed to a film thickness of about 500 nm by a sputtering method, and metal wiring is formed by photoetching. Then, a silicon nitride film is formed as a passivation film by a CVD method to have a thickness of about 800 nm, and a pad electrode is opened by photoetching.

By thus forming the MOS transistor, the P-type diffusion layer 102 is formed in the central portion of the gate electrode 105 and directly under the gate electrode on the source side, and the P-type diffusion layer 102 is formed under the end of the gate electrode on the drain side and the sidewall. A diffusion layer 108 containing a low concentration of N-type impurities is formed on the lower semiconductor substrate, and the semiconductor substrate immediately below the end of the gate electrode on the source side is formed by the lower side wall on the source side and the lateral diffusion due to thermal diffusion. A diffusion layer 108 containing a low concentration of N-type impurities is formed on the semiconductor substrate, and a high-concentration diffusion layer 112 containing N-type impurities is formed on the semiconductor substrate in the source / drain region excluding the lower portions of the gate electrode and the sidewalls. Become.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, the low concentration diffusion layer 108 containing N-type impurities is formed so as to overlap the gate electrode 105 in the region where the electric field strength is high at the drain end. Therefore, by relaxing the electric field strength, it is possible to prevent the deterioration of the device characteristics due to the hot carrier phenomenon as in the conventional case. Further, according to the method for manufacturing a semiconductor device of the present invention, since the diffusion layer 112 containing a high concentration of N-type impurities is not formed immediately below the gate electrode, the drain leakage current generated by the influence of the electric field of the gate electrode is the same as the conventional one. Can be suppressed to Further, according to the method of manufacturing a semiconductor device of the present invention, since the low concentration diffusion layer 108 containing N-type impurities is hardly formed below the end of the gate electrode on the source side, the effective channel length is reduced by the low concentration N-type. Since the diffusion layer 108 containing impurities is overlapped just below the end of the gate electrode on the drain side, the punch through phenomenon is less likely to occur than in the conventional case, and further miniaturization is possible, and the delay time is reduced. It will be possible. Further, since the diffusion layer 108 including the low concentration N-type impurity formed immediately below the gate electrode end has a higher impurity concentration than the diffusion layer 102 including the low concentration P-type impurity immediately below the gate electrode, the present invention According to the method of manufacturing a semiconductor device described above, since the diffusion layer 108 containing a low concentration of N-type impurities is hardly formed immediately below the end of the gate electrode on the source side, the electric capacitance of the gate electrode becomes smaller than in the conventional case and the gate delay is reduced. The time can be shortened.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of main steps of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of main steps of a conventional semiconductor device manufacturing method.

[Explanation of symbols]

 101, 201 ... Semiconductor substrate 102, 202 ... Diffusion layer containing low concentration P-type impurity 103, 203 ... Element isolation oxide film 104, 204 ... Gate oxide film 105, 205 ... Gate Electrodes 106, 206, 110, 210 ... Photoresist 107, 207 ... First ion implantation 108, 208 ... Diffusion layer containing low concentration N-type impurity 109, 209 ... Formed of silicon oxide Side wall 111, 211 ... Second ion implantation 112, 212 ... Diffusion layer containing high concentration N-type impurity

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8617-4M H01L 21/265 F

Claims (2)

[Claims] 1. In a process of forming a source / drain region of a MOS type semiconductor device, 1) N type impurities are diffused through a gate oxide film on a semiconductor substrate on which a diffusion layer containing a low concentration of P type impurities is formed. A step of forming a gate electrode including 2) a step of forming a photoresist on a portion other than the drain region and a portion of the source region separated from the end of the gate electrode by a certain distance; The ion implantation is performed from a direction inclined by 30 to 60 degrees with respect to the vertical direction, the wafer is rotated by a certain angle, and this is repeated a plurality of times to perform the first ion implantation. A step of forming a diffusion layer containing a low concentration of N-type impurities in the source / drain region excluding a part of the source region and immediately below the electrode end, and 4) using a silicon oxide film beside the gate electrode. A step of forming a side wall, and 5) a source having a high concentration of N-type impurities by performing second ion implantation in the source / drain region except under the side wall formed of silicon oxide beside the gate electrode and the gate electrode. And at least a step of forming a drain region. 2. A first ion implantation is performed after a photoresist is formed on a portion other than the drain region and a portion on the source region separated from the end of the gate electrode by about 0.2 μm to 1.2 μm. The method of manufacturing a semiconductor device according to claim 1.