JPH05113939A - Method and device for transferring data - Google Patents

Abstract

PURPOSE:To apply the retry processing of the OS of a CPU to any type of I/O units in the same way in regard to a system where the data are transferred to the I/O unit from the CPU. CONSTITUTION:A data transfer circuit transfers the data to an I/O unit 3 from a CPU unit 1 via a bus 2. The unit 3 contains a 1st register 4 which is connected to the bus 2 and plural 2nd registers 5 which are connected to the register 4. Then the data received from the unit 1 are once stored in the register 4 and checked there. When no error of the data is checked, the data are directly transferred to one of registers 5. Thus the transfer of data is completed. When an error of data is detected, the data are not sent to any register 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (CP
The present invention relates to a method of transferring data from U) to an input / output (I / O) unit, and more particularly to a data transfer apparatus and method for preventing the transfer of error data when a data transfer error occurs.

In the control computer system, there is a demand for a technique for operating the control computer system without causing erroneous control in response to the demand for high reliability.

In such a control computer system or the like, there are many opportunities to transfer data from the CPU to a plurality of registers in the I / O unit.

Therefore, when data is transferred from the CPU to the I / O unit, a retry process is performed by the same method for a data transfer circuit in which any type of I / O unit is mounted. It is desired to be able to write protect data to a register.

[0005]

2. Description of the Related Art FIG. 5 shows a conventional data transfer circuit, in which 11 is a CPU unit, 12 is a data bus for transferring data, and 13 is an I / O unit. I
In the / O unit 13, 14 _{1 to} 14 ₄ are registers.

In FIG. 5, the I / O unit 13 operates as an output circuit, and the data transferred from the CPU unit 11 via the data bus 12 are stored in the registers 14 _{1 to} 14 14.
It is designed to be directly received and retained by the ₄ .

FIG. 6 shows a write bus cycle when there is no data error in the data transfer circuit of FIG.

Now, when the transfer of the data N from the CPU unit 11 through the data bus 12 to the I / O unit 13 is started (), then the I / O write signal becomes "L" (), and the address is changed. Data begins to be written to the specified register. When the writing is completed, the I / O unit 13 sets the ready signal to "L" (). At the same time, the existence of an error in the data is checked by a bus parity test or the like. If there are no data errors,
NMI that notifies CPU unit 11 of an error
The (Non Maskable Interrupt) signal remains "L". The CPU unit 11 detects that the ready signal has become "L" and returns the I / O write signal to "H" (). When this is detected by the I / O unit 13, the ready signal is returned to "H" (), and the data transfer is completed.

FIG. 7 shows a write bus cycle when there is a data error in the data transfer circuit of FIG.

As in the case of FIG. 6, at the end of writing, the presence or absence of an error in the data is checked. If there is an error, the NMI signal is set to "H" (), and the error is sent to the CPU unit 11. Notify that there was. After that, as in the case of no error, the CPU unit 1
1 detects that the ready signal has become “L” and
When the O write signal is returned to "H" (), and the I / O unit 13 detects this, the ready signal is returned to "H" (), and the data transfer is completed.

[0011]

In the conventional data transfer method, even if an error is detected by the data check, the data is already written in the register at that time. It is necessary to perform a retry process in (OS) and write data again.

However, the configuration of the I / O unit is
Not only the simple one as shown in FIG. 5 but also another one having a different configuration.

FIG. 8 shows the structure of another conventional I / O unit, in which 15 is an I / O unit and 16 ₁
˜16 ₄ are registers. In the I / O unit shown in FIG. 8, only the register 16 ₁ has the data bus 12
And registers 16 _{2 to} 16 ₄ are connected to register 16 ₁
It is designed to be connected via the internal bus from.

FIG. 9 is a diagram for explaining generation of internal addresses in the I / O unit of FIG. 8, where (a) shows selectors and (b) shows address distribution.

In the I / O unit shown in FIG. 5, the CP
Since the data from the U unit is sent directly to each register,
Two address lines are required. On the other hand, I shown in FIG.
In the / O unit, the register 16 ₁ once receives the data, and 2 of the data D _{15 to} D ₀ shown in FIG.
Bits D _{1 and} D ₀ are used as selectors to specify the addresses of the other registers 16 _{2 to} 16 ₄ as shown in (b) to transfer data. Therefore, in this case, only one address line is required to transfer data from the CPU unit to the I / O unit.

When the I / O unit as shown in FIG. 8 is mounted on the data transfer circuit in a mixed manner with other types of I / O units, the OS of the CPU unit operates in the data transfer circuit. If it is not known in advance which IC configuration of which I / O unit has which register configuration, the retry process cannot be performed. However, since the ICs of a large number of I / O units are usually mounted in the data transfer circuit, it is difficult to control them separately even if there are I / O units of different configurations. However, there is a problem that the retry process cannot be performed by the OS.

The present invention is intended to solve the problems of the prior art as described above.
An object of the present invention is to provide a data transfer device and method capable of performing retry processing in the same method for any type of I / O unit in a data transfer circuit for transferring data to an O unit.

[0018]

A data transfer apparatus of the present invention is a data transfer circuit for transferring data from a CPU unit to an I / O unit via a bus, and a first I / O unit connected to the bus. And a plurality of second registers connected to the first register,
The data sent from the U unit is temporarily held in the first register for data check, and if there is no error, this data is sent as it is to any one of the second registers to end the data transfer and the error is detected. If there is, this data is not sent to the second register.

According to the data transfer method of the present invention, in the data transfer circuit for transferring data from the CPU unit to the I / O unit via the bus, the data sent from the CPU unit is temporarily held in the first register via the bus. Data check is performed, and if there is no error, this data is sent as it is to any of the second registers to end the data transfer, and if there is an error, this data is not sent to the second register, It is characterized in that a retry process is performed by the OS of the CPU unit and data writing to the first register is tried again.

[0020]

FIG. 1 shows the principle of the present invention. In the data transfer circuit, data is transferred from the CPU unit 1 to the I / O unit 3 via the bus 2. In this case, the data transfer apparatus according to the present invention uses the I / O unit 3
, A first register is provided to connect to the bus 2, and a plurality of second registers 5 are provided to connect to the first register 4. Then, the data sent from the CPU unit 1 is temporarily held in the first register 4 to perform a data check, and if there is no error, this data is sent as it is to any one of the second registers 5 for data transfer. To finish.
On the other hand, when there is an error, this data is not sent to the second register 5. Therefore, according to the present invention,
When an error occurs, the retry process can be performed on any type of I / O unit by the same method.

Further, in the data transfer method of the present invention, in the above-mentioned data transfer circuit, the data sent from the CPU unit 1 is temporarily held in the first register 4 via the bus 2 and data check is performed, and there is no error. At this time, this data is sent as it is to any one of the second registers 5 to end the data transfer. When an error occurs, the OS of the CPU unit 1 performs retry processing without sending this data to the second register 5, and the first register 4 again.
Since an attempt is made to write data to the I / O unit, a retry process can be performed on any type of I / O unit by the same method when an error occurs.

[0022]

FIG. 2 shows the configuration of an embodiment of the present invention, in which the same elements as those in FIG. 5 are designated by the same reference numerals, and 21 is an I / O unit. I / O unit 21
In the above, 22 is a first register, and 23 ₁ to 23 ₄ are second registers.

In the data transfer circuit shown in FIG. 2,
The I / O unit 21 operates as an output circuit, and the data transferred from the CPU unit 11 via the bus 12 is temporarily held in the first register 22 to perform a data check, and then the second register 23 ₁ It is adapted to be transferred to one of the to 23 _4.

FIG. 3 shows a write bus cycle when there is no data error in the data transfer circuit of FIG.

Now, when the transfer of the data N from the CPU unit 11 through the data bus 12 to the I / O unit 21 is started (), then the I / O write signal becomes "L" (), and the first The data starts to be written in the register 22 of. When the writing is completed, the I / O unit 21 sets the ready signal to "L" (). At the same time, the existence of an error in the data is checked by a bus parity test or the like. If there is no data error, the NMI signal notifying the CPU unit 11 of the error is “L”.
It remains. At this time, the data in the first register 22 is transferred to any of the second registers designated by the address (). The CPU unit 11 detects that the ready signal has become "L" and returns the I / O write signal to "H" (). When this is detected by the I / O unit 21, the ready signal is returned to "H" () and the data transfer is completed.

FIG. 4 shows a write bus cycle when there is a data error in the data transfer circuit of FIG.

As in the case of FIG. 3, at the end of writing, the presence or absence of an error in the data is checked, and if there is an error, the NMI signal is set to "H" (), and the error is sent to the CPU unit 11. Notify that there was. At this time, the data in the first register 22 is not transferred to the second register (). After that, similarly to when there is no error, the CPU unit 11 detects that the ready signal has become “L”, returns the I / O write signal to “H” (), and returns this to the I / O unit. When 21 detects, the ready signal is returned to "H" (). After that, a retry process is performed by the OS of the CPU unit 11, and the first
The writing of data to the register 22 is attempted.

As described above, in the data transfer apparatus and method of the present invention, the data is temporarily held in the first register for error check, and if there is an error, the data is not transferred to the second register. , The OS performs the retry process and then transfers it to the second register, so that the OS can perform the retry process with the same method regardless of the configuration of the second register.

In the embodiment of FIG. 2, the I / O unit 21 is used as the output circuit, but if there are many I / O units,
Other units may be used as the output circuit. Further, although the error notification to the CPU unit 11 is performed by the NMI signal, a method of monitoring the ready signal of the CPU unit 11 by time may be used. In this case, when an error is found in the data check, the ready signal is not returned to the CPU unit 11, and the CPU unit 11 does not return the ready signal within a certain period of time. Error notification is given.

[0030]

As described above, according to the present invention, C
In the data transfer circuit for transferring data from the PU unit to the I / O unit, when an error occurs, it is possible to perform the retry process on the register of the I / O unit having any structure by the same method. The reliability of the control computer can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a write bus cycle when there is no data error in the data transfer circuit of FIG.

FIG. 4 is a diagram showing a write bus cycle when there is a data error in the data transfer circuit of FIG.

FIG. 5 is a diagram showing a conventional data transfer circuit.

6 is a diagram showing a write bus cycle when there is no data error in the data transfer circuit of FIG.

7 is a diagram showing a write bus cycle when there is a data error in the data transfer circuit of FIG.

FIG. 8 is a diagram showing a configuration of another conventional I / O unit.

9A and 9B are diagrams for explaining generation of an internal address in the I / O unit of FIG. 8, in which FIG. 9A shows a selector,
(B) shows distribution of addresses.

[Explanation of symbols]

 1 CPU unit 2 Bus 3 I / O unit 4 First register 5 Second register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Kanda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (2)

[Claims] 1. A data transfer circuit for transferring data from a CPU unit (1) to an I / O unit (3) via a bus (2), wherein the I / O unit (3) is connected to the bus (2). A first register (4) and a plurality of second registers (5) connected to the first register (4) are provided, and the data sent from the CPU unit (1) is temporarily stored in the first register (4). Data is checked by holding it in the first register (4), and when there is no error, the data is directly sent to any of the second registers (5) to end the data transfer, and when there is an error, A data transfer device, characterized in that the data is not sent to the second register (5). 2. A data transfer circuit for transferring data from a CPU unit (1) to an I / O unit (3) via a bus (2), wherein data sent from the CPU unit (1) is transferred to a bus (2). After that, the data is temporarily held in the first register (4) to check the data, and if there is no error, the data is directly sent to any one of the second registers (5) to end the data transfer, and at the same time, there is an error. When this happens, the CPU does not send the data to the second register (5).
A data transfer method characterized in that a retry process is performed by the OS of the unit (1) and data writing to the first register (4) is tried again.