JPH05111051A - Cross color suppressing circuit and television receiver - Google Patents

Abstract

PURPOSE:To prevent the generation of a dot fault due to traversal trunk and to improve a cross color suppressing effect, in respect to a comb filter for separating a composite video signal into a luminance signal and a chroma signal. CONSTITUTION:Delay circuits 32 to 35 for delaying each chroma signal only by a half of wavelength are cascade-connected and minimum value circuits 38 to 42 each of which extracts the minimum value of specific three signals out of plural output signals from respective delay circuits 32 to 35 and minimum value circuits 43 to 45 each of which extracts the minimum value of specific two signals are connected. A chroma signal and a luminance signal are respectively obtained from output terminals 47, 52 through maximum value circuits 46, 49 for detecting the maximum output of outputs from respective minimum value circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross color suppression circuit constructed by using inter-line comb filters and a television receiver having this circuit.

[0002]

2. Description of the Related Art A video signal detected by a tuner in a television receiver is a signal in which a luminance signal, a color signal, a horizontal and vertical synchronizing signal, etc. are combined into one. Various YC separation circuits are used to separate a luminance signal (Y signal) and a color signal (chroma signal or C signal) from a video signal. Among them, in the method using the inter-line comb filter, the Y signals of two continuous scanning lines having line correlation have the same phase and the C signal has the opposite phase. Therefore, by adding and subtracting both signals, Y signals are respectively obtained. The signal and the C signal are separated.

However, the YC separation using such a comb-shaped filter has a drawback that the resolution is deteriorated with respect to a dot obstacle or a slender thin line unless there is a perfect line correlation. That is, if there is no line correlation, the separated Y signal and C signal also include other signal components, and a cross color suppression circuit is used to remove these signals.

FIG. 4 is a block diagram showing an example of a conventional cross color suppression circuit. In the cross color suppression circuit shown in this figure, the input terminal 1 is an input section for a chroma signal (C signal) output by an interline comb filter. To the input terminal 1, four delay circuits (T) 2, 3, 4, 5 are connected in series. Each delay circuit 2, 3, 4, 5 is C
This is a circuit for delaying a signal by a half cycle period of the signal, and inverting circuits 6 and 7 are connected to output terminals of the delay circuits 2 and 4, respectively.

Next, five minimum value circuits (MIN) 8, 9, 10, 11, 12 for inputting each delayed signal are provided. Each of these minimum value circuits has three input terminals, detects the minimum signal of the signals input to each input terminal, and selects and outputs the minimum signal. Of these, the minimum value circuit 8 is given the respective signals of the input terminal 1, the inverting circuit 7, and the delay circuit 5 of the C signal. Similarly, each signal of the input terminal 1, the inverting circuit 6, and the delay circuit 5 is input to the minimum value circuit 9. The minimum value circuit 10 is supplied with signals from the input terminal 1, the inverting circuit 6, and the delay circuit 3. The minimum value circuit 11 is supplied with signals from the inverting circuits 6 and 7 and the delay circuit 3. Then, the minimum value circuit 12 is given the signals of the delay circuits 3, 5, and the inverting circuit 7.

Next, each output of the minimum value circuits 8 to 12 is given to the maximum value circuit (MAX) 13. The maximum value circuit 13 selects and outputs the signal having the maximum amplitude among the input signals. The output of the maximum value circuit 13 is the subtracter 14 and C
The signal is output to the output terminal 15. The subtractor 14 has an input terminal 1
6 is a circuit for subtracting the output signal of the maximum value circuit 13 from the composite video signal input from 6, and its output is given to the output end 17 of the Y signal.

The operation of the conventional cross color suppression circuit configured as described above will be described. 5 to 8 are shown in FIG.
It is a waveform diagram which shows the waveform of each part of a of. First, consider the operation when the sine wave of one cycle of the C signal shown in a of FIG. 5 is input to the input terminal 1 of FIG. The sine wave input to the input terminal 1 is delayed by half cycles by the delay circuits 2, 3, 4, and 5, and the signals having the waveforms shown by b, c, d, and e in FIG. 5 are output. The inverting circuits 6 and 7 output the signals shown in f and g of FIG. The signals shown in a, e, and g of FIG. 5 are input to the minimum value circuit 8, and at the first time T1, the signals of e and g are 0, and the signal of a changes on the + side. Therefore, the minimum value of the three signals becomes 0 at time T1, and a signal of 0 output is output at time T1 as shown by h. Next, at time T2, the signals e and g are 0, and the signal a changes at the − side. Therefore, the signal of a becomes the minimum, and the minimum value circuit 8
At the output of, the waveform of the time T2 portion of the signal of a is obtained.
Similarly, at time T3, 0 output, at time T4, the signal g is selected, becomes 0 at time T5, and at time T6.
Then, the signal e is selected, and the output signal shown in h is obtained.

Next, in the minimum value circuit 9, the signals shown in a, e, and f of FIG. 5 are input, and the signal having the minimum level is selected at each time T1 to T7, and the signal shown in i of FIG. can get. Similarly, the minimum value circuits 10, 11 and 12 output the signals indicated by j, k and l in FIG.

Next, in the maximum value circuit 13, h, i,
Of the five signals indicated by j, k, and l, each time T1 to T7
The signal with the highest level at is selected. Time T
At 1, each of the signals indicated by h, i, j, k, and 1 is 0 level, so that the output is also 0 level. At time T2, the 0 level signal of 1 is selected. Similarly, time T
Since any one of the five input signals is 0 level in each section from 3 to time T7, the output of the maximum value circuit 13 is always 0 level as indicated by m. That is, even if the sine wave of one cycle shown in a of FIG. 5 is input to the input end 1 of the cross color suppression circuit shown in FIG. 4, no signal is output from the output end 15.

FIG. 6 is an explanatory diagram of waveform processing when a sine wave of 1.5 cycles is input to the cross color suppression circuit shown in FIG. The description of the operation in this case is the same as that in the case where the waveform shown in FIG. 5 is input, and thus detailed description will be omitted. In the minimum value circuit 10, since the signals a, c, and f all change on the + side at the time T3, the minimum value does not reach 0 level, but changes on the + side as indicated by j in FIG. Signal is obtained. Similarly, at the output of the minimum value circuit 12, the signals c, e, and g are output as they are at time T5. Then, the maximum value circuit 13 outputs a signal as indicated by m. In the above waveform processing, 1.
When a sine wave of 5 cycles is input to the cross color suppression circuit of FIG. 4, it is delayed by 1 cycle and output as it is.

FIG. 7 and FIG. 8 are waveform charts of respective parts when a sine wave whose amplitude changes and continues for several cycles is input. When the signal shown in a of FIG. 7 is input to the input terminal 1 of FIG. 4, the signals shown in b, c, d, and e of FIG. 7 are obtained at the outputs of the delay circuits 2, 3, 4, and 5, and inverted. The outputs of the circuits 6 and 7 are the signals shown in f and g. In this case also, the same signal processing as in FIGS. 5 and 6 is performed, and the signals shown in h, i, j, k and l of FIG. 8 are obtained at the outputs of the minimum value circuits 8, 9, 10, 11, and 12. Be done. In the maximum value circuit 13, the signals of h, i, j become − level at times T1, T2, and the signals of k, l become maximum at 0 level. Therefore, the 0-level output is obtained from the maximum value circuit 13. At time T3, the signal of l is the maximum, and at time T4
The signal of j is maximum, the signal of l is maximum at time T5, and the signals of h, i, j, k, and l are maximum at time T6, and the maximum signal of each period is also similarly at time T7 to time T10. Are output respectively. Therefore, the signal shown by m in FIG. 8 is obtained from the output terminal 15 of the cross color suppression circuit. This output signal is a signal having the same wave number as the input signal of a and a part of the amplitude reduced.

Here, at the input terminal 16 of the subtractor 14, c in FIG.
When a composite video signal with the same waveform as the signal shown in is input,
Since the signal indicated by m in FIG. 9 is subtracted from this signal, the signal indicated by n in FIG. 9 is output from the output terminal 17. As described above, in the cross color suppression circuit shown in FIG. 2, when a signal corresponding to one cycle of the chroma signal as shown in a of FIG. 5 is input to the input terminal 1, the signal as shown in m of FIG. Is not output. On the other hand, when a signal for 1.5 cycles of the chroma signal as shown in a of FIGS. 6 and 7 is input to the input terminal 1,
As indicated by m in FIG. 8, the chroma signal is directly output to the output end 15. That is, in the conventional cross color suppression circuit configured as shown in FIG. 2, only signals having a period of 1.5 cycles or more are regarded as chroma signals, and signals shorter than that are not regarded as chroma signals. As a result, it is possible to suppress the cross color in the thin diagonal line portion of the luminance signal without changing the rise time of the chroma signal.

Next, another conventional cross color suppression circuit will be described. FIG. 9 is a block diagram showing the configuration of this cross color suppression circuit. The input terminal 11 is an input section for the chroma signal (C signal) output from the interline comb filter. Two delay circuits 12 and 13 are connected in series to the input terminal 11. Each of the delay circuits 12 and 13 is a circuit that delays the signal by the half cycle period of the C signal. Further, the inverting circuits 14 and 15 are provided at the input terminal 11 and the output terminal of the delay circuit 13.
Are connected.

Next, three minimum value circuits 16, 17, and 18 for inputting each delayed signal are provided. These minimum value circuits have two input terminals, detect the minimum signal of the signals input to each input terminal, and select and output the signal. The minimum value circuit 16 is given the respective signals of the inverting circuits 14 and 15. Similarly, the minimum value circuit 17 is given the respective signals of the inverting circuit 14 and the delay circuit 12. The minimum value circuit 18 is given the signals of the delay circuit 12 and the inverting circuit 15.

Next, the respective outputs of the minimum value circuits 16, 17 and 18 are given to the maximum value circuit 19. The maximum value circuit 19 is shown in FIG.
Is the same as the maximum value circuit 13 of FIG.
Is applied to one input end of the signal and the output end 21 of the C signal. The subtractor 20 is a circuit that subtracts the C signal of the maximum value circuit 19 from the composite video signal input from the input end 22, and the output thereof is output as the Y signal via the output end 23.

Waveform processing when sine waves having different wave numbers are input in the cross color suppression circuit configured as described above will be described with reference to FIGS. Figure 10
FIG. 10 is a waveform diagram when a half cycle sine wave is input to the input terminal 11 of the cross color suppression circuit shown in FIG. 9. 10a
, The delay circuits 12 and 13 b,
The signal shown in c is obtained. Further, the signals indicated by d and e are obtained from the inverting circuits 14 and 15. Therefore, the minimum value circuit 16,
The signals f, g, and h are output to the outputs of 17 and 18, and the signal of i is output to the output of the maximum value circuit 19. Therefore, even if a half cycle sine wave is input to the input end 11, no signal is output to the output end 21 of the cross color suppression circuit of FIG.

Next, FIG. 11 is a waveform diagram when one cycle of a sine wave is input to the input terminal 11. In this case, when the signal shown in a is input, the same waveform as the original signal delayed by a half cycle is output to the output end 21 as shown in i.

FIG. 12 is a waveform diagram when a sine wave whose amplitude changes for several cycles is input. When a signal of the waveform indicated by a is input to the input terminal 11 of the cross color suppression circuit,
Similar to FIGS. 7 and 8, the output of the maximum value circuit 19 is shown in FIG.
The signal indicated by i in 2 is output. In this case, the same waveform as the input signal can be obtained. On the other hand, the input terminal 22 of the subtractor 20
When a signal having the same waveform as that of b in FIG. 12 is input as the composite video signal, the signal shown in i is subtracted from this signal. Therefore, the output of the subtracter 20 is an alternating current as shown in j in FIG. A 0 level signal from which the components have been removed is output.

[0019]

However, in the cross color suppression circuit of FIG. 4, when the C signal of one cycle is input, this signal is suppressed, but when the C signal of 1.5 cycles or more is input. It is output without being suppressed. Therefore, the circuit of FIG. 4 can suppress the cross color of a thin diagonal line. On the other hand, when a C signal of several cycles is input as shown in a of FIG. 7, a C signal with a part of reduced brightness is output as shown in m of FIG. Further, there is a drawback in that the C signal, which should not be originally output, is output to the output end 17 of the Y signal as the waveform shown by n in FIG. 8, resulting in dot failure.

Further, in the cross color suppression circuit of FIG.
When a C signal of several cycles is input as shown in 2a,
As indicated by i in 2, the original C signal whose brightness is not reduced is output. Further, as shown by j in FIG. 12, the C signal is not mixed into the output end 23 of the Y signal, and as a result, the dot trouble does not occur. On the other hand, the circuit of FIG.
0, as shown in FIG. 11, a signal of 1 cycle or more is regarded as a C signal, and therefore a signal of 1.5 cycles or more is regarded as a C signal.
There is a drawback that the effect of suppressing cross color is less than that of the suppressing circuit of.

The present invention has been made in view of such conventional problems. Even if a chroma signal of several cycles is input, there are few dot defects, and the effect of suppressing cross color can be obtained. Another object of the present invention is to provide a cross color suppression circuit which has the advantages of the circuit of FIG.

[0022]

According to the present invention, a first delay circuit for inputting a band-limited chroma signal and delaying the signal by a half cycle time of the chroma signal has the same characteristics as the first delay circuit. And second, third, and fourth delay circuits that are cascade-connected to the output terminal of the first delay circuit, and first and second inverting circuits that invert the output signals of the first and third delay circuits When,
The output signals of the second delay circuit, the fourth delay circuit, the first inverting circuit, and the second inverting circuit, and three different signals of the input chroma signal are input, and a signal having the minimum level is output. Of the output signals of the first to fifth minimum value circuits and the second delay circuit, the first inverting circuit, and the second inverting circuit. The sixth to eighth minimum value circuits for outputting and the first
-The 1st maximum value circuit which selects the signal which has the maximum level of each output signal of the 5th minimum value circuit, and outputs a chroma signal, and the maximum level of each output signal of the 6th-8th minimum value circuits A second maximum value circuit for selecting a signal having the following, and a subtractor for subtracting an output signal of the second maximum value circuit from a composite video signal input from the outside to output a luminance signal. It is a feature.

[0023]

According to the present invention having such characteristics, when the band-limited chroma signal is input to the first, second, third and fourth delay circuits connected in cascade, the half cycle time of the chroma signal is reduced. However, the signals are delayed respectively. Next, the first to fifth minimum value circuits have a minimum level by inputting three specific signals from the output signals of the second and fourth delay circuits and the output signals of the first and second inverting circuits. The signal is selected, and the sixth to eighth minimum value circuits input two specific signals of each output signal and select the signal having the minimum level. Then, the first maximum value circuit selects a signal having the maximum level of each output signal of the first to fifth minimum value circuits, and the second maximum value circuit outputs each output of the sixth to eighth minimum value circuits. Select the signal with the highest level of signal. The subtractor subtracts the output signal of the second maximum value circuit from the composite video signal input from the outside, and outputs the luminance signal in which the chroma signal is suppressed. The first maximum value circuit outputs only the chroma signal.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a cross color suppression circuit according to an embodiment of the present invention. In the figure, an input terminal 31 is an input section for a band-limited chroma signal (C signal) output by an interline comb filter. The input terminal 31 has the first to fourth delay circuits 32, 3
3, 34 and 35 are connected in series. Each delay circuit 32 to
Reference numeral 35 is a circuit for delaying the signal by half a cycle of the C signal. The delay circuit 32 and the delay circuit 34 have first and second delay circuits.
The inverting circuits 36 and 37 are connected.

Next, first to eighth minimum value circuits 38 to 45 for inputting the respective delayed signals are provided respectively. The minimum value circuits 38 to 42 have three input terminals, and select and output the minimum signal of the input signals. The minimum value circuit 43-
45 has two input terminals, and selects and outputs the minimum signal of the input signals.

The signals of the inverting circuit 37, the delay circuit 35 and the input terminal 31 are applied to the minimum value circuit 38. Further, each signal of the delay circuit 35, the input terminal 31, and the inverting circuit 36 is given to the minimum value circuit 39. The minimum value circuit 40 has an input terminal 31,
Each signal of the inverting circuit 36 and the delay circuit 33 is given. The signals of the inverting circuits 36 and 37 and the delay circuit 33 are applied to the minimum value circuit 41, respectively. The signals of the delay circuits 33 and 35 and the inverting circuit 37 are given to the minimum value circuit 42, respectively.

On the other hand, the minimum value circuit 43 includes an inverting circuit 37,
Each signal of the delay circuit 33 is given, the minimum value circuit 44 is given each signal of the delay circuit 33 and the inverting circuit 36, and the minimum value circuit 45 is given each signal of the inverting circuits 36 and 37. Next, the respective output signals of the minimum value circuits 38 to 42 are given to the first maximum value circuit 46. The maximum value circuit 46 selects and outputs the signal having the maximum amplitude among the five input signals, and outputs the C signal via the output terminal 47.

Next, the outputs of the minimum value circuits 43 to 45 are output to the second
To the maximum value circuit 49. The maximum value circuit 49 selects the signal having the maximum amplitude from the three input signals and supplies the output to the subtractor 50. The subtractor 50 subtracts the output signal of the maximum value circuit 49 from the composite video signal input to the input end 51, and outputs the Y signal from the output end 52.

The operation of the cross color suppression circuit of the present embodiment having such a configuration will be described. Each delay circuit 3
2 to 35, minimum value circuits 38 to 45, and maximum value 46,
The waveform processing operation at 49 is the same as the waveform processing at the circuits of FIGS. 4 and 9, and therefore the description of the waveform processing at the input end and the output end of each circuit is omitted, and the input end 31 of FIG.
The operation of signal processing after the output terminals of the maximum value circuits 46 and 49 when a signal is input to will be described.

2 and 3 are diagrams showing output waveforms when sine waves of different periods are input to the cross color suppression circuit of FIG. As shown in FIG. 2A, the input terminal 31 of FIG.
When the C signal of the cycle is input, the signal processing in this case is the same as the waveform processing of the cross color suppression circuit of FIG. 4, so that no signal is output to the output end 47 of the C signal. On the other hand, as shown in FIG. 2B, the C signal of 1.5 cycles is input terminal 3
When it is input to 1, the input signal is directly output to the output terminal 47 as in the case of FIG. That is, in the cross color suppression circuit of the present embodiment, only signals having a period of 1.5 cycles or more are regarded as C signals, and signals shorter than that are not regarded as C signals.
Therefore, even if a thin diagonal line is input to the screen on the imaging side, the C signal is not output to the output end 47 of the chroma signal, and the cross color in the diagonal line portion of the Y signal is not changed without changing the rise time of the C signal. Can be suppressed.

Next, as shown in FIG. 3A, when a C signal of several cycles is input to the input end 31, the C signal is input in the same manner as in the case of the waveform processing from the input end 1 to the output end 15 in FIG. As shown in FIG. 3B, a C signal having a sine wave having the same period as the input signal is output to the output terminal 47 of the. On the other hand, the subtractor 50
A composite video signal having the same waveform as that of FIG. Further, the output signal of the maximum value circuit 49 becomes the signal shown in FIG. 3C, as in the case of the waveform processing of the cross color suppression circuit of FIG. Therefore, the subtractor 50
No signal is output to the output terminal 52 of the Y signal as shown in FIG. That is, the C signal is not mixed with the Y signal, and the dot trouble is prevented.

As described above, the conventional cross color suppression circuit shown in FIG. 9 is superior in terms of dot disturbance, and the cross color suppression circuit shown in FIG. 4 is superior in terms of the cross color suppression effect. The suppression circuit has the effect of having the advantages of both. Incidentally, FIG.
It goes without saying that the delay circuits, the minimum value circuits, and the maximum circuits shown in (3) can be realized by analog elements or digital elements, respectively.

[0033]

As described in detail above, according to the present invention, a narrow chroma signal is input by using the two types of cross color suppression circuits shown in FIGS. 4 and 9 in combination. Sometimes dot failure can be prevented.
Further, it is possible to suppress the cross color in the thin diagonal line portion of the luminance signal, and it is possible to realize an excellent cross color suppressing circuit that separates and outputs the luminance signal and the chroma signal. If the cross color suppression circuit of this embodiment is connected to the output terminal of the interline comb filter of the television receiver, the cross color is effectively suppressed and a high quality color image is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cross color suppression circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram (No. 1) showing input / output signals of the cross color suppression circuit according to the present exemplary embodiment.

FIG. 3 is a waveform diagram (No. 2) showing input / output signals of the cross color suppression circuit according to the present exemplary embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional cross color suppression circuit (type 1).

5 is a waveform diagram (No. 1) showing input / output signals of the cross color suppression circuit of FIG.

FIG. 6 is a waveform diagram (No. 2) showing input / output signals of the cross color suppression circuit of FIG.

7 is a waveform diagram (3) showing input / output signals of the cross color suppression circuit of FIG.

8 is a waveform diagram (No. 4) showing input / output signals of the cross color suppression circuit of FIG.

FIG. 9 is a block diagram showing a configuration of a conventional cross color suppression circuit (type 2).

10 is a waveform diagram (No. 1) showing input / output signals of the cross color suppression circuit of FIG.

FIG. 11 is a waveform diagram (No. 2) showing input / output signals of the cross color suppression circuit of FIG.

12 is a waveform diagram (No. 3) showing input / output signals of the cross color suppression circuit of FIG.

[Explanation of symbols]

1, 11, 31 Input ends 2-5, 12, 13, 32-3
5 Delay circuit 6,7,14,15,36,37 Inversion circuit 8-12,16-18,38-45 Minimum value circuit 13,19,46,49 Maximum value circuit 14,20,50 Subtractor 15,17 , 21, 23, 47, 51 Output end

Claims (2)

[Claims] 1. A first delay circuit for inputting a band-limited chroma signal and delaying the signal by a half cycle time of the chroma signal; and a first delay circuit having the same characteristics as the first delay circuit. Second, third, and fourth delay circuits connected in cascade to the output terminal of the delay circuit; first and second inverting circuits that invert the output signals of the first and third delay circuits; Each of the output signals of the second delay circuit, the fourth delay circuit, the first inverting circuit, and the second inverting circuit and three different signals of the input chroma signal are input, and a signal having the minimum level is output. Of the output signals of the first to fifth minimum value circuits and the second delay circuit, the first inverting circuit, and the second inverting circuit, two different signals are input and a signal having the minimum level is input. Sixth to eighth minimum value circuits for outputting, and the first to fifth minimum values A first maximum value circuit which selects a signal having the maximum level of each output signal of the circuit and outputs a chroma signal, and a signal which has the maximum level of each output signal of the sixth to eighth minimum value circuits is selected. And a subtractor that subtracts the output signal of the second maximum value circuit from the composite video signal input from the outside to output a luminance signal. Color suppression circuit. 2. A television receiver including the cross color suppression circuit according to claim 1.