JP3034664B2 - Beat suppression circuit and television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a beat suppressing circuit using a comb filter between lines, and a television receiver incorporating the circuit.

[0002]

2. Description of the Related Art A composite video signal detected by a tuner in a television receiver is a composite signal of a luminance signal, a chromaticity signal, a horizontal / vertical synchronization signal, and the like. Various YC separation circuits are used to separate a luminance signal (Y signal) and a color signal (chroma signal or C signal) from a composite video signal. In the method using the interline comb filter, the Y signal of two continuous scanning lines having a line correlation is in phase and the C signal is in opposite phase. The signal and the C signal are separated.

Next, an example of a conventional interline comb filter will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of a conventional interline comb filter. The input terminal 1 is an input terminal for a video signal in which a Y signal and a C signal are combined. Input 2 is one horizontal scanning period (1H) delaying an input terminal and inputs the image signal obtained by inverting the <br/> phase. The input terminal 3 is an input terminal for a video signal delayed by 2H. The minimum value circuits (MIN) 4 and 5 are circuits for inputting two different video signals among the three video signals input to the input terminals 1, 2 and 3, and selecting the minimum signal. Maximum value circuits (MAX) 6 and 7 are circuits for inputting two specific video signals among these three video signals and selecting the maximum signal. The minimum value circuit 4 selects and outputs the minimum signal from the input signals to the input terminals 1 and 2. The minimum value circuit 5 selects the minimum signal from the input signals of the input terminals 2 and 3. The maximum value circuit 6 selects a signal having the maximum amplitude from the input signals of the input terminals 2 and 3. The maximum value circuit 7 selects a signal having the maximum amplitude from the input signals of the input terminals 1 and 2.

The outputs of the minimum value circuits 4 and 5 are output to the maximum value circuit 8
And the minimum value circuit 9. The outputs of the maximum value circuits 6 and 7 are supplied to a minimum value circuit 10 and a maximum value circuit 11, respectively. Next, the outputs of the minimum value circuit 9 and the maximum value circuit 11 are given to the arithmetic circuit 12. The arithmetic circuit 12 outputs a signal obtained by averaging two input signals.

Next, among the three signals output from the maximum value circuit 8, the minimum value circuit 10, and the arithmetic circuit 12, there are provided minimum value circuits 13, 14, 15 for inputting two different signals. The minimum value circuit 13 includes the maximum value circuit 8 and the arithmetic circuit 12.
Is to select the minimum signal. Also minimum value circuit 1
Reference numeral 4 denotes a circuit for detecting the minimum signal of the arithmetic circuit 12 and the minimum value circuit 10, and the minimum value circuit 15
And the minimum signal among the maximum value circuits 8. Next, the maximum value circuit 16 is divided into three minimum value circuits 13, 1
A maximum signal is selected and output from the output signals 4 and 15, and a chroma signal is output via an output terminal 17.

[0006] In the interline comb filter configured as described above, when a composite video signal is input, a Y signal and a C signal are input.
The C signal is output from the output terminal 17. Generally, in the case of an image having a single color that is vertically different from a specific horizontal scanning line in a frame, when a color signal of the boundary line is input, the correlation between the lines is lost at the boundary of the scanning line. For this reason, the C signal bleeds in the vertical direction, and a pseudo signal that becomes a fine point in the Y signal appears. This pseudo signal has a dot shape, and a dot failure occurs. However, if the interline comb filter shown in FIG. 4 is used, it is possible to suppress the dot failure at the boundary between the colors in the vertical direction and to suppress the signal deterioration at the upper and lower ends of the multiburst signal.

[0007]

However, in the interline comb filter having such a configuration, a problem arises when a video signal having an oblique line having a period close to the color subcarrier is input into a frame. FIG. 5 is an explanatory diagram showing a signal waveform output by the above-described interline comb filter when a video signal having a pattern having oblique lines in a frame is input. When a video signal of a pattern having a plurality of thin oblique lines in a frame is input as shown in FIG. 5A, the video signal obtained from the adjacent scanning lines L1, L2, and L3 becomes a broken line in FIG. As shown by, the signals are sinusoidal signals delayed from each other. In order to digitally process these signals, the amplitude of the video signal is sampled at a clock cycle, and the amplitude is held for the time of the clock cycle to obtain a signal having a step-like waveform as shown by a solid line. When these signals are inputted to the interline comb filter shown in FIG. 4, a signal as shown in FIG. If a circuit (not shown) subtracts the signal shown in FIG. 5C from the composite video signal and outputs the Y signal, an interference fringe equal to the clock cycle appears in the Y signal, degrading the quality of the video. Had problems.

The present invention has been made in view of such a conventional problem. When a video signal having an oblique line pattern is input, a signal serving as an interference fringe is not output.
In the case of a video signal containing a normal color signal, a beat suppression circuit capable of obtaining a high-quality video by faithfully outputting a color signal, and a television receiver incorporating the circuit are provided. The purpose is to:

[0009]

According to a first aspect of the present invention, an A / D conversion is performed using a sampling clock having a rate that divides one wavelength period of a chroma signal into 2N equal parts (N ≧ 3), and passes through a comb filter between lines. The subsequent digital chroma signal is used as an input signal, and the input signal alternately increases and decreases every clock during the N clock periods of the sampling clock.
When detecting the decrease repetition, it outputs the H level,
In other cases, it is determined whether or not the output signal of the vibration detection unit that outputs the L level is at the H level for more than a majority of the clock periods of the N clock periods of the sampling clock, a majority decision circuit for outputting the H level if the level, a multiplier for attenuating a delayed signal of the digital chroma signal, the majority circuit unit
Outputs the multiplier output signal when the control signal from is high
When the control signal is L, the digital chroma output signal is delayed.
And a changeover switch for outputting an extended signal, wherein the changeover switch outputs a chroma signal.

Further, in the invention of claim 2 of the present application, the vibration detecting section receives the digital chroma signal after passing through the interline comb filter as an input signal, and delays the signal by one clock period; A comparator for comparing the chroma signal with an output signal of the first delay circuit and outputting an H or L level signal; and a cascade- connected second and third cascade connection for delaying the output signal from the comparator for one clock period. A delay circuit;
Of the output signals of the comparator and the second and third delay circuits,
First and second outputs an exclusive OR of two different signals
An exclusive OR circuit; a first AND circuit that outputs a logical product of output signals of the first and second exclusive OR circuits;
Wherein the majority circuit section includes cascaded fourth and fifth delay circuits for delaying the output signal of the first AND circuit by one clock period, and the first AND circuit and the fourth and fifth delay circuits. A second AND third AND circuit that outputs a logical product of two different signals among the signals of the delay circuit of FIG.
OR to output OR of output signals of fourth AND circuit
And a circuit.

[0011]

According to the present invention having the above features, when the digital chroma signal after passing through the interline comb filter is input to the vibration detecting section, the polarity corresponding to the increase and decrease of the amplitude of the input digital chroma signal is obtained. A changing pulse signal is output. When this pulse signal is given to the majority circuit,
It decides whether or not the vibration with a period of a majority of the several periods of San flop rings clock is detected, and outputs the determination result as a control signal. With this control signal, the changeover switch switches between the delayed original chroma signal and the chroma signal attenuated by the multiplier to output a beat-suppressed chroma signal.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a beat suppression circuit according to one embodiment of the present invention. Input terminal 21
Is a terminal for inputting a digitally processed chroma signal (C signal) after passing through the interline comb filter shown in FIG. 4, and the signal is a first delay circuit (T) 22 and a comparator 2
3 given. The delay circuit 22 is a circuit that delays the C signal by one clock period. The comparator 23 is a circuit for comparing the level of the signal at the input terminal 21 with the level of the output signal of the delay circuit 22. When the signal level at the input terminal 21 is higher or lower than the output of the delay circuit 22, the comparator 23 has an H or L level, respectively. Is output.

The output terminal of the comparator 23 is connected to second and third delay circuits 24 and 25 connected in series. The delay circuits 24 and 25 are circuits having the same characteristics as the delay circuit 22, and outputs of the delay circuits 24 and 25 are given to first and second exclusive OR circuits (hereinafter referred to as EOR circuits) 26 and 27. Can be The EOR circuit 26 includes a comparator 23 and a delay circuit 24.
Output an H level signal when only one of the output signals is at the H level.
Outputs an H level signal when only one of the output signals of the delay circuits 24 and 25 is at the H level. EOR
The outputs of the circuits 26 and 27 are provided to a first AND circuit 28. Here, as shown by the dashed line A, the delay circuit 22
Comparator 23, delay circuits 24 and 25, EOR circuit 26, A
The ND circuit 28 outputs the digitally processed C signal to N sampling clocks (N ≧ 3), in this case, three clocks .
Increases and decreases alternately every clock during the lock period
H level when repeating, L level otherwise
The vibration detection unit A that outputs a level is configured.

The output of the AND circuit 28 is provided by a fourth and fifth delay circuits 29 and 30 connected in series, and a second logical product of two different input / output signals of these delay circuits. , And third and fourth AND circuits 31, 32, and 33. The AND circuit 31 takes the logical product of the outputs of the AND circuit 28 and the delay circuit 29, and the AND circuit 32
The ND circuit 28 takes the logical product of the outputs of the delay circuits 30. The AND circuit 33 takes the logical product of the outputs of the delay circuits 29 and 30. Next, the OR circuit 34
Signals from the ND circuits 31 to 33 are input, and their logical sum is calculated. The output of the OR circuit 34 is given to the control terminal 35a of the changeover switch 35. The changeover switch 35 has two input terminals 35b and 35c. When the input of the control terminal 35a is at the H or L level, the output terminal 35d is connected to the terminal 3 respectively.
5b or the terminal 35c.

On the other hand, the output of the delay circuit 22 is provided to a sixth delay circuit 36. The delay circuit 36 is a circuit for delaying the input signal by two periods of the sampling clock of the C signal.
To the multiplier 37. The multiplier 37 is a circuit for attenuating an input signal to a predetermined level, and its output is supplied to a terminal 35b of the changeover switch 35. The output terminal 38 is a terminal that outputs a beat-suppressed C signal output from the changeover switch 35. Here, as indicated by a chain line B, delay circuits 29, 30, AND circuits 31, 32, 33, OR
Circuit 34, of San flop rings clock input signal N Black
Of clocks (N ≧ 3), the H level
Output level H when vibration is detected.
Constitute a majority circuit portion B to determine what was.

[0016] For the operation of the beat suppression circuit of the present embodiment constructed as above 1, 2, will be described with reference to FIG. FIGS. 2 (a) to 3 (m) are waveform diagrams of the respective circuit portions a to m in FIG. 1 when the signal shown in FIG. 5 (c) is input to the beat suppression circuit. One wavelength period of chroma signal is 2
A / D conversion is performed with a clock that divides by N (N ≧ 3).
Input to the inter-line comb filter shown in (1). And rye
When the C signal shown in FIG. 2A obtained from the comb filter is input to the input terminal 21, the signals shown in FIGS. 4B and 4C are output from the delay circuits 22 and 36. Comparator 2
When the levels of the signals shown in (a) and (b) are compared at each clock cycle in 3, the signal shown in (d) is obtained at the output. Next, when this signal is delayed by the delay circuits 24 and 25, the output becomes the signal shown in (e) and (f). EO
Only one of the two input signals of the R circuit 26 is H
Therefore, the output is a signal which is always at H level as shown in FIG. Similarly, the EOR circuit 27
Also, the signal which is always at the H level as shown in FIG.
To output. Therefore, the output of the AND circuit 28 is always a high level signal as shown in (i), and the output of the OR circuit 34 is always high level as shown in (j). Therefore, the output terminal 35d of the changeover switch 35 is switched to the terminal 35b, and the signal (a) input to the input terminal 21 is delayed by three clock periods by passing through the delay circuits 22 and 36. Then, the amplitude of this signal is attenuated by the multiplier 37, and a C signal whose amplitude is attenuated as shown in FIG.

Conventionally, a Y signal is obtained by subtracting a digitally processed C signal from a composite video signal. However, interference fringes due to a sampling clock appear in the Y signal, and the quality of the video is degraded. However, the beat signal included in the input C signal is detected, the level is reduced by the multiplier 37, and interference fringes appearing in the C signal can be suppressed.

Next, the operation when a C signal whose hue changes rapidly will be described with reference to FIG. FIG. 3 is a waveform diagram in each circuit unit of the beat suppression circuit of the present embodiment when a C signal whose hue changes suddenly on the way is input. 3 phase sinusoidal C signal at time t ₁ shown in D of (a) consider the operation when the input signals that varies 180 °. When this C signal is digitally processed, a signal E that changes stepwise with the sampling clock is obtained. When this signal is applied to the interline comb filter of FIG. 4, the same waveform is output from the output terminal 17 thereof. Further, when this output signal is input to the input terminal 21 in FIG. 1, the output of the comparator 23 has a waveform as shown in FIG. When this signal is applied to the delay circuits 24 and 25, the signals become as shown in (e) and (f), and
As the output of the circuit 28 is shown in (i), the pulse signal is obtained only clock from the time t ₁ 2 clock period delay becomes H. When this pulse signal is applied to the delay circuits 29 and 30, signals as shown in (l) and (m) are output, and the output of the OR circuit 34 is always at the L level as shown in (j) by majority processing. Is output. Therefore, the output terminal 35d of the changeover switch 35 is switched to the terminal 35c, and the C signal shown in FIG. 3A input to the input terminal 21 is output from the output terminal 38 as it is.

When a signal containing only a pure C signal is input to the beat suppressing circuit, even if the phase suddenly changes in the middle, the signal is output without attenuating the amplitude. That is, as shown in the waveform of FIG. 2A, the signal is attenuated for the C signal having the distortion modulated by the sampling clock, and is output as it is for the other signal.

[0020]

As described above in detail, according to the present invention, the chroma signal separated by the interline comb filter is passed through the beat suppressing circuit of the present invention, whereby the signal which becomes the interference fringe of the luminance signal is obtained. In this case, this signal is suppressed, and when it is not, this signal is output as it is. Therefore, the beat of the chroma signal can be eliminated. or,
When this beat suppression circuit is provided in a television receiver,
High quality images can be displayed, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a beat suppression circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a beat suppression circuit when a diagonal video signal is input in the embodiment.

FIG. 3 is a waveform diagram of a beat suppression circuit when a video signal whose hue changes rapidly in the present embodiment is input.

FIG. 4 is a block diagram illustrating an example of a configuration of a comb between lines.

FIG. 5 is a waveform chart in a line-to-line comb filter when a diagonal video signal is processed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Input terminal 22, 24, 25, 29, 30, 36 Delay circuit 23 Comparator 26, 27 EOR circuit 28, 31, 32, 33 AND circuit 34 OR circuit 35 Changeover switch 37 Multiplier 38 Output terminal A Vibration detector B Majority circuit

Claims (3)

(57) [Claims] 1. One wavelength period of a chroma signal is divided into 2N equal parts (N
≧ 3) A / D-converted by the sampling clock at the rate of the rate, and the digital chroma signal after passing through the interline filter is used as an input signal, and the input signal alternates every one clock during the N clock period of the sampling clock.
H level when repeated increase and decrease is detected
Vibration detector which outputs L level otherwise
And the output signal of the vibration detection unit is H for more than a majority of the N clock periods of the sampling clock.
A majority circuit that outputs an H level signal when the signal is at the H level for a majority clock period or more, a multiplier that attenuates the delayed signal of the digital chroma signal, and a control signal from the majority circuit circuit If H is H
Output signal of the detector, and when the control signal is L, the digital
A changeover switch for outputting a signal obtained by delaying a tal chroma output signal , wherein the changeover switch outputs a chroma signal. 2. A first delay circuit for receiving a digital chroma signal after passing through a comb filter between lines as an input signal and delaying the signal for one clock period, wherein the vibration detecting section includes: A comparator that compares the output signals of the delay circuits and outputs an H or L level signal, and delays the output signal from the comparator by one clock period.
A cascade-connected second and third delay circuit; and a first which outputs an exclusive OR of two different signals among the output signals of the comparator and the second and third delay circuits.
And a second exclusive OR circuit; and a first AND circuit that outputs a logical product of the output signals of the first and second exclusive OR circuits. Cascaded fourth and fifth delay circuits for delaying the output signal of the first AND circuit by one clock period, and signals of the first AND circuit and the fourth and fifth delay circuits. The second and third AND circuits output the logical product of two different signals, and the OR circuit outputs the logical sum of the output signals of the second to fourth AND circuits. The beat suppression circuit according to claim 1, wherein: 3. A television receiver comprising the beat suppression circuit according to claim 1 or 2.