JP2563950B2 - Luminance signal Color signal separation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention takes a composite video signal as an input, and outputs the composite video signal as a luminance signal (hereinafter referred to as Y signal) and a carrier color signal (hereinafter referred to as C signal). And a luminance signal / color signal separation device for separating into

[Prior Art] FIG. 3 is a block diagram showing a configuration of a conventional luminance signal / color signal separation device. For convenience of explanation, a PAL composite video signal will be described.

In FIG. 3, (100) is an input terminal, and the input terminal (100) has a frequency four times as high as the color subcarrier frequency, and its phase is sampled by a signal whose phase matches the U axis and V axis of the input signal. The digitized digital PAL composite video signal is applied. (201) to (203) are first to third delay circuits,
The signal input from the input terminal (100) and supplied from the preceding circuit is delayed by two sampling cycles. (221), (2
Reference numeral 22) is a first and second two-line delay circuit, which delays the signal supplied from the preceding circuit by two horizontal scanning periods. (31
1) and (312) are the first and second 1/4 times circuits, which multiply the signal supplied from the preceding circuit by 1/4. Reference numeral (321) is a first 1 / 2-fold circuit which doubles the output signal of the second delay circuit (202).

Reference numerals (401) to (403) denote first to third addition circuits, which add signals of two supplied systems. (501) to) (505) are first to fifth subtraction circuits, which perform subtraction between the signals of the two systems supplied. Reference numeral (601) is a switching circuit, which outputs one of the output signals of the first and second subtraction circuits (501) and (502) based on an output control signal of a comparison circuit (900) described later. Switch output. (701), (702) are the first
The second absolute value circuit takes the absolute value of the signal supplied from the previous circuit. (800) is a constant generation circuit that generates a constant.

The comparison circuit (900) is the second absolute value circuit (702).
Of the third adder circuit (403) and the control signal for controlling the operation of the switching circuit (601) is output. (101) is a C signal output terminal for outputting a C signal which is an output signal of the switching circuit (601). (102)
Is a Y signal output terminal for outputting a Y signal which is an output signal of the fifth subtraction circuit (505).

 Next, the operation of the above configuration will be described.

4 of the color subcarrier frequency, which is synchronized with the horizontal scanning frequency
A sampled value series of a PAL-type composite video signal sampled with a signal having a frequency twice that of the input signal whose phase matches the U axis and V axis of the input signal has an array as shown in FIG. The operation of the circuit shown in FIG. 3 will be described with reference to FIG.

Now, if the sample value (N33) of the sampling point (S33) is input from the input terminal (100), the first delay circuit (20
The sample value (N32) of the sampling point of (S32) is output to (1), and the sample value (N23) of the sampling point of (S23) is output to the output of the first two-line delay circuit (221). The sample value (N22) of the sampling point (S22) at the output of the circuit (202) and the sample value (N21) of the sampling point (S21) at the output of the third delay circuit (203)
However, the sample value (N12) of the sample point (S12) is obtained at the output of the second two-line delay circuit (222).

The first adder circuit (401) is the first delay circuit (201).
Output signal (N32) and the second two-line delay circuit (22
2) is added to the output signal (N12), and the first 1/4 multiplication circuit (311) is provided in the first addition circuit (40).
It is configured to multiply the output signal of 1) by 1/4. 1/2
The multiplication circuit (321) is configured to multiply the output signal (N22) of the second delay circuit (202) by half. A first subtraction circuit (501) subtracts the output signal of the first 1/4 multiplication circuit (311) from the output signal of the 1/2 multiplication circuit (321). Therefore, the output signal (CV) of the first subtraction circuit (501)
Becomes CV =-(1/4) N32 + (1/2) N22- (1/4) N12.

The second adder circuit (402) is the third delay circuit (203).
Output signal (N21) and the first two-line delay circuit (22
1) is added to the output signal (N23), and the second 1/4 multiplication circuit (312) is provided with the second addition circuit (40).
It is configured to multiply the output of 2) by 1/4. A second subtraction circuit (502) subtracts the output signal of the second 1/4 multiplication circuit (312) from the output signal of the 1/2 multiplication circuit (321). Therefore, the output signal of the second subtraction circuit (502) (C
H) becomes CH =-(1/4) N21 + (1/2) N22- (1/4) N23.

Furthermore, the output signal (N3
2) and the output signal (N1) of the second two-line delay circuit (222)
2) is supplied to the third subtraction circuit (503), and the output signal of the third subtraction circuit (503) is absolute valued by the first absolute value circuit (701). Therefore, the output signal (DV) of the first absolute value circuit (701) is DV = | N32−N12 |.

In addition, the output signal of the first 2-line delay circuit (221) (N
23) and the output signal (N21) of the third delay circuit (203) are supplied to the fourth subtraction circuit (504), and the output signal of the fourth subtraction circuit (504) is the second absolute value circuit. The absolute value is taken at (702). Therefore, the second absolute value circuit (70
The output signal (DH) of 2) is DH = | N23−N21.

The output signal (DV) of the first absolute value circuit (701) is supplied to the third adding circuit (403). Constant generator (80
0) is configured to generate a certain constant (K), and the output signal (K) of this constant generation circuit (800) is supplied to the third adder circuit (403), and the third adder circuit is also provided. (Four
03) is the output signal (DV) of the first absolute value circuit (701)
And the output signal (K) of the constant generating circuit (800) are added, and thus the output signal (DV1) of the third adding circuit (403) is DV1 = DV + K.

The output signal (DV1) of the third adder circuit (403) and the output signal (DH) of the second absolute value circuit (702) are supplied to a comparison circuit (900). The magnitude of the output signal (DV1) of the adder circuit (403) and the magnitude of the output signal (DH) of the second absolute value circuit (702) are compared, and a control signal is sent to the switching circuit (601) described next. The output signal (CV) of the first subtraction circuit (501) is supplied to the switching circuit (601).
And the output signal (CH) of the second subtraction circuit (502) are supplied, and the comparison circuit (900) outputs both output signals (DV1),
When (DH) is DV <DH, the output signal of the switching circuit (601) becomes the output signal (CV) of the first subtraction circuit (501), and when DV1 ≧ DH, the switching signal is switched. A control signal is sent to the switching circuit (601) so that the output signal of the circuit (601) becomes the output signal (CH) of the second subtraction circuit (502).

In this way, the comparison circuit (900) detects a direction with little signal change, which means a direction with high correlation, and sends a control signal for selecting the output signal of the filter using the sampling points in the direction with little signal change. To do. Further, the constant (K) generated by the constant generation circuit (800) prevents a decrease in vertical resolution due to the use of sample values of two sampling points vertically separated from each other in the vertical direction. By setting an appropriate value in the constant generation circuit (800), it is possible to prevent the vertical resolution from decreasing.

The C signal which is the output signal of the switching circuit (601) is C
The signal is output from the signal output terminal (101) and simultaneously supplied to the fifth subtraction circuit (505).

The fifth subtraction circuit (505) is the second delay circuit (202).
The C signal which is the output signal of the switching circuit (601) is subtracted from the output signal (N22) of. The fifth subtraction circuit (505)
The Y signal, which is the output signal of, is output from the Y signal output terminal (102).

[Problems to be Solved by the Invention] The conventional luminance signal / chrominance signal separation device is configured as described above, and since the correlation is detected using the composite video signal, in order to detect the correlation in the vertical direction. The distance between the two sample points corresponds to four scanning lines on the screen. Therefore, when the image is changing rapidly in the vertical direction, it may not be possible to properly detect the correlation, and as a result, there is a problem that image quality deterioration such as cross color and dot interference easily occurs. .

The present invention has been made in order to solve the above-mentioned problems, and it is possible to appropriately detect the correlation even in an image that is changing rapidly, and to accurately separate the Y signal and the C signal. It is an object of the present invention to provide a luminance signal / color signal separation device that can be used in the above.

[Means for Solving Problems] A luminance signal / chrominance signal separation device according to the present invention delays a composite video signal sampled at a frequency synchronized with a horizontal scanning frequency by a plurality of line delay units for each scanning line. From the sample values of the target sample point and a plurality of reference sample points around it at the same time, and from the sample values of the target sample point and the reference sample points located directly above the target sample point on the screen. A first vertical color signal extraction filter for obtaining a first color signal by extracting a frequency component corresponding to a component of a color subcarrier in the vertical direction, the sample point of interest, and the sample point of interest in a direction directly below the screen. A second vertical color signal extraction filter that obtains a second color signal by extracting a frequency component corresponding to a component of a color subcarrier in the vertical direction from each sample value of a reference sample point located, the sample point of interest, and Around it , A horizontal color signal extraction filter for extracting a frequency component corresponding to a horizontal color subcarrier component from each sample value of the reference sample points to obtain a third color signal, the sample point of interest and the sample point of interest Change amount extraction means for extracting the first change amount of the luminance signal mainly in the vertical direction from the sample values of the reference sample points including the sample points located right above on the screen of the above sample point of interest. And second change amount extraction means for extracting the second change amount of the luminance signal mainly in the vertical direction from the sample values of the reference sample points including the sample points located directly below the sample point of interest on the screen,
Comparing the first to third variation amounts with third variation amount extraction means for extracting a third variation amount of the luminance signal in the horizontal direction from each sample value of reference sample points around the sample point of interest. Determining means for outputting a control signal; selecting means for selecting the first to third color signals on the basis of the control signal to output as an output color signal; and outputting the composite video signal excluding the output color signal. A subtraction means for outputting a luminance signal,
The control signal selects the first color signal when the first amount of change is minimum, and selects the second color signal when the second amount of change is minimum. The selecting means is controlled so that the third color signal is selected when the third variation is the minimum.

[Operation] According to the present invention, by using the low-frequency Y signal component for detecting the correlation, the distance between two sample points used for detecting the correlation is equal to two scanning lines on the screen. Therefore, even when the image changes rapidly in the vertical direction, the correlation can be detected appropriately and with high performance.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a YC separation circuit according to an embodiment of the present invention. In FIG. 1, (100) has a frequency four times the color subcarrier frequency, and its phase is U of the input signal. Input terminal to which a digital PAL system composite video signal sampled with a signal matching the axis and the V axis is applied, (2
01) to (211) are first to eleventh delay circuits that delay the signals supplied from the preceding circuit by two sampling periods, respectively.
(221) and (222) are the signals supplied from the previous circuit.
64 sampling periods, that is, the first and second two-line delay circuits for delaying the period obtained by subtracting 6 sampling periods from 2 horizontal scanning periods, (301) to (304) are the signals supplied from the preceding circuits, respectively. -1/4 times the first to fourth -1/4 times circuits, (31
1) to (317) are 1st to 7th 1/4 multiplying circuits that multiply the signal supplied from the preceding stage circuit by 1/4, respectively (321) to (328)
Are 1st to 8th 1/2 times circuits that respectively multiply the signals supplied from the preceding circuit by 1/2, and (401) to (406) are the 1st to 1st summing signals of the three systems supplied. A sixth adder circuit,
(407) is a seventh adder circuit that adds the signals of the two supplied systems, (501) to (507) is a first to seventh subtraction circuit that performs the subtraction between the signals of the two supplied systems, ( 601) is the first addition circuit (401) and the first and second subtraction circuits (50)
It is a first switching circuit for switching and outputting any one of the output signals 1) and (502) based on an output control signal of a comparison circuit (900) described later.

(602) switches one of the output signals of the ninth delay circuit (209) and the sixth adder circuit (406) based on an output control signal of a horizontal filter detection circuit (910) described later. Second switching circuit for output, (701) to (7
03) is the first to third absolute value circuits that take the absolute value of the signal supplied from the preceding circuit, (800) is a constant generation circuit that generates a certain constant, and (900) is the above first and second absolute value circuits. Absolute value circuit (7
A comparison circuit (910) that compares the output signals of 01), (702) and the seventh addition circuit (407) and outputs a control signal for controlling the operation of the first switching circuit (601), A horizontal filter detection circuit that outputs a control signal for controlling the operation of the second switching circuit (602), which is judged from the output signal of the comparison circuit (900), and (101) is the second switching circuit (6).
02) is a C signal output terminal for outputting a C signal which is an output signal of (02), and (102) is a Y signal output terminal for outputting a Y signal which is an output signal of the seventh subtraction circuit (507).

 Next, the operation of the above configuration will be described.

4 of the color subcarrier frequency, which is synchronized with the horizontal scanning frequency
A sampled value series of a PAL-type composite video signal sampled with a signal having a frequency twice that of the input signal whose phase matches the U axis and V axis of the input signal has an array as shown in FIG. The operation of the circuit of FIG. 1 will be described with reference to FIG.

Now, if the sample value (N33) of the sampling point (S33) is input from the input terminal (100), the first delay circuit (20
The sample value (N32) of the sampling point (S32) at the output of 1) and the sample value (N31) of the sampling point (S31) at the output of the second delay circuit (202) are the first two-line delay. The sample value (N24) of the sampling point (S24) at the output of the circuit (221) and the sample value (N23) of the sampling point (S23) at the output of the third delay circuit (203)
Is the sample value (N22) of the sampling point (S22) at the output of the fourth delay circuit (204) and the sample value (N21) of the sampling point (S21) at the output of the fifth delay circuit (205). Is the sample value (N20) of the sample point (S20) at the output of the sixth delay circuit (206)
Is the sample value (N13) of the sampling point (S13) at the output of the second two-line delay circuit (222), and the sample value (S12) of the sampling point (S12) at the output of the seventh delay circuit (207) ( N12) is the sample value (N1) of the sample point (S11) at the output of the eighth delay circuit (208).
1) is obtained respectively.

The first 1/2 times circuit (321) is the first delay circuit (20).
The second 1/2 circuit (322) multiplies the output signal (N22) of the fourth delay circuit (204) by 1/2 so that the output signal (N32) of 1) is multiplied by 1/2. Is configured. Then the first
And the subtraction circuit (501) operates so as to subtract the output signal of the first 1/2 times circuit (321) from the output signal of the second 1/2 times circuit (322). Therefore, the C signal component (C22B) which is the output signal of the first subtraction circuit (501) becomes C22B = (1/2) N22- (1/2) N32. In this way, the first and second 1/2 times circuits (32
1), (322), and the first subtraction circuit (501) constitute a vertical color signal extraction filter for extracting the C signal at the sampling point (S22).

The second 1/2 circuit (322) is the fourth delay circuit (20).
The third 1/2 circuit (323) multiplies the output signal (N12) of the seventh delay circuit (207) by 1/2 so that the output signal (N22) of 4) is multiplied by 1/2. Is configured. Then the second
The subtraction circuit (502) operates so as to subtract the output signal of the third 1/2 times circuit (323) from the output signal of the second 1/2 times circuit (322). Therefore, the C signal component (C22T) which is the output signal of the second subtraction circuit (502) becomes C22T = (1/2) N22- (1/2) N12. In this way, the second and third half circuits (32
2), (323) and the second subtraction circuit (502) constitute a vertical color signal extraction filter for extracting the C signal at the sampling point (S22).

The first -1/4 times circuit (301) is the third delay circuit (20
The second half of the output signal (N23) of 3) is multiplied by -1/4.
The multiplying circuit (322) multiplies the second delay circuit (204) output signal (N22) by 1/2 so as to multiply the second by -1/4 multiplying circuit (302).
Is the output signal (N21) of the fifth delay circuit (205) is -1 /
It is configured to multiply by 4. Next, the first adder circuit (4
01) is the above-mentioned first and second -1/4 multiplication circuits (301), (30
2) Operates so as to sum the output signals of the second 1/2 circuit (322). Therefore, the C signal component (C22H) which is the output signal of the first adder circuit (401) becomes C22H =-(1/4) N23 + (1/2) N22- (1/4) N21. . In this way, the above-mentioned first and second -1/4 multiplication circuits (30
1), (302), the second 1/2 multiplication circuit (322), and the first addition circuit (401) constitute a horizontal color signal extraction filter for extracting the C signal at the sampling point (S22). ing.

The first switching circuit (601) is an output signal of the first subtraction circuit (501) extracted in the expectation of high correlation between the sampling points (S22) and (S32) in the vertical direction. A certain C signal component (C22B) and the sampling point (S22) in the vertical direction (S22)
12) The C signal component (C which is the output signal of the second subtraction circuit (502) extracted in the expectation of high correlation of the sampling points
22T) and the C signal component (C22H) which is the output signal of the first adder circuit (401) extracted in anticipation of high correlation in the horizontal direction are input and supplied from the comparison circuit (900). Three input signals are switched and output according to the output control signal.

The operation of the filter selection circuit portion generating the output control signal will be described below.

The third subtraction circuit (503) is the fourth delay circuit (204).
Of the first adder circuit (401) from the output signal (N22) of the C signal component (C22H). Therefore, the low frequency Y signal component (Y22H) which is the output signal of the third subtraction circuit (503) becomes Y22H = N22-C22H.

The first 1/4 circuit (311) multiplies the signal (N33) applied to the input terminal (100) by 1/4, and the fourth 1/2 circuit (324) includes the first circuit. The second 1/4 multiplication circuit (312) converts the output signal (N31) of the second delay circuit (202) by 1 so that the output signal (N32) of the second delay circuit (201) is multiplied by 1/2. It is configured to multiply by / 4. Next, the second adder circuit (40
2) is the 1st, 2nd 1/4 circuit (311), (312), 4th
It operates so as to take the sum of the output signals of the 1/2 times circuit (324). Therefore, the low frequency Y signal component (Y32H) which is the output signal of the second adder circuit (402) becomes Y32H = (1/4) N33 + (1/2) N32 + (1/4) N31. . In this way, the first and second 1/4 circuit (31
1), (312), the fourth 1/2 multiplication circuit (324), and the second addition circuit (402) form a horizontal luminance signal extraction filter for extracting the Y signal of the sampling point (S32). ing.

The third 1/4 multiplication circuit (313) divides the output signal (N24) of the first two-line delay circuit (221) by a factor of 5,
The 1/2 circuit (325) of the third delay circuit (203) is arranged to multiply the output signal (N23) of the third delay circuit 1/2 by 1/2, and the fourth 1/4 circuit (3
14) outputs the output signal (N22) of the fourth delay circuit (204)
It is configured to multiply by 1/4. Next, the third adder circuit (403) is connected to the third and fourth 1/4 multiplication circuits (313), (31
4) Operates so as to sum the output signals of the fifth 1 / 2-fold circuit (325). Therefore, the low frequency Y signal component (Y23H) which is the output signal of the third adder circuit (403) becomes Y23H = (1/4) N24 + (1/2) N23 + (1/4) N22. . In this way, the third and fourth 1/4 circuit (31
3), (314), the fifth 1/2 circuit (325), and the third adder circuit (403) form a horizontal luminance signal extraction filter for extracting the Y signal at the sampling point (S23). ing.

The fourth 1/4 circuit (314) is the fourth delay circuit (20
The sixth 1/2 circuit (326) multiplies the output signal (N21) of the fifth delay circuit (205) by 1/2 so that the output signal (N22) of 4) is multiplied by 1/4. Thus, the fifth 1/4 circuit (315) is configured to multiply the output signal (N20) of the sixth delay circuit (206) by 1/4. Next, the fourth adder circuit (40
4) is the fourth and fifth 1/4 times circuits (314), (315), and sixth
It operates so as to take the sum of the output signals of the 1/2 times circuit (326). Therefore, the low-frequency Y signal signal component (Y21H) which is the output signal of the fourth adding circuit (404) is Y21H = (1/4) N22 + (1/2) N21 + (1/4) N20 Become. In this way, the fourth and fifth 1/4 times circuits (31
4), (315), the sixth 1/2 circuit (326), and the fourth adding circuit (404) constitute a horizontal luminance signal extraction filter for extracting the Y signal of the sampling point (S21). ing.

The sixth 1 / 4-fold circuit (316) multiplies the output signal (N13) of the second 2-line delay circuit (222) by a factor of 7,
The 1/2 circuit (327) of the 7th 1/4 circuit (3) multiplies the output signal (N12) of the 7th delay circuit (207) by 1/2.
17) is the output signal (N11) of the eighth delay circuit (208)
It is configured to multiply by 1/4. Next, the fifth adder circuit (405) is connected to the sixth and seventh 1/4 multiplication circuits (316), (31).
7), and operates so as to sum the output signals of the seventh 1 / 2-fold circuit (327). Therefore, the low-frequency Y signal component (Y12H) which is the output signal of the fifth adder circuit (405) is Y12H = (1/4) N13 + (1/2) N12 + (1/4) N11. . In this way, the sixth and seventh 1/4 circuit (31
6), (317), the seventh 1/2 circuit (327), and the fifth adding circuit (405) constitute a horizontal luminance signal extraction filter for extracting the Y signal of the sampling point (S12). ing.

The fourth subtraction circuit (504) is the third subtraction circuit (503).
From the low frequency Y signal component (Y22H) which is the output signal of
Low frequency Y signal component (Y
32H) works to subtract. Next, the first absolute value circuit (701) operates so as to take the absolute value of the output signal of the fourth subtraction circuit (504). Therefore, the output signal (DB) of the first absolute value circuit (701) becomes DB = | Y22H−Y32H |.

The fifth subtraction circuit (505) is the third subtraction circuit (503).
From the low frequency Y signal component (Y22H) which is the output signal of
Low frequency Y signal component (Y
12H) works to subtract. Next, the second absolute value circuit (702) operates so as to take the absolute value of the output signal of the fifth subtraction circuit (505). Therefore, the output signal (DT) of the second absolute value circuit (702) is DT = | Y22H−Y12H |.

The sixth subtraction circuit (506) is the third addition circuit (403).
From the low frequency Y signal component (123H) which is the output signal of
Low frequency Y signal component (Y
21H) works to subtract. Next, the third absolute value circuit (703) operates so as to take the absolute value of the output signal of the sixth subtraction circuit (506). Therefore, the output signal (DH) of the third absolute value circuit (703) becomes DH = | Y23H−Y21H |.

The output signal (DH) of the third absolute value circuit (703) is supplied to the seventh adding circuit (407). Constant generator (80
Since 0) generates a certain constant (K), the output signal (K) of the constant generating circuit (800) is supplied to the seventh adding circuit (407). Seventh addition circuit (407)
Is configured to add the output signal (DH) of the third absolute value circuit (703) and the output signal (K) of the constant generation circuit (800), and thus the seventh addition The output (DHK) of the circuit (407) is DHK = DH + K.

The output signal of the first absolute value circuit (701), which means the amount of change in the low frequency Y signal component between the sampling points (S22) and (S32) in the vertical direction, is output to the comparator circuit (900) ( DB),
The output signal (DT) of the second absolute value circuit (702) meaning the amount of change in the low frequency Y signal component between the sampling point (S22) and the sampling point (S12) in the vertical direction, and the horizontal direction Output signal (DHK) of the seventh adder circuit (407) meaning the amount of change in the low frequency Y signal component between the sampling point (S23) and the sampling point (S21)
3 signals are supplied. The comparison circuit (900) compares the magnitudes of these three signals and determines the smallest signal among them. According to the comparison, the pulse code corresponding to the C signal component (C22B) which is the output signal of the first subtraction circuit (501) when the output signal (DB) of the first absolute value circuit (701) is the minimum, When the output signal (DT) of the second absolute value circuit (702) is minimum, the pulse code corresponding to the C signal component (C22T) which is the output signal of the second subtraction circuit (502) is added to the seventh addition circuit. When the output signal (DHK) of (407) is minimum, a pulse code corresponding to the C signal component (C22H) which is the output signal of the first adding circuit (401) is generated, and the first switching circuit is used as a control signal. Send to (601).

In this way, the filter selection circuit section detects the correlation of the low frequency Y signal and selects the color signal extraction filter configured by using the sample value of the sample point having the highest correlation. Further, the constant (K) generated by the constant generating circuit (800) prevents a decrease in vertical resolution due to the use of sample values of sample points separated by two scanning lines in the vertical direction. By setting an appropriate value in the constant generation circuit (800), it is possible to prevent the vertical resolution from decreasing.

The first switching circuit (601) is a sampling point (S22) obtained by using an appropriate carrier color signal extraction filter at the reference sampling point based on the control signal supplied from the comparison circuit (900). The C signal component (C22D) of is output.
At this time, the output of the ninth delay circuit (209) is (S21)
The C signal component (C21D) at the sampling point is obtained, and the C signal component (C20D) at the sampling point (S20) is obtained at the output of the tenth delay circuit (210).

The third -1/4 circuit (303) is the first switching circuit (60).
1) output signal (C22D) multiplied by -1/4
The doubling circuit (328) multiplies the output signal (C21D) of the ninth delay circuit (209) by ½ so that the fourth −1/4 circuit (30
4) is configured to multiply the output signal (C20D) of the tenth delay circuit (210) by -1/4. Next, the sixth adder circuit (406) is connected to the third and fourth -1/4 multiplying circuits (303), (3
04), and operates so as to take the sum of the output signals of the eighth 1/2 circuit (328). Therefore, the C signal component (C21F) which is the output signal of the sixth adder circuit (406) becomes C21F =-(1/4) C22D + (1/2) C21D- (1/4) C20D. . In this way, the third and fourth -1/4 multiplication circuits (30
3), (304), the eighth 1/2 circuit (328), and the sixth adder circuit (406) constitute a horizontal color signal extraction filter for extracting the C signal.

The eleventh delay circuit (211) is connected to (S2 of the upper comparison circuit (900).
2) A delay circuit for compensation provided to make the output signal corresponding to the sampling point of (2) correspond to the sampling point of (S21).

The horizontal filter detection circuit (910) receives the output signal of the eleventh delay circuit (211) as an input, and receives the first addition circuit (40).
When the pulse code corresponding to the C signal component (C22H) which is the output signal of 1) is detected, that is, when the output signal of the first switching circuit (601) is the output signal of the horizontal color signal extraction filter. Pulse is generated only on the second switching circuit (602) as a control signal.

The second switching circuit (602) is the ninth delay circuit (209).
C signal component (C21D), which is the output signal of the above, and the C signal component (C21F), which is the output signal of the sixth addition circuit (406), are input, and the output supplied from the horizontal filter detection circuit (910). When a pulse exists in the control signal, the C signal component (C21D) which is the output signal of the ninth delay circuit (209).
When there is no pulse, the C signal component (C21F) which is the output signal of the sixth adder circuit (406) is output. Here, when the output signal of the first switching circuit (601) is the output signal of the horizontal color signal extraction filter, it is configured so as not to further pass through the horizontal color signal extraction filter. This is because if the horizontal filters are doubled, the filter characteristics become steep and dot interference easily occurs. In addition, the first switching circuit (60
When the output signal of 1) is not the output signal of the horizontal color signal extraction filter, that is, when it is the vertical color signal extraction filter, it is configured to further pass through the horizontal color signal extraction filter. This is because cross-coloring is likely to occur in a configuration including only a color signal extraction filter in the vertical direction.

The C signal (C21) which is the output signal of the second switching circuit (602) is output from the C signal output terminal (101) and at the same time supplied to the seventh subtraction circuit (507).

The seventh subtraction circuit (507) is the fifth delay circuit (2
05) output signal (N21) to the second switching circuit (602)
It operates so as to subtract the C signal (C21) which is the output signal of. Therefore, the Y signal (Y21) which is the output signal of the seventh subtraction circuit (507) becomes Y21 = N21-C21. The Y signal (Y21) which is the output signal of the seventh subtraction circuit (507) is output from the Y signal output terminal (102).

In the above embodiment, the digital input signal is
The case where the PAL system composite video signal was applied was shown.
The delay time of the first and second two-line delay circuits (221) and (222) is 2264 sampling periods, that is, 6 horizontal sampling periods are subtracted from 904 sampling periods, that is, horizontal scanning period. By substituting 6 sampling periods for the period, NT at a frequency four times the color subcarrier frequency
It can also be applied to a digital NTSC composite video signal obtained by sampling an SC composite video signal.

[Advantages of the Invention] As described above, according to the luminance signal / chrominance signal separation device of the present invention, the composite video signal sampled at the frequency synchronized with the horizontal scanning frequency is divided into a plurality of line delays for each scanning line. Means for simultaneously extracting each sample value of the sample point of interest and a plurality of reference sample points around it, and each sample of the sample point of interest and the reference sample point located right above the screen of the sample point of interest A first vertical color signal extraction filter for obtaining a first color signal by extracting a frequency component corresponding to a vertical color subcarrier component from the value, the sample point of interest and the sample point of interest directly below the screen. A second vertical color signal extraction filter for obtaining a second color signal by extracting a frequency component corresponding to a component of a color subcarrier in the vertical direction from each sample value of reference sample points located in the direction; Dots and their A horizontal color signal extraction filter for obtaining a third color signal by extracting a frequency component corresponding to a component of a horizontal color subcarrier from each sample value of surrounding reference sample points, the sample point of interest and the sample of interest A first change amount extracting means for extracting the first change amount of the luminance signal mainly in the vertical direction from each sample value of the reference sample points including the sample points located right above the screen on the screen; A second extracting amount of a second variation of the luminance signal mainly in the vertical direction from the sample values of the reference sample points including the sample points and the sample points located right below the screen of the sample point of interest.
Change amount extracting means, third change amount extracting means for extracting a third change amount of the luminance signal in the horizontal direction from each sample value of reference sample points around the sample point of interest, and the first to third examples. From the composite video signal, the determination means for comparing the amount of change in the control signal to output a control signal, the selection means for selecting the first to third color signals based on the control signal and outputting the output color signal. Subtracting means for outputting the output luminance signal excluding the output color signal, and the control signal changing the second change so as to select the first color signal when the first change amount is minimum. By controlling the selecting means, the second color signal is selected when the amount is minimum, and the third color signal is selected when the third change amount is minimum, the correlation is controlled. Is configured to detect the low frequency Y signal signal component, The detection properly, and can be carried out performance well, the has the effect of realizing an accurate YC separation without image quality degradation due connexion cross color and dots interference.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a luminance signal / color signal separation device according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing a two-dimensional array of sampling sequences on the screen when sampling is performed at a frequency, and FIG. 3 is a block diagram showing a configuration of a conventional luminance signal / color signal separating device. (100) …… input terminal, (201) to (211) …… first to first
1 delay circuit, (221), (222) ... 1st, 2nd 2 line delay circuits, (301)-(304) ... 1st-4th -1/4
Doubler circuit, (311) to (317) ... 1st to 7th 1/4 times circuit, (321) to (328) ... 1st to 8th 1/2 times circuit, (4
01) to (407) ... 1st to 7th addition circuits, (501) to
(507) ... First to seventh subtraction circuits, (601), (602)
...... First and second switching circuits, (701) to (703) ... First to third absolute value circuits, (800) ... Constant generation circuit, (900) ...
… Comparison circuit, (910) …… Horizontal filter detection circuit, (10
1) …… C signal output terminal, (102) …… Y signal output terminal. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A sampled value of a sample point of interest and a plurality of reference sample points around it by delaying a composite video signal sampled at a frequency synchronized with a horizontal scanning frequency by one scanning line by a plurality of line delay devices. And a frequency component corresponding to the component of the color subcarrier in the vertical direction from each sample value of the sample point of interest and the reference sample point located right above the screen of the sample point of interest. A first vertical color signal extraction filter for obtaining a first color signal, and a vertical color subcarrier from each sample value of the sample point of interest and a reference sample point located directly below the sample point of interest on the screen. A second vertical color signal extraction filter for obtaining a second color signal by extracting a frequency component corresponding to the component, and a color subcarrier in the horizontal direction from each sample value of the sample point of interest and reference sample points around it. Ingredients for Horizontal color signal extraction filter for extracting a frequency component to obtain a third color signal, and each sample of reference sample points including the sample point of interest and sample points located directly above the screen of the sample point of interest First change amount extracting means for extracting a first change amount of the luminance signal mainly in the vertical direction from the value, and a reference sample including the sample point of interest and a sample point located directly below the sample point of interest on the screen Second change amount extracting means for extracting a second change amount of the luminance signal mainly in the vertical direction from each sample value of the point, and luminance in the horizontal direction from each sample value of the reference sample points around the sample point of interest. Third change amount extraction means for extracting a third change amount of the signal, determination means for comparing the first to third change amounts and outputting a control signal, and the first to third color signals Based on the above control signal and output as an output color signal. Selecting means and subtracting means for outputting the output luminance signal by removing the output color signal from the composite video signal, and the control signal outputs the first color signal when the first change amount is minimum. So that the second color signal is selected when the second change amount is the minimum, and the third color signal is selected when the third change amount is the minimum. A luminance signal / color signal separation device characterized by controlling the selection means. 2. A second output color signal is obtained by inputting the first output color signal output from the first selecting means and extracting a frequency component corresponding to a component of a horizontal color subcarrier. A second horizontal color signal extraction filter; a second determination circuit for outputting a second control signal based on the first control signal; and a second determination circuit for the first or second output color signal. Second selection means for selecting based on a control signal and outputting as an output color signal, wherein the second control signal is such that the first control signal selects the first or second color signal. When the signal is a signal, the second output color signal is selected. When the first control signal is a signal that selects the third color signal, the first output color signal is selected. The control means for controlling the second selection means according to claim 1. Degree-chrominance signal separator.