JPH05110551A - Data pulse generating device - Google Patents

Abstract

PURPOSE:To reduce probability of an erroneous decision, compared with the case when a period is derived from only a count value of a level part for decid ing the period by using count values before and after the count value of the level part for deciding the period, for a correction at the time of deciding the period. CONSTITUTION:The device counts time length of a first level part and a second level part of data signal, and outputs a clock pulse signal corresponding to a period of each level part, based on these count values. Also, this device is constituted by providing latch circuits 9-11 of plural stages for latching successively the count values, and a decoder circuit 12 for using the count values before and after the count value of the level part for deciding a period, in the count values latched by each latch circuit 9-11, for a correction at the time of deciding the period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data pulse generator for generating a number of clock pulse signals which is determined based on the time length of a changing section of a binary signal recorded on a recording medium. ..

[0002]

2. Description of the Related Art In a circuit for reproducing and demodulating a data signal which is modulated and recorded on a recording medium, it is necessary to reproduce the clock signal in order to take the reproduced signal into the demodulation circuit. Generally, this clock signal is reconstructed based on the reproduction signal.
A phase locked loop circuit (hereinafter referred to as a PLL circuit), which is a data pulse generator, is frequently used.

In particular, a PL composed of digital elements
The L circuit (hereinafter, referred to as a digital PLL circuit) has many advantages in recent years because it has an advantage that there is less variation due to parts used and desired characteristics can be obtained without adjustment as compared with a PLL circuit using an analog element. The circuit of is proposed.

Conventionally, in the above digital PLL circuit, a master clock signal higher than a reproduction signal is frequency-divided by using a programmable frequency dividing circuit, as disclosed in, for example, Japanese Patent Application Laid-Open No. 1-123525. A method has been proposed in which a reproduced clock signal is generated by a counter, the phase difference between the reproduced clock signal and the reproduced signal is counted by a counter circuit, and the frequency division ratio of the programmable frequency dividing circuit is controlled by the obtained count value.

Further, in the conventional digital PLL circuit, the time length of the H level period and the L level period of the reproduction signal is counted by the counter circuit, and the number of clock pulses is generated based on the obtained count value. A method of making it possible is also proposed.

[0006]

However, in the digital PLL circuit which is the above-mentioned conventional data pulse generator, the level of the reproduction signal is lowered due to the increase of the recording density on the recording medium, which makes it susceptible to noise. The position of the changing point of the reproduced signal is shifted due to this noise, and especially in magnetic recording, the position of the changing point of the reproduced signal is shifted due to the influence of the front and rear magnetic recording patterns due to the characteristics of the magnetic head. A so-called peak shift will occur.

For example, as shown in FIG. 8, a waveform of an analog signal reproduced from a magnetic recording medium through a magnetic head and amplified, and this analog signal is sliced by a slicer and converted into a binary signal (digital signal). The waveform of the reproduced signal (PBSG) is observed with an oscilloscope, and it is assumed that the peak shift occurs at the position of the arrow.

The period of the signal during recording is 1T, 2
If there are four types of T, 3T, and 4T, at the peak shift position of the arrow, for example, 1T is 1.5T and 3T.
T will change to 2.5T.

At this time, since the count by the counter circuit implemented in the conventional data pulse generator has an error of ± 1 count in principle, when the master clock signal is 10 times 1T, Is counted 16 times when counting 1.5T, and is closer to 2T (20 counts) than 1T (10 counts), so there is a possibility that it may be erroneously determined to be 2T. Also, 2.5T is counted 24 times, There is a possibility of erroneous determination as 2T.

As described above, in the digital PLL circuit which is the conventional data pulse generator, when a large peak shift occurs, there is a high possibility that a malfunction will occur due to an erroneous determination. Therefore, in the present invention,
It is an object of the present invention to provide a data pulse generator capable of sufficiently reducing the probability of misjudgment even when a large peak shift occurs.

[0011]

Means for Solving the Problems Claims 1 and 2
In order to solve the above-mentioned problems, the data pulse generator of the present invention counts the time lengths of the first level portion and the second level portion of the data signal, and based on these count values, It outputs a clock pulse signal corresponding to a cycle and has the following features.

That is, a data pulse generator according to a first aspect of the present invention provides a latch circuit which is a plurality of stages of latch means for sequentially latching the count value and a cycle of the count value latched by each of these latch means. It is characterized in that it has a decoder circuit which is a cycle determining means for using a count value before and after the count value of the level section to be judged for correction when judging the cycle.

A data pulse generator according to a second aspect of the present invention includes a NAND circuit and an H counter circuit which are counter means for counting the level portion using one of the rising edge and the falling edge of the clock signal. A NAND circuit that is a counter correction unit that determines the positional relationship between the start edge of the level portion and the other edge of the clock signal, and corrects the count value when the start edge is positioned before the other edge, It is characterized by having a correction counter circuit and an adder.

[0014]

According to the structure of claim 1, since the count value before and after the count value of the level part for judging the cycle is used for the correction at the time of judging the cycle, only the count value of the level part for judging the cycle is used. The probability of misjudgment can be reduced as compared with the case of obtaining.

According to the second aspect of the invention, the positional relationship between the other edge and the start edge of the level portion is determined, and the count value is corrected when the start edge is positioned before the other edge. Therefore, it is equivalent to the case of counting using both edges.

Therefore, the count value can be reduced from a count error of ± 1 to a count error of ± 0.5, which in turn can reduce the probability of erroneous determination when obtaining the cycle from the count value.

[0017]

[Embodiment 1] The following will describe one embodiment of the present invention with reference to FIGS. 1 to 4.

The data pulse generator according to this embodiment is
As shown in FIG. 1, it has an oscillator 1 that outputs a master clock signal MCK, and a shift register circuit 2 to which the reproduced signal PBSG that has been NRZI converted and digitized is input. The shift register circuit 2 outputs a D terminal to which the reproduction signal PBSG is input, a CK terminal to which the master clock signal MCK from the oscillator 1 is input, and a shift signal obtained by shifting the master clock signal MCK by one clock. Output terminals 1Q to 3Q and inverted output terminals 1Q to 3Q. The reproduction signal PBSG is fetched at the rising edge of the master clock signal MCK and the shift signal is output.

Output terminal 1 of the shift register circuit 2 described above
Q and inverting output terminal 2Q are two-input NAND circuit 5
Connected to the input terminals of the NAND circuit 5
Outputs an edge detection signal a indicating the rising edge of the reproduction signal PBSG. In addition, the output terminal 2Q and the inverting output terminal 1Q of the shift register circuit 2
Are respectively connected to the input terminals of the 2-input NAND circuit 6, and the NAND circuit 6 outputs the edge detection signal b indicating the falling edge of the reproduction signal PBSG. Further, the output terminal 1Q and the output terminal 2Q of the shift register circuit 2 are connected to the input terminals of the 2-input EX-OR circuit 7, respectively, and the EX-OR circuit 7 causes the reproduction signal PBSG to rise and fall. An edge detection signal h indicating an edge is output.

The output terminal of the NAND circuit 5 is connected to the reset terminal R of the H counter circuit 3, and NA
The output terminal of the ND circuit 6 is connected to the reset terminal R of the L counter circuit 4. The H counter circuit 3 and the L counter circuit 4 have a CK terminal to which the master clock signal MCK from the oscillator 1 is input and an output terminal Q.
And a count enable terminal E, the output terminal 2Q of the shift register circuit 2 is connected to the count enable terminal E of the H counter circuit 3, and the output terminal 2Q
The shift signal c is input from. Further, the inverting output terminal 2Q of the shift register circuit 2 is connected to the count enable terminal E of the L counter circuit 4, and the shift signal d is input from the inverting output terminal 2Q.

When the edge detection signal a is input, the H counter circuit 3 clears the count value to zero and starts counting the master clock signal MCK. When the shift signal c is input, the H counter circuit 3 stops counting and outputs the count value. H
The count signal e of the level portion (first level portion) is output from the output terminal Q. Further, the L counter circuit 4 clears the count value to zero and starts counting the master clock signal MCK when the edge detection signal b is input, and stops the count when the shift signal d is input to set the count value to the L level portion. (Second level part)
Is output from the output terminal Q as the count signal f.

The output terminal Q of the H counter circuit 3 and the output terminal Q of the L counter circuit 4 are connected to the input terminal A and the input terminal B of the multiplexer circuit 8, respectively. This multiplexer circuit 8 has input terminals A and B
It has an output terminal Y that outputs one of the count signals e and f input to the input terminal and a switching terminal S that switches the output of the count signals e and f. The output terminal 2Q of the shift register circuit 2 is connected to the switching terminal S of the multiplexer circuit 8 so that the shift signal c from the output terminal 2Q is input.

The output terminal Y of the multiplexer circuit 8 is connected to the input terminal D of the latch circuit 9 (latch means), and the count value of the count signals e and f switched by the shift signal c is counted by the count signal g. It is designed to be output as. The output terminal Q of the latch circuit 9 to which the count signal g is input is the latch circuit 1
The latch circuit 10 is connected to the input terminal D of 0 (latch means) and outputs the count signal i, which is a signal obtained by latching the count signal g, to the input terminal D.
The output terminal Q is connected to the input terminal D of the latch circuit 11 (latch means), and the count signal j, which is a signal obtained by latching the count signal i, is output to the input terminal D. Further, in the latch circuit 11, the output terminal Q is connected to the input terminal C of the decoder circuit 12 (cycle determining means), and the count signal k is output to the input terminal C.

In addition to the output terminal Q and the input terminal D, each of the latch circuits 9, 10, and 11 has a clock terminal C.
It also has K, and each clock terminal CK has the above-mentioned EX
The output terminal of the -OR circuit 7 is connected. The latch circuits 9, 10 and 11 are connected to the EX-OR circuit 7
Each time the edge detection signal h is input from the input terminal D.
While receiving the count signals g · i · j input to D · D, the count signals i · j from the output terminals Q · Q · Q
By outputting j · k, consecutive count values are sequentially latched.

The output terminals Q, Q, Q of the latch circuits 9, 10, 11 are the input terminals A, B of the decoder circuit 12, respectively.
-Connected to C. This decoder circuit 12 is shown in FIG.
As shown in, it has ROMs 15, 16 and 17,
The above-mentioned input terminals A, B and C are connected to the address terminals A _{0 to} A ₅ of the ROMs 15, 16 and 17, respectively.

The ROM 15 · 17 described above, as shown in Table 1, the count signal i · k to the address terminals A ₀ to A ₅
The data area corresponding to the address specified by has output data serving as the correction signal p · q.

[0027]

[Table 1]

In Table 1, the output value calculated by using the count signal i · k as the input value X and the relational expression corresponding to the numerical range of the input value X is specified by the input value X. It means that it is stored in the data area corresponding to the address.

Further, the ROM 16 is, as shown in Table 2,
The data area corresponding to the address specified by the count signal j to the address terminals A _{0 to} A ₅ has output data as the control signal r.

[0030]

[Table 2]

The data terminal Q ₀ of the ROM 16 is R
It is connected to the address terminals A ₆ and A ₆ of the OMs 15 and 17, and outputs the control signal r to these address terminals A ₆ and A ₆ . And both ROM15 ・ 1
7, while being adapted to output a correction signal p · q '0' by the control signal r of the address terminal A ₆ · A ₆ '1' is input, the address terminal A ₆ · A ₆ When the control signal r of "0" is input to, the correction signal pq of the output data is output.

The data terminal Q of each of the ROMs 15 and 17 described above.
The input terminals B of _{0 to} Q ₅ and Q _{0 to} Q ₅ and the decoder circuit 12 are connected to the input terminals A and C and B of the adder 18, respectively, and the correction signals p and q are input to the input terminals A and C, respectively. In addition to inputting, the count signal j is input to the input terminal B. The output terminal Y of the adder 18 is the address terminals A ₀ to
It is connected to A ₅ and outputs an addition signal o which is an addition value obtained by adding the count values of the correction signal p · q and the count signal j to the address terminals A _{0 to} A ₅ of the ROM 19. ..

As shown in Table 3, the ROM 19 to which the addition signal o is input outputs the output data which becomes the decode signal 1 in the data area corresponding to the address specified by the addition signal o to the address terminals A _{0 to} A ₅ . have. In the ROM 19, the data terminals Q _{0 to} Q ₅ are connected to the output terminal Q of the decoder circuit 12.

[0034]

[Table 3]

The output terminal Q of the decoder circuit 12 is connected to the load data terminal 13a of the pulse generating circuit 13, as shown in FIG. This pulse generation circuit 13
Has a load terminal 13b, a CK terminal 13e, a data output terminal 13c, and a clock output terminal 13d. The data output terminal 13c outputs a data signal m, and the clock output terminal 13d outputs a clock signal. A pulse signal n is output.

That is, as shown in FIG. 4, the pulse generating circuit 13 comprises a down counter circuit 20, a 2-input NAND circuit 22, a 3-input OR circuit 21, a T-FF circuit 23, and a NOT circuit 30. The down counter circuit 20 includes a load input terminal 20a, a load terminal 20b,
It has a clock terminal CK and output terminals Q _A , Q _B, and Q _C. The load input terminal 20a of the down counter circuit 20 is connected to the load data terminal 13a of the pulse generation circuit 13, and the decode signal 1 is input via the load data terminal 13a.

The load terminal 20b of the down counter circuit 20 is connected to the load terminal 13b of the pulse generating circuit 13.
Are connected, and the edge detection signal h is input through the load terminal 13b. further,
The load terminal 13b is also connected to the input terminal T of the T-FF circuit 23, and the T-FF circuit 23 outputs the data signal m which is inverted every time the edge detection signal h is input, to the output terminal Q.
It is designed to output from. And this T-FF
The output terminal Q of the circuit 23 is connected to the data output terminal 13c of the pulse generation circuit 13.

On the other hand, the output terminals Q _A , Q _B, and Q _C of the down counter circuit 20 are connected to the input terminals of the OR circuit 21, and the output terminal of the OR circuit 21 is the NAND circuit 2
2 is connected to one of the input terminals. The other input terminal of the NAND circuit 22 is connected to the C of the pulse generating circuit 13.
The K terminal 13e is connected, and the master clock signal MCK is input from the CK terminal 13e. The output terminal of the NAND circuit 22 is pulsed through the clock terminal CK of the down counter circuit 20 and the NOT circuit 30. It is connected to the clock output terminal 13d of the generation circuit 13.

As a result, the down counter circuit 20
When the edge detection signal h is input, the value of the decode signal l is set, and this value is counted down for each input of the master clock signal MCK to the clock terminal CK and output terminal Q _A
· Q _B · Q _C is adapted to output to the OR circuit 21 from, the OR circuit 21, when the total signal from the output terminal Q _A · Q _B · Q _C becomes L level, the L level The output of the NAND circuit 22 is stopped by outputting the decoded signal l
The clock pulse signal n having the number of pulses corresponding to the value of is output.

As shown in FIG. 1, the pulse generation circuit 13 has a data output terminal 13c and a clock output terminal 13d connected to the demodulation circuit 14, and the demodulation circuit 14 outputs the pulse from the pulse generation circuit 13. Demodulation is performed based on the clock pulse signal n and the data signal m.

The operation of the data pulse generator having the above structure will be described.

First, the reproduction signal PBSG has a time length which is a positive multiple of the cycle T in which one level is determined, has 1T as the shortest time length, and has 2T as the longest time length. Shall have. Further, the master clock signal MCK is assumed to be 10 times 1T.

The reproduction signal PBSG is taken into the shift register circuit 2 at the rising edge of the master clock signal MCK generated by the oscillator 1, and the shift signals obtained by shifting the master clock signal MCK by one clock are output terminals 1Q to 3Q and output terminals 1Q to 3Q in sequence. It is output from the inverting output terminals 1Q to 3Q. Then, the NAND circuit 5 and the NAND circuit 6 are supplied with these shift signals, and as a result, as shown in FIG. 2, the edge detection signal a corresponding to the fall and rise of the reproduction signal PBSG.
・ B will be output. In addition, the EX-OR circuit 7
Outputs an edge detection signal h corresponding to both the falling edge and the rising edge of the reproduction signal PBSG.

The edge detection signals a and b are input to the H counter circuit 3 and the L counter circuit 4, respectively. At this time, the master clock signal MCK is input to the clock terminals CK and CK of the H counter circuit 3 and the L counter circuit 4, and the shift enable signal from the shift register circuit 2 is input to the count enable terminals E and E. c and d have been entered. Then, the H counter circuit 3 counts the H level "1" section of the reproduction signal PBSG by these signals, and the L counter circuit 4 counts the L level "0" section of the reproduction signal PBSG. .. In the example of FIG. 2, the H counter circuit 3 is used for the cycles 1T, 3T, 1T, 2T, ... Of the reproduction signal PBSG.
And L counter circuit 4 are alternately 12, 25, 14, 1
Counting as 5, ...

The above count value is the count signal ef
While being switched by the shift signal c input to the multiplexer circuit 8 as
The count signal g is input to the latch circuit 9 and latched. The latch circuits 9, 10 and 11 form a shift register, and the count signal i of the latch circuit 9 is sequentially shifted to the latch circuit 10 and the latch circuit 11 by the edge detection signal h. Then, the count signals i.j.k output from the latch circuits 9.10.11 are input to the decoder circuit 12.

The count signals i.j.k input to the decoder circuit 12 are stored in the ROM 15.1 as shown in FIG.
It will be input to 6 ・ 17. Here, for example, in FIG.
The operation after time t ₁ will be described. Since the count signal j has a count value of “12” at time t ₁ ,
The ROM 16 outputs the output value of "1" as shown in Table 2. The output value of "1" is input to the ROMs 15 and 17 as the control signal r, so that the correction signals p and q of "0" are output from the ROMs 15 and 17. Therefore, the adder 18 adds "0", "12", and "0", and the addition value "1".
2'is output to the ROM 19 as the addition signal o, and the ROM 19 outputs '1' corresponding to '12' of the addition signal o as the decoding signal l as shown in Table 3.

Further, at the time point t ₂ , the count signal j becomes "2".
Since the count value is 5 ', the ROM 16 outputs an output value of' 0 'as shown in Table 2. The output value of "0" is used as the control signal r in the ROM 15
・ By inputting in 17, as shown in Table 1,
The ROMs 15 and 17 output the correction signals p and q of "4" and "2" corresponding to "25". Therefore, the adder 18 adds "4", "25", and "2", and the addition value "31" is added to the RO as the addition signal o.
As shown in Table 3, the ROM 19 will output "3" corresponding to "31" of the addition signal o as the decode signal l.

After that, the decode signal 1 is input to the down counter circuit 20 of the pulse generating circuit 13, as shown in FIG.
Sets the value of the decode signal 1 when the edge detection signal h is input, counts down this value for each input of the master clock signal MCK to the clock terminal CK, and outputs from the output terminals Q _A , Q _B, and Q _C by the OR circuit. 21 and outputs the L level from the OR circuit 21 when all the signals from the output terminals Q _A , Q _B, and Q _C become the L level, thereby stopping the output of the NAND circuit 22 and decoding the decoded signal. The number of clock pulse signals n corresponding to the value of 1 is output to the demodulation circuit 14. Further, the T-FF circuit 23 outputs the data signal m, which is inverted every time the edge detection signal h is input, to the demodulation circuit 14.

As described above, the data pulse generator of this embodiment uses the count signals i · k before and after the count signal j for correction when determining the period of the clock pulse signal n or the like from the count signal j. Therefore, the probability of misjudgment is reduced as compared with the case where the period is obtained from only the count signal j.

The decoder circuit 12 in this embodiment is used.
Is composed of the ROMs 15, 16, 17, 19 and the adder 18, and is adapted to form the decoded signal 1 by the above-mentioned calculation procedure, but the present invention is not limited to this. That is, the decoder circuit 12 sums up the count value of the count signal j and the count values of the count signals i · k that precede and follow the count signal j, and the count signal i
The value obtained by adding a predetermined value such as '10' to the cycle indicated by k is subtracted from the above total value, and the cycle of the count signal j is obtained by comparing the subtracted value with Table 3. Is also good.

[Embodiment 2] Next, another embodiment of the present invention will be described with reference to FIGS. 5 to 7.

The data pulse generator according to this embodiment is
As shown in FIG. 5, it has an H counter circuit section. This H counter circuit section is provided with a first shift register circuit 2 '.
(Counter means, counter correction means) and the second shift register circuit 24 (counter correction means).
The first shift register circuit 2 ′ has a D terminal to which the reproduction signal PBSG is input, a CK terminal to which the master clock signal MCK is input, and an output terminal which outputs a shift signal obtained by shifting the master clock signal MCK by one clock. It has 1Q to 3Q and inverting output terminals 1Q to 3Q, and takes in the reproduction signal PBSG at the rising edge of the master clock signal MCK and outputs the shift signal. The output terminal 1Q and the inverting output terminal 2Q of the first shift register circuit 2'are respectively connected to the input terminals of a 2-input NAND circuit 5 '(counter means), and the NAND circuit 5'reproduces the reproduction signal PBSG. Edge detection signal a ′ indicating the rising edge of
Is to be output.

On the other hand, the second shift register circuit 24 has a D terminal to which the reproduction signal PBSG is input, an inverted CK terminal to which the master clock signal MCK is input, and a shift signal obtained by shifting the master clock signal MCK by one clock. Output terminals 1Q to 3Q and inverting output terminals 1Q to 3Q for outputting the master clock signal MC.
Capture the playback signal PBSG at the falling edge of K,
The shift signal is output. The output terminal 3Q of the second shift register circuit 24 is 2
It is connected to one input terminal of an input NAND circuit 25 (counter correction means).

The other input terminal of the NAND circuit 25 is connected to the inverting output terminal 3Q of the above-mentioned first shift register circuit 2 ', and the NAND circuit 25 outputs the output terminal of the second shift register circuit 24. By inputting the shift signal of 3Q before the shift signal of the inverting output terminal 3Q of the first shift register circuit 2 ', the reproduced signal PB
An edge detection signal t indicating the rising edge of SG is output.

The output terminal of the NAND circuit 25 is connected to the clock terminal CK of the correction counter circuit 26 (counter correction means). In addition, the correction counter circuit 26
The output terminal of the NAND circuit 5 ′ described above is connected to the inverting reset terminal R of the count enable terminal E.
A reset signal of "1", which is an H level, is input to. Then, the correction counter circuit 26
Has its output terminals Q ₀ and Q ₁ connected to _one input terminal B ₀ and B ₁ of a two-input adder 27 (counter correction means).

The NAND circuit 5'connected to the inverting reset terminal R of the correction counter circuit 26 is also connected to the inverting reset terminal R of the H counter circuit 3 '(counter means). The output terminal 2Q of the first shift register circuit 2'is connected to the count enable terminal E of the H counter circuit 3 ', and the master clock signal MCK is input to the clock terminal CK. .. The output terminals Q _{0 to} Q _{5 of} the H counter circuit 3 '
Is connected to the other input terminals A _{1 to} A ₆ of the adder 27, and the adder 27 has both input terminals A _{1 to} A _6.
The values input to B ₀ and B ₁ are added and output as the count signal e of the H level portion.

The circuit configuration of the H counter circuit section is such that the master clock signal MCK and the reproduction signal PBS are
The circuit configuration is the same as that of the L counter circuit unit that generates the count signal f from the G level to the L level, and the other circuit configuration of the data pulse generator of the present embodiment is the same as the circuit configuration of the first embodiment described above. Since they are equivalent, description of these circuit configurations will be omitted.

The operation of the data pulse generator having the above structure will be described.

The reproduced signal PBSG is taken into the first shift register circuit 2'at the rising edge of the master clock signal MCK, and the shift signals obtained by shifting the master clock signal MCK by one clock are sequentially output. Further, the reproduction signal PBSG is taken into the second shift register circuit 24 at the falling edge of the master clock signal MCK.

Output terminal 1 of the first shift register circuit 2 '
The shift signals from Q and the inverted output terminal 2Q are input to the NAND circuit 5'as shown in FIGS. 6 and 7, and the NAND circuit 5'detects the edge corresponding to the rising edge of the reproduction signal PBSG. The signal a'will be output.

The shift signal from the output terminal 3Q of the first shift register circuit 2'and the shift signal from the inverting output terminal 3Q of the second shift register circuit 24 are NAN.
It is input to the D circuit 25, and the NAND circuit 25
Is the first latched reproduction signal PBSG at the rising and falling edges of the master clock signal MCK, respectively.
The edge detection signal t corresponding to the output difference between the shift register circuit 2'and the second shift register circuit 24 is output. That is, the edge detection signal t is the master clock signal MCK when the reproduction signal PBSG rises.
Will be output when the latch by the falling edge precedes the latch by the rising edge of, or at the falling edge of the reproduction signal PBSG, the rising edge by comparison with the latch by the falling edge of the master clock signal MCK. Will be output when the latch by is precedent.

The edge detection signal a ′ is supplied to the H counter circuit 3 ′ and the reset terminal R · R of the correction counter circuit 26.
Will be input respectively. Further, the master clock signal MCK is input to the clock terminal CK of the H counter circuit 3 ′, and further, the H counter circuit 3 ′.
A shift signal from the output terminal 2Q of the first shift register circuit 2'is input to the count enable terminal E of the. Then, the H counter circuit 3'counts the '1' section of the reproduction signal PBSG based on the input signal, and the count signal e'is input terminal A ₁ of the adder 27.
To output to A ₆ . The count signal e '
Is shifted by 1 bit from the output terminals Q _{0 to} Q ₅ to the input terminals A _{1 to} A ₆ , and is input.
It will be input as the double count signal e ′.

At this time, as shown in FIG. 6, when the edge detection signal t is input to the correction counter circuit 26, the correction counter circuit 26 starts counting, and this count value is added as the correction signal s by the adder. 27 input terminals B ₀ and B ₁
Will be output to. On the other hand, as shown in FIG. 7, when the edge detection signal t is not input to the correction counter circuit 26, the correction counter circuit 26 does not start counting, and “0” is set as the correction signal s at the input terminal of the adder 27. B
It will be output to ₀ · B ₁ .

The correction signal s and the count signal e'are added together by the adder 27, and the count value is output as the count signal e of the H level portion.

As a result, the count signal e'which does not use the correction signal s and is equivalent to that of the conventional one, as shown in FIGS. 6 and 7, has the same time length ta as the master clock signal MCK.
Despite the fact that tb is a different count value of '7' and '8' despite tb, both count signals e using the correction signal s show a count value of '16'. It has become. Therefore, in the data pulse generator of this embodiment, the count signal e is ± 1 from the count error of ± 1.
It is possible to reduce the count error to 0.5, which in turn makes it possible to reduce the probability of erroneous determination when determining the cycle. The operation after outputting the count signal e is the same as that of the first embodiment, and therefore the description thereof is omitted.

[0066]

As described above, the data pulse generator according to the first aspect of the present invention counts the time lengths of the first level portion and the second level portion of the data signal, and based on these count values. For outputting a clock pulse signal corresponding to the cycle of each level part, and a plurality of stages of latch means for sequentially latching the count value, and a cycle of the count values latched by these latch means. And a cycle determining unit that uses a count value before and after the count value of the level unit for determining when the cycle is determined.

As a result, since the count value before and after the count value of the level portion for judging the cycle is used for the correction at the time of judging the cycle, it is more erroneous than the case of obtaining the cycle only from the count value of the level portion for judging the cycle. This has the effect of reducing the probability of making a decision.

Further, the data pulse generator according to the invention of claim 2 counts the time lengths of the first level portion and the second level portion of the data signal as described above, and based on these count values. For outputting a clock pulse signal corresponding to the cycle of each level section, the counter section counting the level section by using one of the rising edge and the falling edge of the clock signal, and the level section. A counter correction means for determining the positional relationship between the start edge and the other edge of the clock signal, and incrementing the count value by 1 when the start edge is positioned before the other edge. is there.

As a result, since the count value is corrected when the start edge is positioned before the other edge, it is equivalent to the case where counting is performed using both edges. As a result, the count value is counted by ± 1. Since the error can be reduced to a count error of ± 0.5, it is possible to reduce the probability of erroneous determination when obtaining the cycle from the count value.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a data pulse generator of the present invention.

FIG. 2 is an explanatory diagram showing a signal state of a data pulse generator.

FIG. 3 is a circuit diagram of a decoder circuit.

FIG. 4 is a circuit diagram of a pulse generation circuit.

FIG. 5 is a circuit diagram of an H counter circuit unit.

FIG. 6 is an explanatory diagram showing a signal state of an H counter circuit section.

FIG. 7 is an explanatory diagram showing a signal state of an H counter circuit section.

FIG. 8 is an explanatory diagram showing a state of a reproduction signal used in a conventional example.

[Explanation of symbols]

1 Oscillator 2 Shift Register Circuit 2'First Shift Register Circuit (Counter Means, Counter Correcting Means) 3 H Counter Circuit 3'H Counter Circuit (Counter Means) 4 L Counter Circuit 8 Multiplexer Circuit 9/10/11 Latch Circuit (Latch Means) 12 Decoder circuit (cycle determination means) 13 Pulse generation circuit 14 Demodulation circuit 15 to 17-19 ROM 18 Adder 20 Down counter circuit 23 T-FF circuit 24 Second shift register circuit 26 Correction counter circuit (counter correction means) 27 adder (counter correction means)

Claims (2)

[Claims] 1. A data pulse for counting the time lengths of a first level portion and a second level portion of a data signal and outputting a clock pulse signal corresponding to the cycle of each level portion based on these count values. In the generator, a plurality of stages of latch means for sequentially latching the count value and count values before and after the count value of the level part for judging the cycle among the count values latched by these latch means are provided. A data pulse generator, comprising: a cycle determining means used for correction when determining a cycle. 2. A data pulse for counting a time length of a first level portion and a second level portion of a data signal and outputting a clock pulse signal corresponding to a cycle of each level portion based on these count values. A generator, which is a counter means for counting the level part using one of the rising edge and the falling edge of the clock signal, and the positional relationship between the starting edge of the level part and the other edge of the clock signal. And a counter correction means for correcting the count value when the start edge is positioned before the other edge.