JPH0511024A - Data generating system for ic tester - Google Patents

Abstract

PURPOSE:To easily generate an irregular data pattern by only changing addresses by providing a memory which stores the inverted information of data at every address and writing the inverted information in the memory by means of software. CONSTITUTION:A data pattern memory 2 stores arbitrary data patterns at every address and an area inverting memory 3 stores data patterns for inverting data of specific areas. The inverted information corresponding to input addresses are outputted from the memories 2 and 3 in accordance with addresses inputted from an address input terminal 4. A data generating section 5 outputs final data to a data output terminal 6 by exclusive ORing data from an input terminal 1 for pattern data (information of '0' or '1' indicating the presence/absence of inversion of bit information) and the data outputted from the memories 2 and 3. The generation of complicated data patterns is made easier by constituting the memory 2 in such a way that the memory 2 stores inverted information at every address and can operate stored patterns by means of software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data generation method for an IC tester, and more particularly to an ALPG (A
lgolithic Pattern Genera
to generate write data and expected value data I
The present invention relates to a data generation method of a C tester.

[0002]

2. Description of the Related Art Conventionally, an ALP for this type of memory IC test
The generation unit of G write data and expected value data has a structure as shown in FIG. The data generator 5 takes the exclusive OR of the pattern data, the address function 7, and the area inversion memory 3, and outputs the result as data. Here, the pattern data is information of "0" and "1" indicating whether the bit is inverted or not. The address function 7 may be a function between the arrangement of the data written in the memory and the address. The address function facilitates the generation of data by preparing this function.

An example of the address function is shown in FIGS. FIG. 4A shows CHECKERBOARD X, Y.
When the exclusive OR of the least significant bits X ₀ and Y ₀ of the address is "1", the data is inverted. Part 4 (b) is ROW
The data is inverted when the least significant bit X ₀ of the X address is “1” in BAR. FIG. 4C shows a COLUMN BA.
When the least significant bit Y ₀ of the Y address is “1” in R, the data is inverted.

The area inversion memory 3 is for inverting the data in a specific area. For example, DRAM (Dyn
atomic Random Access Memor
In the case of y), in order to maintain the electrical balance, the input / output data and the data held in the cell are inverted at a specific address, so the data is inverted to make the cell data similar to the input / output data. There is a need to. The area inversion memory 3 stores the inversion information for each address.

[0005]

In the above-mentioned conventional technique, the generation of data is easily realized by using the address function. However, the pattern that can be generated is a regular pattern, and the pattern of the IC tester is used in advance. It has to be built into hardware and software, and has the disadvantage of lacking freedom. The generation of irregular data patterns was realized by complicated operations of patterns and programs.

[0006]

A data generation method of an IC tester according to the present invention comprises a data input terminal for indicating whether bit information is inverted, an area inversion memory, and a data pattern for storing an arbitrary data pattern. A memory and a data generator that creates actual input / output data from the above three data.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
The pattern data input terminal 1 inputs data of "0" and "1" indicating whether bit information is inverted, and the data pattern memory 2 stores an arbitrary data pattern for each address. The area inversion memory 3 stores a data pattern for inverting the data in the specific area. Inversion information corresponding to the input address is output from the data pattern memory 2 and the area inversion memory 3 according to the address input from the address input terminal 4.

The data output from the pattern data input terminal 1 and the data output from the data pattern memory 2 and the area inversion memory 3 are exclusive ORed by the data generator 5 to output the final data. Output to terminal 6.
Like the conventional area inversion memory 3, the data pattern memory 2 has inversion information for each address and makes it possible to operate the stored pattern by software so that a complicated data pattern can be easily generated. To do.

FIGS. 2A to 2C are diagrams showing an example of data generation according to the present invention. When the pattern data is “0”, the result of (data pattern memory shown in FIG. 2A) + (region inversion memory shown in FIG. 2B) + (pattern data) is shown in FIG. Obtain the occurrence data of c).

[0010]

As described above, according to the present invention, the IC
Data pattern in the data generator of the ALPG of the tester
A memory, that is, a memory for storing inversion information of each address is provided so that the inversion information can be written by software, an arbitrary data pattern is stored, and three data of the data of the area inversion memory and the inversion data of bit information are stored. By taking the exclusive OR of, not only the simple regular data pattern realized by the address function, but also the non-regular data pattern realized by the complicated operation of the pattern program Also has the effect that it can be easily generated only by changing the address.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A to 2C are diagrams showing an example of data generation according to the present invention.

FIG. 3 is a block diagram showing a conventional example.

4A to 4C are diagrams showing an example of an address function.

[Explanation of symbols] 1 pattern data input terminal 2 data pattern memory 3 area inversion memory 4 Address input terminal 5 Data generator 6 Data output terminal 7 Address function

Claims (2)

[Claims] 1. In a data generation method of an IC tester for generating write data of ALPG and expected value data used during a test of a memory part of an IC tester, a memory for storing data inversion information for each address is provided, and the inversion information is provided. Is written in the memory, an arbitrary data pattern is created, and data can be generated only by changing the address. 2. An input / output terminal for data indicating whether bit information is inverted, an area inversion memory, a data pattern memory for storing an arbitrary data pattern, and actual input / output data from the three data. A data generation method of an IC tester, which includes a data generation unit to be created.