JPH05109882A - Manufacture of semiconductor - Google Patents

Abstract

PURPOSE:To prevent an interconnection from being cut at a stepped part due to the difference in level of an isolation groove part which has been formed in an SOI substrate and to prevent a short circuit from being caused. CONSTITUTION:A field oxide film 8 is formed on the main face of an SOI layer composed of a second silicon substrate 3 which has been formed on an insulating film 2. A silicon nitride film 9 and an SiO2 film 10 are formed sequentially. After that, isolation grooves 13 which reach the insulating film 2 are formed by an R. I. E. operation by making use of the SiO2 film 10 as a mask. Insulating films 13 are formed on the inner wall surface of the isolation grooves 12; in addition, polycrystalline silicon 14 is filled into the isolation grooves 12. While a control operation is being executed in such a way that the upper end of the polycrystalline silicon 14 inside the isolation grooves 12 becomes higher than the upper end of the silicon nitride film 9, the polycrystalline silicon 14 is etched back, and the polycrystalline silicon 14 on the surface of the substrate is removed. Then, the SiO2 film 10 is etched and removed while the poly-crystalline silicon 14 inside the isolation grooves 12 and the silicon nitride film 9 are used as etching stoppers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, SOI (Silicon On Ins).
ultor) separation of elements in a substrate.

[0002]

2. Description of the Related Art Conventionally, as an element isolation method used for a monolithic semiconductor integrated circuit, a method of isolating elements with an insulator has been known. For example, JP-A-61-5
Japanese Patent No. 9852 discloses a method of manufacturing a semiconductor device in which a separation groove is formed in a bonded SOI substrate to perform element separation. In this method, two silicon substrates are joined together via an insulating film to obtain an SOI substrate, and a trench isolation groove from one main surface of the SOI substrate to the insulating film in the substrate is formed, followed by thermal oxidation or the like. SO including the inner wall surface of the separation groove
I After forming an insulating film on the surface of the substrate and filling the separation groove with polycrystalline silicon, the insulating film and the polycrystalline silicon protruding from the separation groove on the surface of the substrate are removed, and an insulating material is provided between the substrate and the elements. They are completely electrically separated.

[0003]

By the way, in the above manufacturing process, when forming an isolation groove in an SOI substrate, it is general to form an oxide film as a mask on the surface of the substrate. Here, the oxide film as the mask is S
Since the insulating film has the same etching ratio as the insulating film for separating the substrates in the OI substrate, the insulating film is exposed in the separation groove immediately after the formation of the separation groove, and the oxidation as the mask is performed. When the film is to be removed by etching, the insulating film in the substrate is also etched at the same time. For this reason, it is general that the oxide film as the mask is filled with polycrystalline silicon to fill the isolation trench, and then is removed by etching after removing the insulating film.

However, in that case, it was found that when the oxide film as the mask is removed, the insulating coating formed on the inner wall surface of the separation groove is also etched in the depth direction. When the insulating film on the inner wall surface of the separation groove is etched, a severe step is formed on the substrate surface in the separation groove portion, and the polysilicon wiring or the Al wiring on the substrate surface is disconnected,
There is a problem that a short circuit occurs.

The present invention has been made in view of the above circumstances, and prevents the insulating film on the inner wall surface of the separation groove from being etched during the above process, thereby eliminating the step in the separation groove portion and disconnecting the wiring. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can eliminate the occurrence of short circuits and short circuits.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, the SO of an SOI layer set on an insulating substrate is
A step of sequentially depositing a first layer and a second layer on the main surface of the I layer, and a step of forming an opening in the first and second layers so as to expose a predetermined portion of the main surface of the SOI layer. , A step of etching the SOI layer through the opening using the second layer as a mask to form a separation groove reaching the insulating substrate, and forming an insulating film on the inner wall surface of the separation groove. A step of filling a filler into the separation groove through the opening to a position where an upper end of the filler is equal to or higher than the position of the first layer; and the filler and the first layer are insulated from each other. Removing the second layer as an etching preventive film for the coating;
Selectively removing the first layer.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, the first and second layers are sequentially formed on the main surface of the SOI layer, and the height of the filling material filling the separation groove is equal to or higher than the position of the first layer. Control to become. Therefore, when the second layer used as a mask for forming the separation groove is removed by etching, the insulating film formed in the separation groove is prevented from being etched by the filler and the first layer, and the insulating film is etched. Therefore, the step of the separation groove portion due to this is not generated.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. (First Embodiment) One main surface of a P ⁻ -type first single crystal silicon substrate 1 is mirror-polished and then thermally oxidized to form an insulating film 2 having a predetermined thickness. Then, a second single-crystal silicon substrate 3 having a mirror-polished main surface is adhered and heated on the surface of the first silicon substrate 1 on the side of the insulating film 2 in a sufficiently clean atmosphere to heat the respective silicon. The substrates 1 and 3 are integrally bonded so as to sandwich the insulating film 2. As a result, an SOI substrate configured by bonding the second silicon substrate 3 on the first silicon substrate 1 via the insulating film 2 is manufactured (see FIG. 1). In FIG. 1, reference numeral 4 indicates a second position before joining.
Is an N-type high-concentration impurity (Sb) layer formed by doping from the surface of the N ⁻ -type silicon substrate 3.

Then, a P well region 5, an N well region 6 and a deep N ⁺ region 7 are formed on the side of the second silicon substrate 3 which is an SOI layer by a series of oxidation, photolithography and impurity diffusion steps (FIG. 2). During this period, the growth and removal of the oxide film on the surface of the second silicon substrate 3 can be freely performed. Then, the field oxide film 8 is formed on the surface of the second silicon substrate 3 side by LOCOS (Local).
Oxidation of Silicon) method (see FIG. 3). In the LOCOS method, a pad oxide film 8a is formed on the surface of the substrate, a Si ₃ N ₄ film as an oxidation suppressing film is formed on a predetermined portion, and then a portion where the Si ₃ N ₄ film is not formed is thermally oxidized. The thick field oxide film 8 is formed by oxidization by, for example,
After oxidation by S method the Si ₃ N ₄ film is a diagram after removal by H ₃ PO _4.

Next, a first insulating layer is again formed on the substrate surface.
Si₃N_FourSiO as the film 9 and the second insulating layer₂film
10 are sequentially deposited by the CVD method, and annealed at 1000 ° C.
Is treated with SiO2₂The film 10 is densified. Continued
Then, deposit a resist (not shown), and
CF as graphic processing and etching gas_Four, CHF ₃
The R.I. I. E (Reactive Ion
 Etching) treatment, SiO₂Film 10, Si
₃N_FourThe film 9 and the field oxide film 8 are masked with a resist
As an etchant until the surface of the silicon substrate 3 is reached.
The openings 11 are formed by etching (see FIG. 4). Note that the figure
4 shows the state after the resist is peeled off.

Next, using the SiO ₂ film 10 as a mask, R.V. I. The second silicon substrate 3 is selectively etched by the E treatment,
The isolation trench 12 reaching the insulating film 2 is formed (see FIG. 5).
In this case, the deposition thickness of the SiO ₂ film 10 in the previous step is determined so that the isolation trench 12 reaches the insulating film 2 favorably by the etching selection ratio between the SiO ₂ film 10 and the silicon substrate 3.

Then, thermal oxidation is applied to the separation groove 1
Insulating film 13 is formed on the inner wall surface of 2, and then polycrystalline silicon 14 is deposited by LP-CVD. At this time,
The polycrystalline silicon 14 fills the isolation trench 12 and is also deposited on the SiO ₂ film 10 (see FIG. 6). Then, by dry etching, the polycrystalline silicon 14 deposited on the SiO ₂ film 10 is etched back (first time) (see FIG. 7). At this time, the separation groove 12
The etching is stopped so that the upper end of the polycrystalline silicon 14 remaining inside is located above the Si ₃ N ₄ film 9.

Next, the SiO ₂ film 10 is removed by etching by a wet etching process using a fluorine solution (see FIG. 8). At this time, the the Si ₃ N ₄ film 9, the Si ₃ N ₄
The polycrystalline silicon 14 left so that its upper end is above the film 9 serves as an etching stopper, and the insulating film 13 formed on the inner wall surfaces of the field oxide film 8 and the isolation trench 12 is not etched.

Next, by dry etching, Si ₃ N of the polycrystalline silicon 14 embedded in the isolation trench 12 is etched.
_{4 The} portion protruding above the film 9 is etched back (second time) (see FIG. 9). At this time, when a thermal oxide film 15 to be described later is grown on the upper side of the polycrystalline silicon 14 in the next step, the polycrystalline silicon 14 and the surrounding field oxide film 8 have the same height so that the thermal oxide film 15 and the surrounding field oxide film 8 have the same height. It is desirable to control the upper end of the field oxide film to be lower than the upper end of the field oxide film 8 by about 0.3 μm.

Next, the upper portion of the polycrystalline silicon 14 embedded in the isolation trench 12 is selectively thermally oxidized by the Si ₃ N ₄ film 9 to grow an oxide film 15 (see FIG. 10). The Si ₃ N ₄ film 9 is removed by etching (see FIG. 11). As is clear from FIG. 11, a step is not formed in the separation groove 12 portion and has a flat shape. Next, after removing the pad oxide film 8a, a thin gate oxide film is formed, and L
Polycrystalline silicon wiring (gate electrode) 16 is formed by performing P-CVD processing, photolithography and etching processing, and P ⁺ diffusion layer 1 is formed by selective doping.
7, N ⁺ diffusion layer 18 is formed (see FIG. 12). During this period, the etching of the field oxide film 8 is about 0.2 .mu.m, and the flatness of the isolation trench 12 portion is not impaired.

Subsequently, an interlayer insulating film 1 of PSG, BPSG, etc.
9 is deposited, a contact hole is formed in a necessary portion,
Al wiring 20, a nitride film formed by plasma CVD, etc.
The protective film 21 is formed, and the CMOS transistor and the bipolar transistor are formed.
Bi-CMOS semiconductor device with integrated transistor
The device is manufactured (see FIG. 13). Thus, the present embodiment
According to the manufacturing method of the
₂Si is removed when the film 10 is removed by etching.₃N_FourMembrane 9 and multi
The crystalline silicon 14 is used to etch the underlying oxide film.
The progress of ching is prevented. Therefore, the step of the separation groove 12 part
No difference is formed and a flat shape is obtained.
Then, the polysilicon wiring 16 and the Al wiring 20 are disconnected,
No traditional problems such as riot occur.

Although the field oxide film 8 is formed in advance by the LOCOS process in the above embodiment,
In addition, a pad silicon oxide film having a uniform thickness is formed, a separation groove is formed after depositing a Si ₃ N ₄ film and a SiO ₂ film by CVD, and an insulating film on the inner wall surface of the separation groove is formed. After filling the inside with polycrystalline silicon, etching back the polycrystalline silicon, and removing the SiO ₂ film by etching using the polycrystalline silicon and the Si ₃ N ₄ film as etching stoppers, the Si ₃ N ₄ film is patterned or Si
After reloading the ₃ N ₄ film, the pad silicon oxide film may be subjected to a LOCOS process to form a field oxide film.

In the above embodiment, the SiO ₂ film formed by CVD is used as an oxide film used as a mask when forming the isolation trench.
Although the film is shown as being formed, a PSG film (Phospho Silicate Glass) may be formed instead. Furthermore, in the first embodiment, the first etching back of the polycrystalline silicon 14 is performed by the dry etching process, but it may be performed by the polishing technique. Illustrating Second Embodiment Hereinafter a second embodiment using a polycrystalline silicon film 9 'in place of the Si ₃ N ₄ film 9 of the first embodiment.

After passing through the steps shown in FIGS. 1 to 3 described above,
Polycrystalline silicon film 9 'by LP over CVD in this embodiment, SiO ₂ is deposited film 10 by CVD, similarly to the step shown in FIG. 4 described above, an annealing process 1000 ° C., densify the SiO ₂ film 10 Turn into. Subsequently, a resist is deposited, a photolithography process is performed to form a resist pattern, and CF ₄ , CHF _{3 are used} as an etching gas.
The R.I. I. SiO ₂ film 10 by E treatment,
Opening 1 in polycrystalline silicon film 9'and field oxide film 8
1 is formed, and the Si ₃ N ₄ film 22 is deposited on the substrate surface (see FIG. 14). Then, the anisotropic R.I. I. E treatment is applied to leave the Si ₃ N ₄ film 22 only on the side wall of the opening 11 (see FIG. 15). The Si ₃ N ₄ film 22 prevents the polycrystalline silicon film 9 ′ exposed in the opening 11 from being simultaneously oxidized when the insulating film 13 is formed on the inner wall of the separation groove 12 by thermal oxidation in a later step.

Next, using the SiO ₂ film 10 as a mask, an R.V. I. Then, the second silicon substrate 3 is selectively etched by the E treatment to form the isolation trench 12 reaching the insulating film 2. Then, the inner wall surface of the separation groove 12 is thermally oxidized to form the insulating coating film 13, and then the Si ₃ N ₄ film 22 covering the wall surface of the opening 11 is removed by the H ₃ PO ₄ liquid (see FIG. 16). ..
As described above, when the insulating coating 13 is formed, the opening 1
The polycrystalline silicon film 9'is not exposed by the Si ₃ N ₄ film 22 in 1 and is not oxidized. Here, if the polycrystalline silicon film 9 ′ is oxidized, the oxidized portion of the polycrystalline silicon film 9 ′ is simultaneously etched by the etchant when the SiO ₂ film 10 is removed by etching in a later step. As a result, a step is generated in the separation groove 12 portion.

Then, similarly to the step shown in FIG.
After depositing the polycrystalline silicon 14 (see FIG. 17), the Bi-CMOS semiconductor device shown in FIG. 13 is manufactured through the same steps as the steps shown in FIGS. 7 to 13 described above. In this embodiment, the polycrystalline silicon film 9'and the separation groove 12 are used.
The polycrystalline silicon 14 filled inside is the SiO ₂ film 10.
It acts as an etching stopper at the time of removal and prevents the field oxide film 8 and the insulating film 13 under the polycrystalline silicon film 9 ′ from being simultaneously etched. Further, since the polycrystalline silicon film 9'has no oxidized portion as described above, the etching does not proceed from there to the lower layer.

Further, in the second embodiment, the polycrystalline silicon film 9'can be removed simultaneously with the second etching back of the polycrystalline silicon film 14.

[0023]

As described above in detail, according to the method of manufacturing a semiconductor device of the present invention, since a flat substrate surface can be obtained without causing a step in the isolation trench portion, polycrystalline silicon wiring and Al can be obtained. It is possible to manufacture a semiconductor device without disconnection of wiring or short circuit.

[Brief description of drawings]

FIG. 1 is a process drawing showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 2 is a process drawing showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 4 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 5 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 6 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 7 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 8 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 9 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 10 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 11 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 12 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 13 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 14 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment.

FIG. 15 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment.

FIG. 16 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment.

FIG. 17 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment.

DESCRIPTION OF SYMBOLS 1 is a first silicon substrate, 2 is an insulating film, 3 is a second silicon substrate, 8 is a field oxide film, 9 is a Si ₃ N ₄ film forming a first insulating layer, and 9 ′ is A polycrystalline silicon film forming a first insulating layer, 10 a SiO ₂ film forming a _second insulating layer, 11
Is an opening, 12 is an isolation groove, 13 is an insulating coating, and 14 is polycrystalline silicon.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Sakakibara 1-1-1, Showa-cho, Kariya city, Aichi Prefecture Nihondenso Co., Ltd.

Claims (1)

[Claims] 1. A step of sequentially depositing a first layer and a second layer on the SOI layer main surface of an SOI layer set on an insulating substrate, and exposing a predetermined portion of the SOI layer main surface. Therefore, the first,
A step of forming an opening in the second layer; a step of etching the SOI layer through the opening using the second layer as a mask to form a separation groove reaching the insulating substrate; Forming an insulating coating on the inner wall surface of the separation groove; filling the inside of the separation groove with a filler through the opening to a position where the upper end of the separation groove is equal to or higher than the position of the first layer; A semiconductor device comprising: a step of removing the second layer using a material and the first layer as an etching prevention film of the insulating coating; and a step of selectively removing the first layer. Manufacturing method.