JPH05109267A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To improve a yield and to reduce a manufacturing cost by reducing the chip size of a semiconductor memory circuit. CONSTITUTION:A row address inputted to a decoder 102 is decoded and outputted to memory cell arrays 101, 102. A write column address inputted to the decoder 104 is inputted to registers 106, 126. A read column address inputted to the decoder 108 is inputted to selectors 110, 130. Data stored in the memory cell array 101 is read after the lapse of 1H (horizontal scanning interval) and simultaneously stored in the memory cell array 121. The data stored in the memory cell array 121 is read after the lapse of 1H further.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit used as a video signal delay circuit.

[0002]

2. Description of the Related Art A conventional semiconductor memory circuit will be described with reference to FIG.

FIG. 3 is a block diagram of a conventional semiconductor memory circuit. This semiconductor memory circuit constitutes a so-called line memory used for a delay circuit of an NTSC format video signal. This semiconductor memory circuit. Memory cell array 301 and decoders 302, 304, 308
And the buffers 303, 305, 309 and the register 30
6, the input / output circuit 307, the selector 310, and the precharge circuit 311.

A row address is input to the decoder 302. The decoder 302 decodes the row address,
The row address decode signal is output to the buffer 303. A word line is connected to the output terminal of the buffer 303. This word line is input to the memory cell array 301. The word line control signal WD is applied to the decoder 302.
Has been entered in. The decoder 302 decodes the row address only when the logic level of the word line control signal WD is “H”. Therefore, one of the word lines is activated.

A write column address is input to the decoder 304. The write column address decode signal output from the decoder 304 is input to the register 306 via the buffer 305. When 8-bit data is input to the register 306, this data is stored in a predetermined register of the register 306 designated by the write column address. The data stored in the register 306 is output to the input / output circuit 307. I / O circuit 30
The logic level of the write enable signal WE input to 7 is "
In the case of H ″, the data input to the input / output circuit 307 is written in the memory cell array 301.

The read column address is input to the decoder 308. The read address decode signal output from the decoder 308 is input to the selector 310 via the buffer 309. On the other hand, when the logic level of the write enable signal WE is “L”, the data written in the memory cell array 301 is output to the selector 310 via the input / output circuit 307. The selector 310 outputs 8-bit data designated by the read column address.

In such a semiconductor memory circuit, when video signal data is input to the semiconductor memory circuit, it is stored in the semiconductor memory circuit. Furthermore, 1H (1 horizontal scanning period)
After the elapse, the data is read from the semiconductor memory circuit. That is, the data delayed by 1H is output. Therefore, by using this semiconductor memory circuit as a 1H delay circuit,
A 1H delay circuit can be constructed. Furthermore, by using two semiconductor memory circuits, a 3-line Y / C separation circuit, a 3-line noise reduce circuit, etc. can be configured.

In order to meet such a purpose of use, a plurality of the semiconductor memory circuits have been provided on the same chip. That is, a plurality of the decoders, the memory cell arrays, the buffers and the like are arranged on the same chip.

[0009]

However, in the conventional semiconductor memory circuit, if a plurality of memory cell arrays, decoders, buffers, etc. are formed on the same chip, the chip size becomes large, so that the yield is lowered, and There were problems such as increased costs.

[0010]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to improve the yield and further reduce the manufacturing cost by reducing the chip size of the semiconductor memory circuit.

[0011]

A semiconductor memory circuit according to a first aspect of the present invention includes a row address decoder for decoding a row address signal and outputting a row address decode signal, and a write column address signal for decoding a write column address signal. A write column address decoder that outputs an address decode signal, a read column address decoder that decodes a read column address signal and outputs a read column address decode signal, the row address decode signal and the write column address decode signal when writing data In a semiconductor memory circuit having a memory cell array in which the row address decode signal and the read column address decode signal are input at the time of data read and an address is designated, the semiconductor memory circuit is configured. Row add Sudekoda, the write column address decoder, and the respective number of the read column address decoder is a singular number of the memory cell array constituting the semiconductor memory circuit is characterized in that it is a multiple.

[0012]

The semiconductor memory circuit according to the invention of claim 1 is
The row address is input to the row address decoder. The row address decoder outputs the row address decode signal to the plurality of memory cell arrays. The write column address is input to the write column address decoder. The write column address decoder outputs a write column address decode signal to the plurality of memory cell arrays. Then, data is written in the memory cell at the address specified by the row address and the write column address.

On the other hand, the read column address is input to the read column address decoder. The read column address decoder outputs a read column address decode signal to the plurality of memory cell arrays. Then, data is read from the memory cell at the address specified by the row address and the read column address.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory circuit according to the first embodiment of the present invention. The semiconductor memory circuit according to this embodiment includes a memory cell array 101 and a buffer 1.
03, 105, 109, a register 106, a selector 110, an input / output circuit 107, and a precharge circuit 11
1 and a first semiconductor memory circuit including a memory cell 121
And the buffers 123, 125, 129 and the register 12
6, a selector 130, an input / output circuit 127, a second semiconductor memory circuit including a precharge circuit 131, and decoders 102, 104, and 108. Note that these are configured on the same chip.

The memory cell array 101 includes 130 word lines, 56 sets (positive logic and negative logic) of digit lines, and 5 word lines.
6 bits × 130 words = 7280 bits of memory cells. Here, the NTSC format video signal is sampled at a frequency four times the color subcarrier frequency (about 14 MHz) and quantized with 8 bits. Then, the 1H (horizontal scanning period) video signal is converted into 910 × 8 = 7280 bit data. Therefore, 1H data can be written in the memory cell array 101.

The precharge circuit 111 has a function of setting all digit lines of the memory cell array 101 to a high level when a precharge signal is input, and preventing the destruction of data in the memory cell at the time of reading.

A row address is input to the decoder 102. Further, the word line control signal WD is supplied to the decoder 1
When the logic level of the word line control signal WD is “H”, the decoder 102 decodes the row address and outputs the row address decode signal to the 130 signal lines. These row address decode signals are input to the buffer 103. The buffer 103 is composed of a non-inverter, and outputs each row address decode signal to 130 word lines. Therefore, the logic level of one of the word lines becomes "H" according to the row address, and the memory cell connected to the word line is activated.

The write column address is input to the decoder 104. The decoder 104 decodes the write column address and outputs the write column address decode signal to the register 106 via the buffer 105. The register 106 has seven 8-bit internal registers.
8-bit data is input to the register 106 and written in the 8-bit internal register designated by the write column address. 7 × 8 written in register 106
= 56-bit data is output to the input / output circuit 107. The output terminal of the input / output circuit 107 is connected to the digit line of the memory cell array 101. Input / output circuit 10
The logic level of the write enable signal WE input to 7 is "
When it becomes H ″, the 56-bit data is written to the row designated by the row address in the memory cell array 101 via the digit line.

The read column address is input to the decoder 108. The decoder 108 decodes the read column address and outputs the read column address decode signal to the selector 110 via the buffer 109. On the other hand, when the logic level of the write enable signal WE is “L”, 56-bit data of the memory cells in one row of the memory cell array designated by the row address is input via the input / output circuit 107 to the selector 110. Is output to. This 5
The 6-bit data is divided and held in seven 8-bit internal registers in the selector 110. Selector 110
The read column address decode signal input to
Any of the seven 8-bit internal registers is selected. Then, the data A held in the 8-bit internal register is output. That is, the data A delayed by 1H is output from the first semiconductor memory circuit.

Further, the data A output from the first semiconductor memory circuit is input to the second semiconductor memory circuit. The data A is written in the memory cell array 121 via the register 126 and the input / output circuit 127. The data A written in the memory cell array 121 is further delayed by 1H and output via the input / output circuit 127 and the selector 130. The output data B is delayed by 1H as compared with the data A, and is delayed by 2H with respect to the data input to the first semiconductor memory circuit. The second semiconductor memory circuit is configured similarly to the first semiconductor memory circuit. Therefore, description of other configurations and operations will be omitted.

The decoders 102, 104 and 108 are commonly used for the first and second semiconductor memory circuits. Therefore, the second designated by these decoders
The address of the memory cell array 121 of the semiconductor memory circuit is the same as the address of the memory cell array 101 of the first semiconductor memory circuit. Therefore, two memory cell arrays 1
Different addresses cannot be accessed for 01 and 121. However, in the semiconductor memory circuit used for the video signal delay circuit, the same address is accessed for each of the plurality of memory cell arrays, so that no problem occurs.

FIG. 2 is a block diagram of a semiconductor memory circuit according to the second embodiment of the present invention. The semiconductor memory circuit according to the present embodiment includes the first to fourth semiconductor memory circuits and the decoder 20.
2, 204, 205 and buffers 203, 223, 20
5, 225, 209 and 229 are formed on the same chip.

The first semiconductor memory circuit includes a memory cell array 201A, an input / output circuit 207A, and a register 206.
A, selector 210A, and precharge circuit 211A
It is configured to include and. Similarly, the second semiconductor memory circuit includes a memory cell array 201B and an input / output circuit 20.
7B, a register 206B, a selector 210B, and a precharge circuit 211B. The third semiconductor memory circuit is a memory cell array 201C and an input / output circuit 207.
C, a register 206C, a selector 210C, and a precharge circuit 211C. The fourth semiconductor memory circuit is a memory cell array 201D and an input / output circuit 207D.
And a register 206D, a selector 210D, and a precharge circuit 211D.

The semiconductor memory circuit according to this embodiment is composed of
It has a fourth semiconductor memory circuit, and the data D is the first
The data input to the semiconductor memory circuit is delayed by 3H. Therefore, this semiconductor memory circuit has a configuration that can be used for a 4H delay circuit.

In this semiconductor memory circuit, the number of the decoder 202 to which the row address is input, the decoder 204 to which the write column address is input, and the number of the decoder 205 to which the read column address are input are each singular. Two buffers are connected to each decoder. For example, the decoder 202 has a buffer 2
03 and 223 are connected. In addition, the buffer 20
Two memory cell arrays 201A and 201B are connected to 3. That is, the number of buffers is half the number of memory cell arrays. Since the load on the buffers increases, it is necessary to increase the drive capability of these buffers.

Therefore, the same number as the memory cell array,
The semiconductor memory circuit according to the present embodiment can have a smaller chip size than a semiconductor memory circuit provided with a decoder, a buffer, and the like.

[0028]

As described above, according to the present invention, by reducing the chip size of the semiconductor memory circuit, the yield can be improved and the manufacturing cost can be kept low.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a semiconductor memory circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional semiconductor memory circuit.

[Explanation of symbols]

 101 memory cell array 102 decoder (row address decoder) 104 decoder (write column address decoder) 108 decoder (read column address decoder) 121 memory cell arrays 201A to 201D memory cell array 202 decoder (row address decoder) 204 decoder (write column address decoder) 205 Decoder (read column address decoder)

Claims (1)

[Claims] 1. A row address decoder which decodes a row address signal and outputs a row address decode signal, a write column address decoder which decodes a write column address signal and outputs a write column address decode signal, and a read column address signal A read column address decoder that outputs a read column address decode signal, the row address decode signal and the write column address decode signal when writing data, and the row address decode signal and the read column address when reading data A semiconductor memory circuit having a memory cell array to which a decode signal is input and whose address is designated, wherein the row address decoder, the write column address decoder, and the preceding Each of the number of read column address decoder is a singular, the semiconductor memory circuit number of the memory cell array constituting the semiconductor memory circuit, wherein a plurality.