JPH05108346A - Random access pipeline register and data transfer device - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of each CPU device by reducing the load of the data transfer processing as much as possible among those processing of the CPU device in a multiprocessing system. CONSTITUTION:A data transfer control circuit 2 outputs a shift signal to 8 RAP consisting of a multistage register and transfers the data on a data transfer bus via the RAP. When the transfer of data is complete, the circuit 2 informs a CPU device 10 of the end of the data transfer. Thus the device 10 gives a command to a RAP 1 and also outputs a SEL signal to a register of a relevant stage when the date on a specific stage is processed. At the same time, a WR signal is outputted and the data are read at the CPU bus side and then written into the original register after processing. Under such conditions, the device 10 sends a transfer command to the circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a randomly accessible pipeline register and a data transfer device for parallel processing having the pipeline register.

[0002]

2. Description of the Related Art Recent advances in VLSI technology have led to the use of microprocessors in various devices.
In addition, some devices use multiple microprocessors to distribute the work to be performed by the devices and provide high performance. Although there are various methods for such parallel processing, FIG. 5 shows an example of a processing method of a device having a plurality of such processors, that is, a concept of a multi-processing system. The processing module i inputs data from the outside, processes it, and passes it to the processing module i + 1. The processing module i + 1 processes and processes the data passed from the processing module i. Thus, the data is output as output data through the required number of processing modules. FIG. 6 describes each processing module and the processing modules. Each processing module is basically a CP
It consists of a U device 10 and a local memory 11. Local memory
Reference numeral 11 includes a program area for operating the CPU device 10 and a work area for performing work. The i-th processing module writes the processed data to the FIFO (first-in first-out memory) 20 with the i + 1-th processing module. Meanwhile, processing module i
+1 CPU device 10 is a FIFO between processing module i and
When the data input to O20 is detected, the data is sequentially fetched and the local memory 11 in the self-processing module
Take in. The CPU device 10 processes the fetched data, and when the processing is completed, writes the data in the FIFO 21 between the processing module i + 2.

What has been described here is an example, and there are various implementation methods for such a processing method. For example, in FIG. 7, a DMA (direct memory access) controller 12 is used for reading and writing of the FIFO.
By doing so, it is possible to expect higher-speed data transfer than data transfer using the CPU device 10. Moreover, FIG. 8 shows FI
The dual port memory 13 is used instead of the FO. When the bus of the CPU device 10 and the bus for data transfer are made independent in this way, the CPU device 10 can perform other processing during data transfer.

[0004]

Attention is now paid to the processing of the processing module i + 1. CP of processing module i + 1
The U device 10 operates as shown in FIG. Of these processes, what the module should originally do is "to process and process data". Therefore, other processing becomes overhead time.

It is also possible to use the DMA controller 12 as shown in FIG. 7 to shorten the transfer time. However, the CPU device 10 cannot operate while the DMA controller 12 is operating, and the DMA controller 12 is activated and D
There is an interrupt process issued from the MA controller 12. Therefore, although the data is not actually transferred, the time during which the CPU device 10 cannot operate and the DMA controller
For the CPU device 10, the time during which the processing related to 12 is performed is also an overhead time related to data transfer.

[0006] The meaningless time due to such data transfer increases as the amount of data to be transferred increases.

Even when the CPU device 10 and the data transfer bus are independent from each other as shown in FIG. 8, even if the CPU device 10 can perform processing even during data transfer, the CPU device 10 still operates. The dual port memory 13 must be managed. That is, the processing module i + 1 has data transmitted from the processing module i, but the processing module i + 1 must tell the processing module i from which address of the dual port memory 13 the data is to be written and what is the allowable reception amount. I have to. The processing module i sets the DMA controller 12 based on this information and transfers the data. Such processing is also an overhead time related to data transfer for each CPU device 10.

The present invention was devised in view of the above problems of the prior art, and by providing an apparatus capable of minimizing the overhead time related to the data transfer of the CPU apparatus as described above, The purpose is to improve the performance of the entire system.

[0009]

Therefore, the present invention relates to a random access pipeline register used for data transfer for parallel processing and a transfer device having the register, of which the configuration of the random access pipeline register is , A multi-stage pipeline register consisting of multiple registers, the input side of each stage register is connected to the output side of each previous stage register except the first stage, and each stage register has its input side The shift signal line for transmitting the shift signal for latching the data of is connected to each register,
A selection signal line for selecting each register is connected, and a data reading and data writing means is connected.

A second aspect of the present invention relates to a configuration of a data transfer device having the random access pipeline register, and in addition to the configuration of the register, the shift signal is generated by detecting an external data input or an external data transfer command. A data transfer control circuit is provided which has a shift signal generator for generating and transmitting it to the shift signal line, and also having a transmission means for transmitting the completion of the shift operation to the outside.

Further, the third invention proposes a structure of a data transfer control circuit provided with a random access pipeline register used as each processing module. As a concrete structure, a data transfer bus and a CPU bus are separately provided. A random access pipeline register in the data transfer bus, and a data transfer control circuit for controlling data transfer of the random access pipeline register in the data transfer bus. The register is composed of multiple stages of registers, and the registers of each stage are connected in series with the registers of the stages before and after that stage, and the shift signal is input from the data transfer control circuit to input and output data in each register. Is shifted,
A random access data bus for reading / writing data from / to the CPU bus is connected,
The register of a specific stage is selected by the input of the SEL signal by the command from the device and the register of the stage selected by the input of the WR signal by the command from the CPU device and the CP.
Data can be read and written between the U buses. On the other hand, in the data transfer control circuit, the shift signal is transferred to the random access pipeline register in response to detection of an external data input or a data transfer command from the CPU device. The basic feature is that the data transfer operation is sent to the CPU device, the completion of the data shift operation is transmitted to the CPU device, and the data transfer command is received from the CPU device.

The random access pipeline register as described above intervenes in data exchange between the processing modules under the control of the data transfer control circuit, and also exchanges data with the CPU bus side in each processing module. Will be done.

That is, in each processing module connected by the FIFO, as shown in FIG.
The PU bus is divided separately, and the random access pipeline register 1 is connected to the data transfer bus and the CPU bus, and is used for data transfer between the processing modules via the FIFO. In addition, in each processing module, a CP is sent via a random access data bus by various command signals issued from the CPU device 10.
Data is read and written between the U bus and RAP.

Data exchange between the processing modules by the random access pipeline register 1 will be described here.

First, the data from the processing module i is FI.
When input to the FO20, the data transfer control circuit 2 changes the signal line 2
This is detected by the signal of 1, and the SHFT signal is sent to the random access pipeline register 1 to input the data into the register 1. When the input is completed, the data transfer control circuit 2 outputs a signal to the signal line 23, and the CPU device 10
Notify that the shift operation has been completed.

Next, data exchange between the random access pipeline register 1, the CPU device 10 and the CPU bus in each processing module will be described.

As described above, when the data transfer control circuit 2 informs the CPU device 10 that the shift operation is completed, the CPU device 10 issues a command to cause the random access pipeline register 1 to issue a SEL signal. A register at an arbitrary stage is selected, and data is exchanged between the register and the CPU bus via the random access data bus. From that state, the CPU
The device 10 gives a command to the register to read the data between this register and the CPU bus or write the processed data by the WR signal. When the CPU device 10 finishes the data processing and the writing to the register, it outputs a data transfer command to the data transfer control circuit 2 via the signal line 23. In response to this instruction, the data transfer control circuit 2 inputs data to the random access pipeline register 1 and shifts data in the register 1, and at the same time, connects the signal line 22 to the FIFO 20 between the subsequent processing modules. A signal for transferring the data is transmitted via the data, and the data is transferred.

Among the processes of the CPU device 10 as described above, the process which becomes the overhead time is the data transfer control circuit 2
Side receives a signal indicating that the data shift operation has been completed, a transmission process for instructing the SEL signal and WR signal output when reading / writing data from / to the register, data processing / processing and register This is limited to the transmission processing of the data transfer command to the data transfer control circuit 2 when the writing of the data to is completed, and most of the time can be effectively utilized.

[0019]

EXAMPLES Specific examples of the constitution of the present invention will be described below.

Inside each processing module connected by the FIFO, there is provided the configuration of the embodiment of the parallel processing data transfer apparatus of the third invention, and the CPU is the same as that shown in FIG.
A bus and a data transfer bus are separately provided, and a 4-bit width input / output three-stage pipeline register (RAP) as shown in FIG. 3 is installed in this data transfer bus. Further, in each processing module, a data transfer control circuit for controlling RAP data transfer in the data transfer bus
Two are provided. A CPU device 10 and a local memory 11 are provided in the CPU bus.

The configuration of the module of each register in the RAP (unlike the processing module described above, the minimum configuration unit of a register including a D flip-flop that does not include a CPU device) will be described with reference to FIG.

First, S added to each module of m stages
The EL signal is output by this RAP based on a command issued from the CPU device 10 to the RAP, and selects the data input / output line. That is, when this SEL signal is "0", DI1 is selected as the input to the D flip-flop of the module, and the output of the D flip-flop is D
Only O1 becomes active, and DO2 becomes high impedance state. On the other hand, when the SEL signal is "1", the input DI2 to the D flip-flop is selected, and the output from the D flip-flop becomes active in both DO1 and DO2. When this SEL signal is "1", the input DI2 or output D of the D flip-flop of the group through which the signal of "1" flows
O2 can exchange data with the CPU bus side via the random access data buses D0 to D3. That is, based on the command output from the CPU device 10 to the RAP, when the WR signal input from the RAP to the CK2 of the module falls (when changing from "1" to "0"), the data to the D flip-flop is written. Will be able to latch. When the WR signal is "0" and the OE signal (output enable signal) is "1", the data in the D flip-flop is the random access data buses D0 to D0.
It is output (read) from D3. On the other hand, when the SEL signal is "0", the input is switched to the input from the input DI1, and when the shift signal is sent from the data transfer control circuit 2, the data is latched to the D flip-flop through the input DI1. The previous data latched by the D flip-flop is shifted to the next module through the output DO1.

Further, the configuration of the RAP of this embodiment is one in which a plurality of modules having the above-mentioned functions are used and each processing module is provided with three stages of 4 bit width, and its operation will be described with reference to FIG. To do.

Each module is provided with one register as described above, and registers of module (0,0), module (1,0), module (2,0), module (3,0). The column (4 bits configuration) is called the first stage pipeline register. Similarly, the module (0,
1), module (1,1), module (2,1),
The register sequence of the module (3, 1) is the pipeline register of the second stage, the module (0, 2), the module (1, 2), the module (2, 2), the module (3, 3).
The register sequence of 2) is called the pipeline register of the third stage.

On the other hand, the data transfer control circuit 2 mainly controls the RAP data transfer in the data transfer bus. That is, the FIFO 20 immediately before is transmitted via the signal line 21.
When it detects that data is input to the parallel data input interface I0, it sends a shift signal to the RAP.
Commanding the RAP to input the data from the I0 to the RAP, to sequentially shift the data latched in the RAP between the stages, and to output the data to the outside from the parallel data output interfaces O0 to O3. When a data transfer command is input from the CPU device 10, as will be described later,
Similarly, the data input from the parallel data input interfaces I0 to I3 to the RAP, the data output from the RAP to the parallel data output interfaces O0 to O3, and the data shift within the RAP are performed. Further, the data transfer control circuit 2 also notifies the CPU device 10 of the completion of the data shift including the input / output of the data in the RAP.

RA controlled by the data transfer control circuit 2
Data input to P, data shift inside the RAP, and data output from the RAP to the outside are performed in the following order. The data transmitted from the FIFO through the 4-bit parallel data input interfaces I0 to I3 when all SEL signals to be described later are “0” is output from the data transfer control circuit 2 and input to the CK1 of the module. The signal is input to the first stage pipeline register at the falling edge of the signal, and the contents of the pipeline register of the same stage are shifted to the second stage, those of the second stage to the third stage, and the pipeline register of the third stage. Is output to the next FIFO through the parallel data output interfaces O0 to O3.

When the data shift operation in the RAP is completed, the data transfer control circuit 2 informs the CPU device 10 of the completion of the shift operation as described above.

The CPU device 10 receiving this notification is the RAP
When it is desired to process any of the data latched in each stage of the RAP, a command is issued to the RAP and a SEL signal is output to any of the stages of the RAP. The SEL signal output based on this command is SEL
There are three, 1, SEL2, and SEL3, all are "0", or only one is "1". And SEL1, SEL
Reference numerals 2 and SEL3 correspond to the first-stage, second-stage, and third-stage pipeline registers, respectively, and select one of the three-stage pipeline registers to change the data input / output line. For example, when the signal of SEL2 is "1", DI2 is selected for all inputs of the second stage pipeline register, and DI1 and DI2 are active for all outputs.

On the other hand, the WR signal shown in the figure is a write pulse signal, and is the SEL1, SEL2 or SEL3.
If any of the signals is output based on the instruction from the CPU device 10 when it is "1", the data can be read / written into / from the pipeline register of the stage selected by the SEL signal. That is, when the WR signal is "1", the pipeline register of the selected stage is in the input (write) waiting state, and when this signal transits from "1" to "0", the data bus for random access is used. The data sent from D0 to D3 (this is the input / output terminal of the bidirectional bus transceiver) will be written into the pipeline register of the selected stage. On the other hand, when the WR signal is "0" and the OE signal is "1", the contents of the pipeline register of the selected stage are the data buses D0 to D0.
It will be output (read) to D3. Therefore, by using this WR signal, it becomes possible to perform bidirectional data exchange between the pipeline register of an arbitrary stage selected by the SEL signal and the CPU bus (however, the OE signal is " When 0 "and the WR signal are also" 0 ", D0 to D1 are in a high impedance state.

Next, the operation of the configuration of this embodiment described above will be described.

First, when data is not input / output between the RAP in the data transfer bus and the CPU bus, the SEL signal issued by the command from the CPU device 10 is SEL.
1, SEL2 and SEL3 are all "0" and FIFO
The data output from the parallel data input interfaces I0 to I3 to the first stage pipeline register together with the SHFT signal, the data of the first stage pipeline register to the second stage pipeline register, and the second stage pipeline register. The data in the pipeline register is output to the third stage pipeline register, and the data in the third pipeline register is output to the next FIFO through the parallel data output interfaces O0 to O3. Therefore, each processing module does not process any data, and the data is sequentially passed to the next processing module via the FIFO.

Then, as described above, of the data sequentially input into the RAP, the CPU device is operated for specific data.
On the 10 side, this is read, judged, processed and processed, and if necessary, data is written to RAP to change the contents.

Writing from the CPU device 10 to the RAP is performed as follows. CPU device 10 writes R to write
An address signal that specifies the AP stage, data to be written, and a "signal indicating writing" are output. The RAP decodes this address and sets the SEL signal of the designated stage to "1". Further, the RAP detects a "signal indicating writing" and sets the WR signal to "1". The data to be written appears on the random access data buses D0 to D3, and when the WR signal makes a transition from "1" to "0", the data is written to the module in the stage designated by the SEL signal. The CPU device 10 reads and writes data to and from the necessary stages in the RAP as necessary. This CPU device
When all the processes in the processing modules including 10 are completed, the CPU device 10 sends a data transfer command to the data transfer control circuit 2. The data transfer control circuit 2 is SH
The necessary number of FT signals are output, the data in the RAP is output from the parallel output interfaces O0 to O3, and the data is written in the FIFO 20 between the next processing module. It should be noted that the number of SHFT signals may be issued from the CPU device 10 by a required number of data transfer command signals, or a memory or the like may be installed in the data transfer control circuit 2.

In the configuration of the present embodiment described above, CP is applied to necessary data out of the data latched in the RAP.
U device 10 will be able to access randomly,
The processing load of the CPU device 10 at the time of data transfer between the RAP and the CPU bus is also reduced.
Since it is divided into two buses, the CP
It is possible to further improve the processing efficiency of the U device 10.

[0035]

According to the random access pipeline register and the data transfer device having the register of the present invention, the processing related to the data transfer in each processor in the multi-processing system is reduced, and the processing efficiency of the processor is improved accordingly. Will be able to.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a basic input / output system of a random access pipeline register.

FIG. 2 is a block diagram showing a basic configuration in each processing module including the random access pipeline register as described above.

FIG. 3 is a 4-bit width input / output 3 according to an embodiment of the present invention.
It is a block diagram which shows the structure of the apparatus of a stage pipeline register.

FIG. 4 is a circuit diagram showing a configuration of a module of each register.

FIG. 5 is a block diagram showing an example of a concept of a parallel processing system.

FIG. 6 is a block diagram showing a conventional example of a connection state between processing modules.

FIG. 7 is a block diagram showing another conventional example of a connection state between processing modules.

FIG. 8 is a block diagram showing another conventional example of a connection state between processing modules.

FIG. 9 is a flowchart showing a processing state of a CPU device in each processing module in these conventional examples.

[Explanation of symbols]

 1a, 1b RAP 2a, 2b Data transfer control circuit 10 CPU device 11 Local memory 12 DMA controller 13 Dual port memory 20, 21 FIFO

Claims (3)

[Claims] 1. In a multi-stage pipeline register composed of a plurality of registers, the input side of each stage register is connected to the output side of each preceding stage register except the first stage, and each stage register has its own output side. A shift signal line for transmitting a shift signal for latching the data on the input side of is connected to each register, a selection signal line for selecting each register is connected to each register, and data reading is performed. And a random access pipeline register, to which data writing means is connected. 2. A shift signal generator for generating the shift signal in response to a data input from the outside or a data transfer command from the outside and transmitting the shift signal to the shift signal line,
A data transfer device comprising: a data transfer control circuit having a transfer means for transmitting the completion of the shift operation to the outside; and the random access pipeline register according to claim 1. 3. A data transfer bus and a CPU bus are separately provided, a random access pipeline register is provided in the data transfer bus, and data transfer of the random access pipeline register in the data transfer bus is controlled. This random access pipeline register is equipped with a data transfer control circuit that
It is composed of a plurality of stages of registers, and the registers of each stage are connected in series to the registers of the preceding and following stages, and the data is shifted by the input / output of each register by the input of the shift signal from the data transfer control circuit. Along with the CPU
A random access data bus for reading and writing data from and to the bus is connected, and a register of a specific stage is selected by the input of the SEL signal according to a command from the CPU device and according to the command from the CPU device. WR
Data is read and written between the register of the stage selected by signal input and the CPU bus. On the other hand, the data transfer control circuit detects data input from the outside or transfers data from the CPU device. The shift signal is sent to the random access pipeline register by a command, the completion of the data shift operation is transmitted to the CPU device, and the data transfer command is received from the CPU device. Data transfer device.