JPH05102437A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To provide a nonvolatile memory which does not use an ion implantation device of highly accelerated energy for producing by reducing a chip size and by reducing a period from building of data to completion of a product. CONSTITUTION:A thin film transistor which becomes a memory cell is formed of gate electrodes (27 to 31) formed on a P-type silicon substrate 21 which is covered with a thick insulating film 22, a gate oxide film 41 formed to cover the gate electrode and a polycrystalline silicon layer 40 which becomes a source, a drain and a channel region formed on the gate oxide film 41. Here, a gate oxide film 41 and the polycrystalline silicon layer 40 of an arbitrary number of thin film transistors are successively formed respectively and building of data is carried out by controlling a threshold voltage by performing selective ion implantation for a channel region of the polycrystalline silicon layer 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory.

[0002]

2. Description of the Related Art In a conventional non-volatile memory, data is created by forming an impurity diffusion layer of a conductivity type opposite to the semiconductor substrate formed on a semiconductor substrate of one conductivity type as a source electrode,
This is done by controlling the threshold voltage of a MOS transistor used as a drain electrode by implanting impurity ions. Hereinafter, a conventional nonvolatile memory will be described with reference to the drawings.

FIG. 3 is a plan view of a conventional nonvolatile memory. FIG. 4 is a sectional view taken along the line AA '. 3 and 4
In the memory cell block, 1 is, for example, a P-type silicon substrate, 2 is a thick insulating film, 3 is an N-type diffusion layer, 4 is an N-type diffusion layer at ground potential, and 5 and 6 are gate electrodes of MOS type transistors. Block selection lines, 7, 8, 9, 10 and 11 are word lines which are gate electrodes of MOS type transistors, and the block selection lines 5 and 6 and word lines 7 to 11 are polycrystalline silicon wirings. . 12 is a gate oxide film of a MOS transistor, 13
Is an N-type impurity diffusion layer in which phosphorus or the like is diffused in order to control the threshold voltage of the MOS transistor. 1
4, 15 and 16 are bit lines made of metal wiring such as aluminum, 17 is an interlayer insulating film, 18 is the bit line 15 and the diffusion layer 3.
Is a contact hole for connecting the above, and 19 is a surface protective film. S _{1 to} S ₆ are block selection transistors, Q
_{1 to} Q ₁₅ are memory cell transistors.

The operation of the nonvolatile memory configured as described above will be described. Now transistor Q ₁
When reading the data created in, the block selection line 5 which is a non-selected block becomes low level and the block selection line 6 which is a selected block becomes high level. The word line 8 is low level, and the word lines 9, 10, 11
Is at a high level, and word lines in blocks other than the selected block are at a low level including the word line 7. The transistor Q ₁ is a depletion type because N-type impurities are diffused in the channel region, and the transistors Q ₂ , Q ₃ , Q ₄ and the selection transistor S ₁ in the same block are also turned on. The potential of the bit line 15 depends on the contact hole 18, the block selecting transistor S ₁ , and the memory cell transistors Q ₁ and Q.
It will be pulled close to the ground potential through ₂ , Q ₃ , and Q ₄ . The potential of the bit line 15 is detected and amplified by a sense amplifier (not shown) and output from an output terminal (not shown).

Next, when reading the data created in the transistor Q ₂ , the block select line of the non-selected block is at the low level and the block select line 6 of the selected block is at the high level, as in the previous case. It becomes a level. The word line 9 is at low level, the word lines 8, 10 and 11 are at high level, and the word lines in the non-selected blocks are at low level. Since the transistor Q ₂ is an enhancement type MOS transistor without diffusion of N type impurities in the channel region, the transistor Q ₂ is turned off,
The potential of the bit line 15 is not pulled to the ground potential, but remains raised to the power supply voltage. The potential of the bit line 15 is detected and amplified by a sense amplifier (not shown) and output from an output terminal (not shown).

As described above, data "1" and "0" are created depending on whether N type impurities are diffused in the channel region or not. The N-type impurity diffusion layer 13 in the channel region is selectively diffused by ion implantation before forming the gate oxide film 12, or the gate electrode (5 to 5) is diffused.
11) High energy after formation of the gate electrodes (7, 8, 1)
1) and the gate oxide film 12 are formed by ion implantation and diffusion so as to penetrate the gate oxide film 12.

[0007]

However, according to the above conventional structure, the impurity diffusion layers 13 in the channel regions of the adjacent memory cells under the same word line are not connected under the thick insulating film 2 for isolation. It is necessary to secure the separation width of the thick insulating film 2. This leads to an increase in chip size. Further, the implantation of impurities before the formation of the gate oxide film 12 takes a long time from data preparation to completion of the product, and the gate electrode (5-1
1) Implantation of impurities after formation requires an ion implantation apparatus with high acceleration energy.

In view of the above problems, the present invention reduces the chip size, shortens the period from data creation to product completion, and does not use a high acceleration energy ion implantation apparatus. An object is to provide a non-volatile memory.

[0009]

In the nonvolatile memory of the present invention, a memory cell is composed of a thin film transistor, and the thin film transistor covers a gate electrode formed on a semiconductor substrate covered with a thick insulating film and the gate electrode. A gate insulating film formed on the gate insulating film and a source / drain thin film to be a source, drain, and channel region formed on the gate insulating film. It is characterized in that data is created by continuously forming and selectively implanting a channel region of a thin film for source / drain of a thin film transistor to control a threshold voltage.

[0010]

According to the structure of the present invention, the source / drain thin film to be the source, drain, and channel regions is formed on the gate electrode and the gate insulating film, and the channel region of the source / drain thin film is selectively ionized. Data is created by injecting and controlling the threshold voltage. Therefore, it is not necessary to use an ion implanter with high acceleration energy for ion implantation into the channel region of the source / drain thin film for controlling the threshold voltage of the thin film transistor, and further, the number of memory cells per unit area can be reduced. The number of chips can be increased, the chip size can be reduced, and the period from data creation to product completion can be significantly shortened.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view of a nonvolatile memory according to an embodiment of the present invention, and FIG. 2 is a BB 'sectional view thereof. In FIGS. 1 and 2, 21 is a P-type silicon substrate,
Reference numeral 22 is a thick insulating film, 25 and 26 are gate electrodes of thin film transistors, block select lines for selecting a memory cell block, 27, 28, 29, 30 and 31 are word lines which are gate electrodes of thin film transistors, and block The selection lines 25 and 26 and the word lines 27 to 31 are polycrystalline silicon wirings. Reference numerals 34, 35 and 36 are bit lines made of metal wiring such as aluminum, 37 is an interlayer insulating film, and 39 is a surface protective film. 40 is the source of the thin film transistor,
A polycrystalline silicon layer (source / drain thin film) serving as drain and channel regions, and 41 are gate oxide films (gate insulating films) of thin film transistors. An impurity diffusion layer 42 is formed by diffusion in the channel region to control the threshold voltage of the thin film transistor. Here, it is assumed that an enhancement type thin film transistor is formed by using boron or the like to increase the threshold voltage. 43
Is a contact hole for connecting the bit line 35 and the polycrystalline silicon layer 40 which becomes the drain region of the thin film transistor. S _{21 to} S ₂₆ are block selection thin film transistors, and Q _{21 to} Q ₃₅ are memory cell thin film transistors.

Since the method of reading the data built in the memory cell of the nonvolatile memory configured as described above is the same as that described in the conventional example, the description thereof is omitted here. A method of creating "1" and "0" will be described. The data "1" and "0" are created by selectively implanting ions in the channel region of the thin film transistor. That is, after forming the polycrystalline silicon layer 40 to be the source, drain and channel regions of the thin film transistor, the gate electrode (25,
26, 29, 30) and ion implantation is performed from the surface opposite to the surface. Therefore, ion implantation with high acceleration energy is not required, and there is no concern about connection between adjacent memory cells on the same word line. Therefore, the separation width of the thin film transistor can be limited to the minimum dimension required at the time of etching or exposure, which helps to reduce the chip size. In addition, the period from data creation to product completion can be significantly shortened.

In this embodiment, the P type silicon substrate 2 is used.
1 is taken as an example, but in the case of an N-type silicon substrate,
It can also be applied to the case of a complementary MOS field effect transistor. Further, as the configuration of the memory cells, the continuous connection of one block and four memory cells and one block selection line is taken as an example, but this is also applicable in an arbitrary number. Furthermore, it goes without saying that the ions to be ion-implanted for controlling the threshold voltage, which is a data preparation, can be arsenic or phosphorus in addition to boron.

[0014]

The non-volatile memory according to the present invention includes a source,
Data is formed by forming a source / drain thin film to be the drain and channel regions on the gate electrode and the gate insulating film, and selectively ion-implanting the channel region of the source / drain thin film to control the threshold voltage. I try to make it. Therefore, it is not necessary to use an ion implanter with high acceleration energy for ion implantation into the channel region of the source / drain thin film for controlling the threshold voltage of the thin film transistor, and further, the number of memory cells per unit area can be reduced. The number of chips can be increased, the chip size can be reduced, and the period from data creation to product completion can be significantly shortened.

[Brief description of drawings]

FIG. 1 is a plan configuration diagram of a nonvolatile memory according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line BB ′ of FIG.

FIG. 3 is a plan configuration diagram of a conventional nonvolatile memory.

4 is a cross-sectional view taken along the line AA ′ of FIG.

[Explanation of symbols]

21 P-type silicon substrate 22 Thick insulating film 25, 26 Block selection line (gate electrode) 27 to 31 Word line (gate electrode) 40 Polycrystalline silicon layer (thin film for source / drain) 41 Gate oxide film (gate insulating film) 42 impurity diffusion layer (ion implanted channel region) S ₂₁ to S ₂₆ block selection thin film transistor Q ₂₁ to Q ₃₅ memory cell thin film transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 29/792 8225-4M H01L 29/78 371

Claims (1)

[Claims] 1. The memory cell comprises a thin film transistor, the thin film transistor comprising: a gate electrode formed on a semiconductor substrate covered with a thick insulating film; a gate insulating film formed to cover the gate electrode; A source / drain thin film for forming a source / drain and a channel region formed on the film, and a gate insulating film and a source / drain thin film of the thin film transistor of an arbitrary number are continuously formed respectively, and the source / drain of the thin film transistor is formed. A nonvolatile memory characterized in that data is created by selectively ion-implanting a channel region of a thin film for use in controlling a threshold voltage.