JPH05102407A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To prevent excessive gate capacitance and realize a high productive yield; by locating the sources and drains for one field effect transistor and for the other field effect transistor in the reverse direction to eliminate a crossed interconnection at a gate part in a differential circuit. CONSTITUTION:A differential complementary semiconductor device is made up of enhancement field effect transistors(EFET's) 2 and 4 and depletion field effect transistors(DFET's) 1 and 3. In the differential complementary semiconductor device, an inverter is made up of a set of circuits, in which one DEFT at the side near to a VDD power supply 11 is connected in series with one EFET at the side of grounding 12, and their mutual gate electrodes are connected in a crossed interconnection. In this case, the DEFET 3 and the EFET 4 are turned at an angel of 180 degrees in their location so that no crossing parts at the gate are needed and the stray capacitance caused by a crossed interconnection can be diminished to zero. moreover, since only one conductor is enough to connect the gates of the adjacent DFET and EFET, the yield can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing a differential complementary semiconductor integrated circuit formed by an enhancement type field effect transistor (abbreviated as EFET) and a depletion type field effect transistor (abbreviated as DFET).

[0002]

2. Description of the Related Art Conventional N-channel FET and P-channel FE
It is known that, in a complementary GaAs integrated circuit using T, the hole mobility of the P channel is smaller than the electron mobility of the N channel, so that sufficient high speed cannot be obtained. In recent years, in order to solve this drawback, a differential complementary circuit composed of an N-channel EFET and DFET has been proposed (1), and its high speed has been shown by simulation.

However, when forming an inverter using this circuit, the gate of one DFET of the differential circuit is connected to the gate of the other EFET, and the gate of one EFET is connected to the gate of the other DFET. The cross wiring of the "crossing" is necessary, but the gate part of the FET not only requires the finest processing technology, but also has a special structure related to the self-alignment technology. It is extremely difficult to form with a high yield, and there is a drawback that stray capacitance is increased due to an increase in wiring width at the crossing portion and high speed is lost.

(1) M. Passlack et al., Theoretical Ev
aluation of a Novel Design forDigital GaAs IC "S", I
EEE J. Solid-State Circuits, Vol.23, no.5, P, 1249,198
8. Also, in the ultra-high speed complementary GaAs integrated circuit, current spikes occur in the power supply line during switching operation, which causes frothtalk, but with the improvement in operating speed,
It has been clarified that the conventional method of loading an external capacitance on the power supply line cannot obtain a sufficient crosstalk removing effect.

[0005]

(1) One of the objects of the present invention is to provide a differential complementary integrated circuit composed of an EFET and a DFET, which has a gate part which causes an increase in delay time and a decrease in yield. It is an object of the present invention to provide a means for easily removing a cross wiring and obtaining a high-density ultra-high speed complementary integrated circuit.

(2) Another object of the present invention is to eliminate spike noise that occurs in the power supply line during switching operation and causes crosstalk in an ultra-high speed complementary integrated circuit, and to eliminate the spike noise in the integrated circuit chip. It is intended to provide a means for reducing the effective area occupied by the power supply line.

[0007]

[Means for Solving the Problems] (1) EFET, DFE
The means for removing the cross wiring of the gate portion in the differential complementary integrated circuit constituted by T is as follows.

The differential complementary inverter is a pair of circuits in which one DFET on the V _DD power supply side and one EFET on the ground side are connected in series, and the gate electrodes of the respective EFETs and DFETs are "thinned". It is formed by connecting. At this time, if one circuit is rotated 180 ° with respect to the other, the "pull-out" wiring that connects the gates of the EFET and DFET is converted into a shape that connects the adjacent EFET and DFET with a single common gate. The stray capacitance due to the "pull-out" wiring can be reduced to zero.

Further, at this time, since the V _DD power supply side and the ground side of the pair of differential circuits are reversed, a new intersection is generated between the power supply wiring and the ground wiring, but this portion is unrelated to the signal path. Therefore, even if a large capacitance is generated here, it does not hinder the circuit operation. (2) During the switching operation of the ultra high speed complementary integrated circuit,
The means for removing spike noise generated in the power supply line is as outlined below.

By rotating one of the pair of differential circuits by 180 ° with respect to the other as described above, the respective V _DD
Terminal and the ground terminal are arranged in close proximity, the complementary circuit, since DC current is very low 100μA or less is supplied from the feed line, so the voltage drop due to the ohmic resistance of the feed line negligibly small, V _DD a power supply line to the ground line widely formed in each metal thin film, by weight疊this by field insulating film, a feed line having a capacitance, a pair of V _DD terminals and ground terminals located than this close range If it is connected to, it is possible to obtain a power supply line having an excellent ability to suppress spike noise.

[0011]

(1) According to the method of the present invention in which one of a pair of differential circuits is rotated by 180 ° with respect to the other, a common circuit is used for one EFET and the other DFET of the differential circuits adjacent to each other. Since the gate may be formed as a single straight line, even for a FET having a self-aligned complex gate structure, the stray capacitance around the gate can be obtained at a yield equivalent to that of forming one FET. Small gate connections can be made. (2) According to the method of the present invention in which a thin film-shaped power supply line has a capacitance, it is possible to absorb a current spike generated in the power supply line during the switching operation of the ultra-high speed complementary circuit and suppress crosstalk noise. At the same time, especially in the GaAs complementary integrated circuit, since the feed line is in the form of a thin film, due to the high dielectric constant of GaAs, it is repelled on a semi-insulating GaAs substrate that is originally not suitable for signal wiring, By covering the entire surface of the chip with a thick SiO ₂ film for decoupling to reduce the effect of high dielectric constant, and then forming the signal wiring, the power supply that was conventionally provided in the uppermost layer due to the thickness of the power supply line The wiring area is unnecessary and the chip size can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings by taking a differential complementary integrated circuit using GaAs as an example. Figure 1 (a) shows DFET (1) and EFET
(2) is a circuit diagram of a differential complementary inverter using DFET (3) and EFET (4) (see reference (1)). FIG. 1B is a pattern diagram of the inverter manufactured by a combination of known techniques. (1) ~
The N-type channel layer of (4) is N on the semi-insulating GaAs substrate.
It is formed by implanting shape impurities in a dose amount corresponding to a predetermined threshold value. The fine gate wirings (7) and (8) that also serve as gate connections to the gate electrodes of the FET are formed by sputtering the heat-resistant metal WN and then shaping it into a width of 0.5 μm by reactive ion etching. In this way, a Schottky barrier having a barrier height of 0.8 eV is formed at the interface between the N-type channel layer and the WN. The source and drain electrodes of each FET are N ⁺ After the injection, AuGe / Au is manufactured by a known method of vapor deposition sintering. (5) and (6) in FIG. 1 are Ti / Pt / Au for differential input connected to the gate wirings (7) and (8).
Wirings (9) and (10) are differential output Ti / PT / Au wirings, (11) is a _VDD power supply line, and (12) is a ground line.

In the manufacturing process of FIG. 1B, the greatest yield factor is the intersection (1) of (7) and (8).
3). The WN gate requires a thickness of 0.5 μm in order to reduce the gate resistance, but under this condition it is extremely difficult to cross (7) and (8) across the insulating film, and wiring at the crossing Since the width is widened, the effective gate capacitance is increased, and it has been impossible to obtain the desired propagation delay time of 20 ps of the inverter. Another yield factor is that the lead-out of the output wiring (10) further crosses over (13) at (14), and this portion has a substantially three-layer structure of fine wiring.
Securing the yield becomes even more difficult. FIG. 2 is a pattern diagram showing one of the embodiments of the patent of the present invention devised in order to solve these problems in terms of yield and characteristics.
The major difference from Fig. 1 (b) is DFET (3) and EFET.
(4) is the point rotated by 180 °. 4 FETs
By arranging the gates as shown in FIG. 2, not only the gate intersection (13) becomes unnecessary, but also the adjacent DFET
(1) and EFET (4), EFET (2) and DFET
Since the gate connection of (3) can be formed by a single straight WN common gate, even if a complicated self-aligned structure is adopted, the yield is the same as that of manufacturing one FET. The gates of the FETs forming the differential circuit can be connected to each other.

On the other hand, in FIG. 2, the intersection of the gate wirings is not required, but the extension and the intersection of the feeder lines (11) and (12) as shown in (15) and (16) are required.
The heavy portions of (15) and (16) that bound the insulating film act as a large capacitance, but since the power supply line is not a signal path, it has no effect on the propagation delay time of the inverter. Since this capacitance is effective in removing the spike current generated in the power supply line during the switching operation of the inverter, it is better to form the power supply line in a wide thin film shape and to have a large capacitance in the critical part, because of crosstalk noise due to spike current. It was found to be advantageous in suppressing Further, the output wirings (9) and (10) must be able to overcome the power supply lines (15) and (16) at (17) and (18).
As described in (2) of (Operation), the power supply line has a thickness of 50
SiO ₂ for decoupling over 00 Å
Since it is covered with the film, the step (17), (18) over the step is gentle and does not cause a decrease in yield.

FIG. 3 is a pattern diagram showing another embodiment of the present patent. Here, V _DD power line (11) and ground line (1
2) is severed across the insulating film over the entire surface, and (1
1) Since power is supplied to each differential circuit that constitutes the inverter in the immediate vicinity of the large distributed capacitance formed between (12), the effect of suppressing the spike noise is large. See also FIG.
Compared with the above, the intersection of (17) and (18) is reduced, which contributes to the reduction of the stray capacitance of the wiring. With this configuration, the desired propagation delay time of 20 ps for the complementary inverter could be achieved. Also in this structure, the feeder lines (11), (12)
Since all are buried under the decoupling SiO ₂ film, the wide feed line does not have any influence on the wiring area of the signal line.

The method of the present patent can be applied to all logic gates of a differential complementary integrated circuit such as NAND and NOR as well as an inverter. Further, it is easily similar to that it can be applied to an E / D complementary integrated circuit using other semiconductor materials such as InGaAs and Si by making some modifications.

[0017]

According to the present invention, one of the field effect transistors of the differential circuit and the source 9 and the drain of the other field effect transistor are arranged in directions opposite to each other, and the cross wiring generated in the gate portion of the differential circuit is removed. can do.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a differential complementary inverter using an EFET and a DFET.

FIG. 2 is a pattern diagram of an inverter showing an embodiment of the present invention.

FIG. 3 is a pattern diagram of an inverter showing another embodiment of the present invention.

[Explanation of symbols]

1, 3 ... DFET 2, 4 ... EFET 5, 6 ... Input line 7, 8 ... Gate wiring 9, 10 ... Output line 11 ... V _DD power supply line 12 ... Ground line 13 ... Gate intersection 14 ... Crossing of output line 10 Part 15 ... Lead line of V _DD power line 11 16 ... Lead line of ground line 17, 18 ... Cross section of output lines 9 and 10 and V _DD power line 15

Claims (2)

[Claims] 1. A differential complementary semiconductor integrated circuit comprising an enhancement type field effect transistor and a depletion type field effect transistor, wherein one of the field effect transistor of the differential circuit and the other field effect transistor of the differential circuit are provided. By arranging the source and drain in opposite directions, the cross wiring that occurs in the gate part of the differential circuit is removed, the gate excess capacitance that causes the increase in propagation delay time is reduced, and a high manufacturing yield is obtained. Complementary semiconductor device. 2. A power supply line of a complementary semiconductor device, in the vicinity of source and drain electrodes arranged in directions opposite to each other,
The power supply line and the ground line are connected to each other through an insulating film to form a capacitance, thereby forming a capacitance, suppressing spike noise generated in the power supply line during switching operation, and reducing the wiring area required for the power supply line. Complementary semiconductor device.