JPH05102359A - Colling structure for memory module - Google Patents
Colling structure for memory moduleInfo
- Publication number
- JPH05102359A JPH05102359A JP3263548A JP26354891A JPH05102359A JP H05102359 A JPH05102359 A JP H05102359A JP 3263548 A JP3263548 A JP 3263548A JP 26354891 A JP26354891 A JP 26354891A JP H05102359 A JPH05102359 A JP H05102359A
- Authority
- JP
- Japan
- Prior art keywords
- memory module
- polyimide film
- wiring board
- printed wiring
- semiconductor storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はメモリモジュールに係
り、特に、動作時に発生する熱を除去する冷却構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module, and more particularly to a cooling structure for removing heat generated during operation.
【0002】[0002]
【従来の技術】メモリモジュールは、複数個の半導体記
憶素子を回路パターンを形成したプリント配線基板上に
近接して配列したもので、パーソナルコンピュータやワ
ークステーションの拡張記憶装置として用いられてい
る。このメモリモジュールの冷却法として半導体記憶素
子をフレキシブル基板に実装し二つ折りにして発泡ゴム
マットを囲む。それを金属ハウジング内に差し込み、半
導体記憶素子が発泡ゴムマットの弾性力で金属ハウジン
グに十分接し冷却する方法が、アイ・ビー・エムテクノ
ロジー ディスクロージャー ブリテン,27,(19
84)第2642頁(IBM Technology
Disclosure Bulletin,Vol.2
7,No.4B,(1984)pp.2642)に記載
されている。2. Description of the Related Art A memory module has a plurality of semiconductor memory elements arranged in close proximity on a printed wiring board having a circuit pattern formed thereon and is used as an extended memory device for personal computers and workstations. As a method of cooling this memory module, a semiconductor memory element is mounted on a flexible substrate and folded in two to surround a foam rubber mat. A method of inserting it into a metal housing and allowing the semiconductor memory element to sufficiently contact the metal housing with the elastic force of the foamed rubber mat to cool it is disclosed by IBM Technology Disclosure Bulletin, 27, (19).
84) p. 2642 (IBM Technology)
Disclosure Bulletin, Vol. Two
7, No. 4B, (1984) pp. 2642).
【0003】[0003]
【発明が解決しようとする課題】しかし、上記従来技術
は発熱量が大きくパッケージ高さの異なる半導体記憶素
子が複数個基板上に配列した時、発泡ゴムマットの弾性
力では金属ハウジング間とギャップを生じ十分な冷却が
行われず過熱により半導体記憶素子の誤動作を生じ安定
した動作が得られない点について触れられていない。However, in the above-mentioned prior art, when a plurality of semiconductor memory elements which generate a large amount of heat and have different package heights are arranged on a substrate, the elastic force of the foam rubber mat causes a gap between the metal housings. There is no mention that the semiconductor memory device malfunctions due to overheating without sufficient cooling and stable operation cannot be obtained.
【0004】本発明の目的は、発熱量が大きくパッケー
ジ高さの異なる半導体記憶素子を複数個基板上に実装し
た場合に、動作時に発生する熱を効果的に半導体記憶素
子から除去することで過熱による半導体記憶素子の誤動
作を防ぎ安定した動作を得るメモリモジュールの冷却構
造を提供することにある。An object of the present invention is to overheat by effectively removing heat generated during operation when a plurality of semiconductor memory elements which generate a large amount of heat and have different package heights are mounted on a substrate. It is an object of the present invention to provide a cooling structure for a memory module which prevents a malfunction of a semiconductor memory element due to the above and obtains stable operation.
【0005】[0005]
【課題を解決するための手段】上記目的は、ポリイミド
フィルムでメモリモジュールの周囲を密封し中に不活性
液体あるいはゲル状物質を充填することで達成される。The above object is achieved by sealing the periphery of a memory module with a polyimide film and filling an inert liquid or gel-like substance therein.
【0006】[0006]
【作用】不活性液体あるいはゲル状物質中にメモリモジ
ュールを浸漬することで、動作時にパッケージの高さの
異なる半導体記憶素子から発生する熱を除去し、半導体
記憶素子の過熱を防ぎ半導体記憶素子の安定した動作を
得ることができる。By immersing the memory module in an inert liquid or gel-like substance, heat generated from semiconductor memory elements having different package heights during operation is removed to prevent overheating of the semiconductor memory elements. A stable operation can be obtained.
【0007】[0007]
【実施例】図1、図2及び図3を用いて本発明における
第一の実施例を示す。図1において、メモリモジュール
は、半導体記憶素子パッケージ1、プリント配線基板
2、ポリイミドフィルム3、冷却剤4、外部入出力5、
シーリング部6などからなっている。プリント配線基板
2上には半導体記憶素子パッケージ1が実装されプリン
ト配線基板2に形成されている配線パターンで外部入出
力5に引き回されている。プリント配線基板2の上には
図2に示すように半導体記憶素子パッケージ1を覆うよ
うにポリイミドフィルム3が張られており、中に冷却剤
4が充填されシーリング部6で密封されている。冷却剤
4は不活性液体で、例えば、パーフロロカーボンなどが
用いられる。半導体記憶素子パッケージ1が動作すると
周囲の冷却剤4が熱を奪い、図3に示すように対流によ
ってポリイミドフィルム3へ伝熱する。熱はポリイミド
フィルム3を介して筐体や空気中へ放熱される。これに
より半導体記憶素子パッケージ1から発生する熱は効率
的に取り除かれ、動作時の温度を約80℃以下に抑える
ことができる。また、半導体記憶素子パッケージ1をテ
ープキャリアパッケージ化しガラスエポキシ製の枠を使
って縦方向に積み重ねた積層型メモリモジュール10の
場合でも同様の効果が得られる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, the memory module includes a semiconductor memory device package 1, a printed wiring board 2, a polyimide film 3, a coolant 4, external input / output 5,
It consists of a sealing part 6 and the like. The semiconductor memory device package 1 is mounted on the printed wiring board 2 and is routed to the external input / output 5 by the wiring pattern formed on the printed wiring board 2. As shown in FIG. 2, a polyimide film 3 is stretched on the printed wiring board 2 so as to cover the semiconductor memory device package 1, and a coolant 4 is filled therein and sealed by a sealing portion 6. The coolant 4 is an inert liquid, and for example, perfluorocarbon or the like is used. When the semiconductor memory device package 1 operates, the surrounding coolant 4 takes heat, and heat is transferred to the polyimide film 3 by convection as shown in FIG. The heat is radiated to the housing and the air through the polyimide film 3. As a result, the heat generated from the semiconductor memory device package 1 is efficiently removed, and the operating temperature can be suppressed to about 80 ° C. or lower. The same effect can be obtained also in the case of the stacked memory module 10 in which the semiconductor memory device package 1 is formed into a tape carrier package and stacked vertically using a frame made of glass epoxy.
【0008】次に図4を用いて本発明における第二の実
施例を示す。図4において、メモリモジュールは、積層
型メモリモジュール10、プリント配線基板2、ポリイ
ミドフィルム3、充填剤7、外部入出力5、シーリング
部6などからなっており筐体8中の主基板9上に筐体8
と密着して実装されている。プリント配線基板2上には
積層型メモリモジュール10がはんだ付けで実装されプ
リント配線基板2に形成されている配線パターンで外部
入出力5に引き回されている。プリント配線基板2の上
には積層型メモリモジュール10を覆うようにポリイミ
ドフィルム3が張られており、中に充填剤7が満たされ
シーリング部6で密封されている。充填剤7としては不
活性のゲル状物質で、例えば、シリカ系の軟質ゲルなど
が用いられる。積層型メモリモジュール10が動作する
と周囲の充填剤7が熱を奪い、熱伝達によってポリイミ
ドフィルム3へ伝熱する。熱はポリイミドフィルム3を
介して筐体や空気中へ放熱される。これに積層型メモリ
モジュール10よりから発生する熱は効率的に取り除か
れ、動作時の温度を約80℃以下に抑えることができ
る。また、筐体に機械的な外力が加わった場合、図5に
示すように、ポリイミドフィルム3中の充填剤7が適度
な弾性力を持ちながら筐体の空間を隙間なく埋めるよう
に倣う。これによりプリント配線基板2上の特定の積層
型メモリモジュール10のはんだ付け部分に集中荷重が
加わらないようにすることができる。Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 4, the memory module comprises a laminated memory module 10, a printed wiring board 2, a polyimide film 3, a filler 7, an external input / output 5, a sealing portion 6, etc., and is placed on a main board 9 in a housing 8. Case 8
It is mounted in close contact with. The laminated memory module 10 is mounted on the printed wiring board 2 by soldering and is routed to the external input / output 5 by the wiring pattern formed on the printed wiring board 2. A polyimide film 3 is stretched on the printed wiring board 2 so as to cover the laminated memory module 10. The polyimide film 3 is filled therein with a filler 7 and sealed by a sealing portion 6. The filler 7 is an inert gel-like substance, for example, a silica-based soft gel or the like is used. When the laminated memory module 10 operates, the surrounding filler 7 takes heat, and the heat is transferred to the polyimide film 3 by heat transfer. The heat is radiated to the housing and the air through the polyimide film 3. The heat generated from the stacked memory module 10 is efficiently removed, and the temperature during operation can be suppressed to about 80 ° C. or lower. Further, when a mechanical external force is applied to the housing, as shown in FIG. 5, the filler 7 in the polyimide film 3 has an appropriate elastic force and fills the space of the housing without any gap. As a result, it is possible to prevent concentrated load from being applied to the soldered portion of the specific stacked memory module 10 on the printed wiring board 2.
【0009】次に図6(a)〜(d)を用いて本発明に
おける第三の実施例を示す。図6(a)において、先
ず、メモリモジュールは、積層型メモリモジュール1
0、プリント配線基板2からなっており、プリント配線
基板2の全体をポリイミドフィルム3で覆うようにす
る。次に(b)においてプリント配線基板2上のシーリ
ング部6に紫外線硬化型接着剤11を一部を残して塗布
し硬化させる。更に(c)において注入器12の先端部
をシーリング部6の紫外線硬化型接着剤11の未塗布部
分から挿入し冷却剤4を中に送りこむ。最後(d)にお
いて注入器12の挿入部分に紫外線硬化型接着剤11を
塗布し硬化させて、全体のシーリングが完了する。これ
によりポリイミドフィルム状の中にほとんど気泡を残さ
ず冷却剤4を注入することができ、冷却構造全体の熱伝
達効率を損なうことがなくなる。また、接着剤の硬化に
は紫外線を用いるので、ほとんど熱を発生せず冷却剤4
の沸点を越えずにシーリングすることが可能となる。Next, a third embodiment of the present invention will be described with reference to FIGS. In FIG. 6A, first, the memory module is the stacked memory module 1
0, the printed wiring board 2, and the printed wiring board 2 is entirely covered with the polyimide film 3. Next, in (b), the ultraviolet curable adhesive 11 is applied to the sealing portion 6 on the printed wiring board 2 leaving a part thereof and cured. Further, in (c), the tip of the injector 12 is inserted from the portion of the sealing portion 6 where the ultraviolet curable adhesive 11 has not been applied, and the coolant 4 is fed therein. At the last (d), the ultraviolet curable adhesive 11 is applied to the insertion portion of the injector 12 and cured to complete the whole sealing. As a result, the coolant 4 can be injected into the polyimide film with almost no bubbles left, and the heat transfer efficiency of the entire cooling structure is not impaired. Also, since ultraviolet rays are used to cure the adhesive, almost no heat is generated and the cooling agent 4 is used.
It becomes possible to perform sealing without exceeding the boiling point of.
【0010】[0010]
【発明の効果】本発明によれば、半導体記憶素子パッケ
ージをプリント配線基板上に並べたメモリモジュールに
おいて、動作時に半導体記憶素子パッケージから発生す
る熱を効率的に除去することができるので、高密度に実
装されたメモリモジュールが使用可能となる。また、筐
体の加わる外力を適度に分散しエンボスや支柱の数を低
減できるので、筐体の薄肉化や軽量化が可能となる効果
がある。According to the present invention, in a memory module in which semiconductor memory device packages are arranged on a printed wiring board, heat generated from the semiconductor memory device packages during operation can be efficiently removed, so that high density is achieved. The memory module mounted in can be used. Further, since the external force applied to the housing can be dispersed appropriately to reduce the number of embossments and columns, there is an effect that the housing can be made thin and lightweight.
【図1】本発明の第一の実施例を示すメモリモジュール
の斜視図、FIG. 1 is a perspective view of a memory module showing a first embodiment of the present invention,
【図2】本発明の第一の実施例を示すメモリモジュール
の縦断面図、FIG. 2 is a vertical sectional view of a memory module showing a first embodiment of the present invention,
【図3】本発明の第一の実施例の伝熱の説明図、FIG. 3 is an explanatory diagram of heat transfer according to the first embodiment of the present invention,
【図4】本発明の第二の実施例を示す積層型メモリモジ
ュールの縦断面図、FIG. 4 is a vertical sectional view of a stacked memory module showing a second embodiment of the present invention,
【図5】本発明の第二の実施例の効果を説明するための
縦断面図、FIG. 5 is a vertical cross-sectional view for explaining the effect of the second embodiment of the present invention,
【図6】本発明の第三の実施例を示すメモリモジュール
の冷却構造の製造の工程図。FIG. 6 is a process diagram of manufacturing a cooling structure for a memory module according to the third embodiment of the present invention.
1…半導体記憶素子パッケージ、 2…プリント配線基板、 3…ポリイミドフィルム、 4…冷却剤、 6…シーリング部。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory element package, 2 ... Printed wiring board, 3 ... Polyimide film, 4 ... Coolant, 6 ... Sealing part.
フロントページの続き (72)発明者 石田 寿治 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 宮野 一郎 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内Front page continued (72) Inventor Toshiharu Ishida, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd.Production Technology Research Institute, Hitachi, Ltd. (72) Inventor Ichiro Miyano, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Production Technology Laboratory
Claims (4)
基板上に並べたメモリモジュールにおいて、ポリイミド
フィルムで周囲を密封し中に不活性液体を充填したこと
を特徴とするメモリモジュールの冷却構造。1. A cooling structure for a memory module, in which a semiconductor memory device package is arranged on a printed wiring board, the periphery of which is sealed with a polyimide film and an inert liquid is filled therein.
素子を収納するために凹部あるいは穴を設けた枠に前記
テープキャリア半導体素子を取り付け厚み方向に複数個
積み重ねた積層形半導体パッケージをプリント配線基板
上に並べたメモリモジュールの冷却構造。2. The printed wiring board according to claim 1, wherein the tape carrier semiconductor element is mounted on a frame provided with a recess or a hole for accommodating the tape carrier semiconductor element, and a plurality of stacked semiconductor packages are stacked in a thickness direction. Cooling structure for memory modules arranged in parallel.
ドフィルムの中にゲル状物質を充填したメモリモジュー
ルの冷却構造。3. The cooling structure for a memory module according to claim 1, wherein the sealed polyimide film is filled with a gel material.
ムでプリント配線基板の周囲を密封しシーリング部の大
半に紫外線硬化型の接着剤を塗布・硬化させた後、注入
器で不活性液体を充填し残りのシーリング部に紫外線硬
化型の接着剤を塗布・硬化させたメモリモジュールの冷
却構造の製造方法。4. The polyimide film according to claim 1, wherein the periphery of the printed wiring board is sealed with the polyimide film, an ultraviolet curable adhesive is applied and cured on most of the sealing portion, and then an inert liquid is filled with an injector. A method of manufacturing a cooling structure for a memory module in which an ultraviolet curing adhesive is applied and cured on the remaining sealing portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3263548A JPH05102359A (en) | 1991-10-11 | 1991-10-11 | Colling structure for memory module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3263548A JPH05102359A (en) | 1991-10-11 | 1991-10-11 | Colling structure for memory module |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05102359A true JPH05102359A (en) | 1993-04-23 |
Family
ID=17391075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3263548A Pending JPH05102359A (en) | 1991-10-11 | 1991-10-11 | Colling structure for memory module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05102359A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140019066A (en) * | 2012-07-19 | 2014-02-14 | 삼성전자주식회사 | Storage device |
US8787022B2 (en) | 2009-07-24 | 2014-07-22 | Kabushiki Kaisha Toshiba | Semiconductor storage device and method of manufacturing the same |
-
1991
- 1991-10-11 JP JP3263548A patent/JPH05102359A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8787022B2 (en) | 2009-07-24 | 2014-07-22 | Kabushiki Kaisha Toshiba | Semiconductor storage device and method of manufacturing the same |
KR20140019066A (en) * | 2012-07-19 | 2014-02-14 | 삼성전자주식회사 | Storage device |
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