JPH05101147A - Method for determining wiring order - Google Patents

Abstract

PURPOSE:To prevent the wiring length of a network from exceeding a wiring limit length without decreasing the wiring rate of a wiring process by determin ing the wiring order of pin pairs by the wiring order determining method for the layout design of an LSI, etc., in consideration of the degree of wiring conges tion and the wiring limit length. CONSTITUTION:Boxes 1-1-1-2 input logical connection information, arrangement information, and wiring limit lengths of respective networks. Boxes 1-3-1-5 find the permissible values of bypass wiring of respective pin pairs in consideration of the wiring limit lengths of the respective networks. Boxes 1-6-1-7 calculate expected values of wiring of the pin pairs by the shortest paths in consideration of the degree of wiring congestion in consideration of the degree of wiring congestion. Boxes 1-8-1-10 determine wiring order so that the pin pairs can be wired from pair pins which are smaller in the permissible value of bypass wiring and low in the expected value of shortest-path wiring.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a printed wiring board, L
The present invention relates to a method for determining the wiring order in wiring design such as SI.

[0002]

2. Description of the Related Art Conventionally, in this kind of wiring order determining method,
There are a wiring order determination method that prioritizes improving the wiring rate and a wiring order determination method that considers only the wiring limit length.

In the wiring order determination method which gives priority to improving the wiring rate, a method of deciding the wiring to give priority to a wiring having a short distance between the pin pairs and a pin pair traveling in an area having a high wiring congestion degree. There is a method of deciding to preferentially wire. As a related document, "Design of VLSI I" 1985, published by Iwanami Shoten Author Makoto Watanabe
There are 3 other 4 chapters layout design.

[0004]

In the above-described conventional wiring sequence determining method that prioritizes improvement of the wiring rate, the wiring rate can be expected to be improved, but depending on the wiring result, a net that violates the wiring length limit may be generated. It has the drawback of occurring.

Further, in the wiring order determination method considering only the wiring length limitation, no net violating the wiring length limitation is generated, but generally, the net which is likely to violate the wiring length limitation has a longer distance between the pin pairs. Since the wiring is prioritized over this wiring, the short pin pair between the pin pairs has a drawback that the wiring sequence is delayed and, as a result, the wiring rate is reduced.

[0006]

The wiring order determining method of the present invention inputs logical connection information and block layout information in determining the wiring order of a pin pair in wiring design of a printed wiring board, LSI, etc. A means for inputting and storing the wiring limit length of the net, calculating the virtual wiring length of the net after placement, and subtracting the virtual wiring length from the wiring limit length is used as the allowable value of the bypass wiring for each pin pair of the net. , A method of calculating and storing the allowable value of the bypass wiring of each pin pair, a means of obtaining an expected value that can be wired in the shortest route between two points of each pin pair based on the wiring congestion degree on the board, and a bypass wiring of each pin pair The allowable value of detour wiring is smaller than the allowable value of and the expected value that can be routed between two points, and the wiring order is determined so that wiring is performed from a pin pair with a lower expected value that can be routed between two points with a shorter expected value. Means and And wherein the Mukoto.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a flow chart showing a processing procedure in an embodiment of the present invention.

In the processing box 1-1, logical connection information necessary for designing a printed wiring board, LSI, etc. and layout information of each block are input and stored.

In the processing box 1-2, the wiring limit length for each net is input and stored. At this time, if the net has no wiring limit length, the wiring limit length is
It is stored as a half circumference that is the sum of the side lengths.

In the processing box 1-3, 1 is selected from all nets.
The net is taken out, the terminal position of the terminal to which the net is connected is obtained from the placement result of the blocks constituting the taken out net, the Steiner tree of the net is constructed, and the virtual wiring length of the net is calculated from the constructed Steiner tree. And ask.

In the processing box 1-4, next, the net is disassembled into each pin pair, and the value obtained by subtracting the virtual wiring length of each net from the wiring limit length of each net is the value of each pin pair in that net. It is stored as the total allowable value for the bypass wiring.

In the judgment box 1-5, the virtual wiring lengths of all nets are calculated, and it is judged whether or not the allowable values are calculated. If the allowable values are calculated for all the nets, the processing box 1 is selected. Go to -6, and if there is a net for which the allowable value has not been calculated yet, return to processing box 1-3.

In the processing box 1-6, one pin pair is extracted from all the pin pairs, and the pins of the extracted pin pairs and the wiring capacity and the wiring congestion degree within the minimum rectangle surrounding the pins are obtained,
A value obtained by dividing the wiring capacity by the wiring congestion degree is stored as an expected value that can be wired in the shortest route between two points of the pin pair.

In the judgment box 1-7, it is judged whether or not the expected value that can be wired on the shortest route between the two points has been calculated for all pin pairs, and if the calculation is completed, the processing box 1-8 is entered. If there is a pin pair for which calculation has not been completed yet, the processing box 1-6 is returned to.

In the processing box 1-8, the evaluation value V defined by taking into consideration the allowable value of the detour wiring of each pin pair and the expected value that can be wired in the shortest route between two points is defined by the following equation V = α · L + β · It is calculated and stored using D (L is a permissible value of detour wiring of a pin pair, D is an expected value for wiring between two points in the shortest route, and α and β are coefficients).

In the judgment box 1-9, it is judged whether or not the evaluation value in which the allowable value of the detour wiring of all pin pairs and the expected value for wiring between the two points are taken into consideration is calculated, and the calculation is ended. If there is a pin pair for which the evaluation value has not been calculated yet, the process returns to process box 1-10.

In the processing box 1-10, all the pin pairs are used with the evaluation value considering the detour wiring allowable value of the pin pair calculated in the processing box 1-8 and the expected value for wiring the shortest route between two points as the source key. Are sorted in ascending order of evaluation value, the sorted pin pair is arranged and stored as the wiring order of the pin pair, and the next wiring process is performed.

In the wiring process, the pin pairs are wired in the order of the pin pairs determined in the processing box 1-10.

FIG. 2 is an image diagram showing that the wiring route is different depending on the wiring order in the wiring of the net having three pins and the wiring length is severe, and the diagrams (A), (B), The same arrangement result is obtained in all three views of FIG. In the diagram (A), since the wiring order of the two pin pairs is slow, the wirings of both pin pairs are detour wirings, and the net wiring length exceeds the net wiring limit length. In the diagram (B), the wiring order of one pin pair is not a detour wiring because it is fast, but it is a detour wiring because the wiring order of another pin pair is slow, and the net wiring length is the wiring of the net. The limit length is exceeded. In the diagram (C), since the wiring order of both the two pin pairs is short, detour wiring does not occur, and the wiring length of the net and the wiring limit length do not exceed.

[0021]

As described above, the present invention inputs the logical connection information and the block layout information in determining the wiring order of the pin pair in the wiring design of the printed wiring board, the LSI, etc., and the wiring limit length of each net. The virtual wiring length of the net after placement is calculated, and the value obtained by subtracting the virtual wiring length from the wiring limit length is set as the allowable value of the bypass wiring of each pin pair of the net, and the value of the bypass wiring of each pin pair is stored. The allowable value is calculated and stored, and the expected value that can be wired between the two points of each pin pair by the shortest route is calculated from the wiring congestion degree on the board, and the allowable value of the bypass wiring of each pin pair and the distance between the two points are calculated. By determining the wiring order so that the allowable value of detour wiring is smaller than the expected value that can be routed on the shortest route and the expected value that can be routed on the shortest route between two points is low, the detouring is performed in the routing process. Distribution Of small tolerance, since preferentially wiring lower possibly be bypass wiring pin pair generates no net violates the wiring length limited by the wiring is bypassed. In addition, since the wiring congestion degree is taken into consideration by preferentially wiring the pin pair having a low expected value that can be wired between the two points with the shortest route, it is possible to prevent the wiring rate from decreasing.

[Brief description of drawings]

FIG. 1 is a flow chart showing a processing procedure of an embodiment of the present invention.

FIG. 2 is an image diagram showing that the wiring route is different depending on the wiring order of the pin pairs in the same placement result. The partial diagram (A) is an image diagram showing that the two pin pairs of the net are routed late, and thus the detour wiring is performed. The diagram (B) is an image diagram showing that one pin pair of the net is not routed by detouring because the pin order is fast, and the other pin pair is routed slowly, so the diagram (C) is Image diagram showing that the detour wiring was not performed because the wiring order of the two pin pairs of the net was quick

[Explanation of symbols]

 2-1 Pins that make up a net 2-2 Wiring route for a net that is made up of 3 pins 2-3 Pins for another net 2-4 Routed route for another net 2-5 Through hole (via)

Claims (1)

[Claims] 1. A method for determining a wiring order between two points of all pin pairs to be connected in a wiring design of a printed wiring board, an LSI or the like, in which logical connection information and block information necessary for circuit design are input, and The wiring limit length for the wiring pattern of each net is input, the virtual wiring length of each net is obtained from the placement result of the block, and the value obtained by subtracting the virtual wiring length from the wiring limitation length is obtained to obtain the net of that net. The allowable value for the detour wiring of each pin pair is determined, and the allowable value is calculated for all nets.Next, the value obtained by dividing the wiring capacity by the wiring congestion degree from the wiring capacity and the wiring congestion degree within the range surrounding each pin pair is calculated. , The expected value that can be routed between the two points of the pin pair by the shortest route, and the allowable value of the bypass wiring of each pin pair and the expected value that can be routed between the two points of each pin pair by the shortest route. A wiring order determining method characterized in that the wiring order is determined so that a pin pair having a smaller bypass wiring allowable value and a lower expected value that can be wired in a shortest route between two points is wired.