JPH05101128A - Circuit diagram editor - Google Patents

Abstract

PURPOSE:To display the connection state of respective symbols on a drawing at all times on the circuit diagram editor. CONSTITUTION:Whenever symbols are arranged and wired (process 40) on the circuit diagram editor, the connection state of all pins of the symbols which are arranged and wired is checked (process 41); and, when the symbols include no free pin (arrow 43), the symbols are emphasized and displayed, so that the connection state of the symbols is displayed on the drawing at all times. Consequently, the connection state of the symbols can easily and securely be checked on the circuit diagram editor.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a schematic editor,
Particularly, it relates to a means for checking the connection state of symbols.

[0002]

2. Description of the Related Art On a conventional schematic editor, on the schematic editor screen, after the placement of symbols and wiring work are completed,
Only when a command related to connection check is entered, check the connection status of all symbols on the screen, highlight symbols including empty pins, and output the name of the symbol including empty pins as a message. Displays the connection status of each symbol.

Such a conventional circuit diagram editor is shown in FIG.
It is difficult to read the connection state of each symbol from the drawing at the time when the symbols 2, 3, 4, and 5 arranged in 1 are wired (FIG. 5). In this state, by executing the command 50 regarding connection check,
For the first time, only the symbol 5 including the empty pin is highlighted, and the clear connection state of each symbol can be read from the screen (FIG. 6).

In the conventional circuit diagram editor, after arranging and wiring the symbols, the command relating to the connection check is executed to check the connection state. If there is a symbol including an empty pin, the circuit diagram Correction and recheck of connection status must be done. Also, after wiring is completed, I forget to check the connection status,
It is also possible to create a circuit diagram in which a symbol including an empty pin exists.

[0005]

The means for displaying the connection status of the symbols in the above-mentioned conventional circuit diagram editor has the connection status of each symbol until the command 50 relating to the connection check is executed after the wiring between the symbols is completed. There is a drawback that it is not clearly displayed.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a circuit diagram editor in which the connection state of each symbol is clearly displayed.

[0007]

The circuit diagram editor of the present invention has a structure in which every time a symbol is placed and wiring between the symbols is performed, all pins of the symbol subjected to the placement and wiring are placed. It is characterized in that it comprises means for checking the connection state and means for always clearly displaying the connection status of each symbol on the screen so that the connection status of the symbol can be checked at any time.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a method of checking the connection state of symbols in an embodiment of the present invention.

In FIG. 1, in the present embodiment, symbols are arranged and wired on the circuit diagram editor (Process 4).
Every 0th time, the connection state of all pins is checked (process 41) for the (placed and wired) symbol, and if all pins are connected (process 43), the There is a method of visually displaying that there is no empty pin by changing the display color of the symbol (process 44).

If the symbol includes an empty pin (process 42), the process proceeds to process 40. When the process 44 ends, the process returns to the process 40.

FIG. 2 is a plan view showing a state in which symbols are arranged in an embodiment of the present invention.

FIG. 3 is a plan view showing a state in which the symbols arranged in FIG. 2 are wired.

In this embodiment, as shown in FIG.
Symbols 2, 3 placed on the schematic editor screen 1
As shown in FIG. 3, the symbols 2, 3, 4 in which the connection of all the pins have been completed at the time when the wiring is done for 4, 5,
Since the display color of is changed and highlighted, it is possible to always read the clear connection state of each symbol from the screen.

2 and 3, the symbols 2 and 3 are
Is a buffer, an AND gate is a symbol 4, and a symbol 5 is an OR gate.

According to the present invention, in contrast to the above-described conventional method for checking the connection state of symbols in the circuit diagram editor, every time a symbol is placed and wired, all pins of the symbol to be placed and wired are placed. By checking the connection state of No. and if all the pins are connected, the symbol can be highlighted so that the clear connection state of each symbol can always be displayed on the drawing.

Next, another embodiment of the present invention will be described.

In the present embodiment, when checking the disconnection of the signal line on the circuit diagram editor, the connection check of the signal line is performed every time the signal line is wired, and the wired signal line is disconnected. If it does not include, the connection information of the signal line can be always displayed on the screen by performing highlighting at any time.

[0018]

As described above, in the present invention, after the symbols are arranged, if wiring is performed until all the symbols are highlighted, each symbol will not include an empty pin. There is an effect that the connection state can be checked simply and surely.

[Brief description of drawings]

FIG. 1 is a flowchart showing a method for checking a symbol connection state according to the present invention.

FIG. 2 is a plan view showing symbols arranged in one embodiment of the present invention.

FIG. 3 is a plan view showing a state in which the symbols arranged in FIG. 2 are wired.

FIG. 4 is a plan view showing a state in which symbols are arranged in a conventional editor.

FIG. 5 is a plan view showing a state in which the symbols arranged in FIG. 4 are wired.

6 is a plan view showing a state in which a command relating to a connection check is executed on the screen of FIG.

[Explanation of symbols]

 1 Circuit diagram editor screen 2,3,4,5 Symbol 50 Command execution 40,41,44 Process 42,43 Arrow

Claims (1)

[Claims] 1. A means for checking the connection state of all pins of the symbol subjected to the placement and the wiring each time the placement of the symbol and the wiring between the symbols are performed, and the connection of each symbol. A circuit diagram editor, characterized in that it is provided with means for constantly displaying the situation clearly on the screen so that the connection state of the symbols can be checked at any time.