JPH05100955A - Control system for cache memory - Google Patents

Abstract

PURPOSE:To efficiently shorten the processing waiting time for a processor with a smaller storage capacity. CONSTITUTION:A cache memory controller 4 is interposed among a processor 1, a main memory 2 and a cache memory 3, controls registration of an instruction or data in the main memory 2 to the cache memory 3, and when read-out is requested from the processor 1, in accordance with whether an instruction or data corresponding to the read-out request is registered in the cache memory 3 or not, it is read out of the cache memory 3 or the main memory 2 and returned to the processor 1. In such a cache memory control system, when the read-out request of the processor 1 corresponds to the part in which continuity of the instruction is lost on a program, only the instruction or the data corresponding to this read-out request is registered in the cache memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage system for a cache memory, and more particularly to a cache memory control system capable of efficiently exhibiting its function with a small storage capacity.

As a technique for improving the processing capacity of a processor, various systems have been proposed and implemented.
One of them is to use a cache memory.

The cache memory is a small-capacity high-speed storage device used for adjusting the difference in operating speed between the main storage device (main memory) and the processor, and the contents of the main memory that are frequently used for this purpose. A part of (instruction and data) is copied from the main memory, and the processor first accesses it to increase the apparent operation speed of the main memory as seen from the processor,
It has a function of shortening the processing waiting time of the processor and preventing the high-speed operation of the processor from being hindered.

A data storage system in such a cache memory is required to be capable of efficiently reducing the processing waiting time of the processor with a small storage capacity.

[0005]

2. Description of the Related Art FIG. 5 shows a conventional cache memory control system, in which 11 is a processor,
Reference numeral 12 is a main memory, and 13 is a cache memory.
A cache memory controller 14 is provided between the processor 11 and the main memory 12 and the cache memory 13 to control reading of instructions and data from the respective memories and storage of the contents of the main memory 12 in the cache memory 13. is there.

The operation of each unit in the configuration of FIG. 5 is performed as follows. The processor 11 outputs a command or data read request to the cache memory controller 14 via a control line, and outputs an address (main memory address) instruction of the command or data via an address bus.

Cache memory controller 14
Receives this and, for the cache memory 13,
A read memory control signal is output via the control line, and an address is output via the address bus. The address in this case has a certain correlation with the address for the main memory 12, and is subjected to a certain modification such as using a part of the address of the main memory.

If the requested instruction or data has been registered, the cache memory 13 outputs this so that the cache memory controller 14 checks the content. The check in this case is performed, for example, by checking the confirmation information (tag data) added to the instruction or data in the cache memory 13 and indicating that the instruction or data is registered corresponding to the address of the main memory 12. ..

When there is no requested copy of the main memory in the cache memory 13, the cache memory controller 14 outputs a read request to the main memory 12 via the control line, and outputs the read request to the main memory 12 via the address bus. , Output main memory address.

The main memory 12 returns the requested instruction or data to the cache memory controller 14.

Cache memory controller 14
Returns the received instruction or data to the processor 11 and, at the same time, outputs the write memory control signal via the control line, thereby writing the instruction or data in the cache memory 13.

As described above, as a conventional method of using the cache memory, a method of storing a copy of all the instructions and data read once by the processor in the cache memory is generally used.

[0013]

In the cache memory, when the processor accesses the cache memory and the desired instruction or data is in the cache memory and can be immediately read (hit), the processor However, if the desired instruction or data is not in the cache memory, the main memory must be accessed again, and an extra time is required before the desired instruction or data is read. I need time.

Therefore, it is necessary to reduce the number of miss hits in the cache memory, but in the conventional method, the mapping method of the cache memory and the main memory is devised in order to reduce the probability of the miss hit to the cache memory. By increasing the capacity of the cache memory or by increasing the capacity of the cache memory, it is possible to have as many copies of the main memory as possible in the cache memory.

On the other hand, as a processing method of a processor, a mode is generally used in which the processing shifts to the processing of the next instruction when the processing of one instruction is completed. In this case, if the data communication speed between the main memory and the processor is almost the same as the instruction processing speed in the processor, or faster than the instruction processing speed in the processor, the processor can perform satisfactory processing without the cache memory. You can gain the ability.

However, the conventional cache memory storage system stores a copy of all instructions and data once read by the processor, as described above, and thus can be said to be a wasteful method. ..

The processing capability of the processor decreases when there is no continuity between the processed instruction and the next instruction on the program (address addresses do not continue). That is, when an instruction called a jump instruction or a branch instruction is executed, it takes time to read the instruction at the jump destination or branch destination from the main memory and reach the processor, that is, communication between the main memory and the processor. Such a reduction in processing capacity occurs when the time becomes long.

Therefore, by using the cache memory only when the communication time between the main memory and the processor becomes long, the processing waiting time of the processor is shortened by using the cache memory with a small capacity.
Although it is possible to prevent the reduction of the instruction processing capability of the processor, conventionally, such a method of using the cache memory has not been proposed.

The present invention is intended to solve such a problem of the prior art, and uses a cache memory having a small capacity to prevent the communication time between the main memory and the processor from increasing, and It is an object of the present invention to provide a cache memory control method capable of reducing the processing waiting time.

[0020]

According to the present invention, a processor 1 is provided.
And controlling the registration of instructions or data in the main memory 2 in the cache memory 3 by interposing between the main memory 2 and the cache memory 3, and when there is a read request from the processor 1, this read request Depending on whether or not the instruction or data corresponding to is registered in the cache memory 3,
Alternatively, in the cache memory controller 4 which reads from the main memory 2 and returns it to the processor 1, when the read request of the processor 1 corresponds to a location where instruction continuity is lost on the program, Only the corresponding instruction or data is registered in the cache memory 3.

Further, according to the present invention, in such a cache memory control system, the value obtained by adding +1 to the address at the time of the previous read request is compared with the address at the time of the current read request, and when they do not match, the current read request is programmed. The read request discriminating means 5 for discriminating that the instruction corresponds to the portion where the continuity of the instruction is lost is provided.

Further, according to the present invention, in such a cache memory controller 4, the read request storage means for storing that the read request of the processor 1 corresponds to a portion where the continuity of instructions is lost on the program. When the instruction or data corresponding to such a read request is read from the main memory 2, it is registered in the cache memory 3 based on the storage of the read request storage means 5.

[0023]

FIG. 1 shows the principle of the present invention. The cache memory controller 4 is the processor 1
And is interposed between the main memory 2 and the cache memory 3, and controls registration of instructions or data in the main memory 2 in the cache memory 3 and
When there is a read request from the processor 1, if an instruction or data corresponding to this read request is registered in the cache memory 3, this is read from the cache memory 3 and is not registered in the cache memory 3. At this time, the function of reading this from the main memory 2 and returning it to the processor 1 is performed.

In such a cache memory controller 4, when the read request of the processor 1 corresponds to a location where the continuity of instructions is lost on the program, only the instruction or data corresponding to this read request is issued. Are registered in the cache memory 3.

As described above, according to the cache memory control method of the present invention, an instruction such as a jump instruction or a branch instruction, which has a great influence on reducing the processing capability of the processor, corresponds to a read request which disturbs the continuity of the instruction. Alternatively, since only the data is registered in the cache memory, it is possible to efficiently prevent the deterioration of the processing capability of the processor by using the cache memory having a small capacity.

Further, in such a cache memory control system, the read request discriminating means 5 is provided, and the value obtained by adding +1 to the address at the time of the previous read request and the address at the time of the current read request are compared and they do not match. At this time, by determining that the read request this time corresponds to the part where the continuity of the instruction is lost in the program, the normal read request and the instruction Even in the case of a processor that cannot output a read request that disturbs continuity separately, only an instruction or data corresponding to a read request that disturbs instruction continuity can be registered in the cache memory.

Further, in these cases, the cache memory controller 4 is provided with the read request storage means 5 so that the read request of the processor 1 corresponds to a portion where the continuity of instructions is lost on the program. When the instruction or data corresponding to such a read request is stored in the cache memory 3 based on the stored result, the cache memory 3 stores the instruction or data. In addition, only an instruction or data corresponding to a read request that disturbs the continuity of instructions can be registered.

[0028]

FIG. 2 shows the structure of an embodiment of the present invention, in which the same components as those in FIG. 5 are designated by the same reference numerals. 11A indicates a processor in the case of the present invention, 1
4A is a cache memory controller in the present invention. Reference numerals 15 and 16 are first and second control lines connecting the processor 11A and the cache memory controller 14A, respectively.

The operation of each unit in the configuration of FIG. 2 is performed as follows. The processor 11A outputs a command or data read request to the cache memory controller 14A via the control line, and outputs an address (main memory address) instruction of the command or data via the address bus. At this time, if the read request is a normal request, it is output via the control line 15, and if it is a read request generated by a jump instruction or a branch instruction, it is output via the control line 16.

Cache memory controller 14A
Receives this and, for the cache memory 13,
A read memory control signal is output via the control line, and an address is output via the address bus. At this time, if the read request is a read request input via the control line 16 and is generated by a jump instruction or a branch instruction, the fact is stored.

If the requested instruction or data has been registered, the cache memory 13 outputs it, so the cache memory controller 14 A checks the content.

When the requested copy of the main memory is not present in the cache memory 13, the cache memory controller 14 A outputs a read request to the main memory 12 via the control line, and then, via the address bus, Outputs the main memory address.

The main memory 12 returns the requested instruction or data to the cache memory controller 14A.

Cache memory controller 14A
Returns the received instruction or data to the processor 11A and, at the same time, when this instruction or data corresponds to the read request generated by the jump instruction or the branch instruction stored at the step of, the control line is set. This is registered in the cache memory 13 by outputting a memory control signal for writing via. Other instructions or data are not registered in the cache memory 13.

FIG. 3 shows a processor used in the embodiment of FIG. The processor 11A can separately output an instruction or data read request into a normal read request and a read request generated by a jump instruction or a branch instruction, and these requests are output as control lines 15 and 16, respectively. It is shown to be output via the.

FIG. 4 shows the configuration of another embodiment of the present invention, in which the same components as in FIG. 2 are designated by the same reference numerals. Reference numeral 11 denotes a processor similar to that of the conventional system shown in FIG. 5, and 17 is a read request classification circuit for classifying a read request into a normal read request and a read request corresponding to a jump instruction or a branch instruction. is there.

In the read request classification circuit 17, 21
Is a +1 circuit that adds +1 to the input data, and 22 is a holding circuit that temporarily holds the input data, and is composed of, for example, a flip-flop or a latch circuit. 23 is
A comparison circuit for comparing two inputs, and 24 is a selector for switching the input to two outputs.

When a read request is issued from the processor 11, the read request classification circuit 17 includes a +1 circuit 21.
Then, the value of the address output from the processor 11 is incremented by 1 and held in the holding circuit 22 until the next read request is generated. When the next read request is generated, the comparison circuit 22 compares the address held in the holding circuit 22 with the address output from the processor 11, and generates an output indicating a match or a mismatch. The selector 24 switches and outputs the read request from the processor 11 according to the output of the comparison circuit 22.

At the time of a match in the comparison circuit 23, the addresses are continuous and the continuity of the instructions on the program is not lost, so the output from the selector 24 is a normal read request and is sent via the control line 15. It is input to the cache memory controller 14A. When the comparison circuit 23 does not match, the addresses are discontinuous and the instruction continuity on the program is lost. Therefore, the selector 2
The output from 4 is a read request corresponding to a jump instruction or a branch instruction, and is input to the cache memory controller 14A via the control line 16.

Therefore, according to the embodiment shown in FIG. 4, the instruction or data read request of the processor 11 which cannot output the read request separately from the normal read request and the read request based on the jump instruction or the branch instruction. Even in such a case, the cache memory controller 14A operates in the same manner as in the embodiment of FIG. 2 and registers only the instruction or data corresponding to the read request that disturbs the continuity of instructions on the program in the cache memory 13. You can

[0041]

As described above, according to the present invention, a read request that disturbs the continuity of instructions in a program, such as a jump instruction or a branch instruction, which has a large effect on reducing the processing capability of a processor. Since only the corresponding instructions or data are registered in the cache memory, a processor capacity equivalent to that of the conventional cache memory that stores all instructions or data is used with a small capacity cache memory. Obtainable.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 shows a processor used in the embodiment of FIG.

FIG. 4 is a diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a diagram showing a conventional cache memory control method.

[Explanation of symbols]

 1 Processor 2 Main Memory 3 Cache Memory 4 Cache Memory Controller 5 Read Request Discriminating Means 6 Read Request Storage Means

Claims (3)

[Claims] 1. A processor (1) interposed between a main memory (2) and a cache memory (3),
The instruction or data in the main memory (2) is controlled to be registered in the cache memory (3), and when a read request is issued from the processor (1), the instruction or data cache memory corresponding to the read request ( In the cache memory controller (4) which reads out from the cache memory (3) or the main memory (2) and returns it to the processor (1) according to the presence / absence of registration in 3), a read request from the processor (1) is issued. The cache memory (3) stores only the instruction or data corresponding to the read request when the instruction corresponds to a portion where the continuity of the instruction is lost on the program.
A cache memory control method characterized by being registered in the cache memory. 2. The cache memory control method according to claim 1, wherein the address at the time of the previous read request is +1.
When the read request and the address at the time of this read request do not match, the read request at this time corresponds to the part where the continuity of instructions is lost in the program. A method for controlling a cache memory, characterized in that means (5) is provided. 3. A read request memory for storing, in the cache memory controller (4), a read request of the processor (1) when the read request corresponds to a location where instruction continuity is lost on a program. Means (6), characterized in that when an instruction or data corresponding to the read request is read from the main memory (2), it is registered in the cache memory (3) based on the storage. Item 3. A cache memory control method according to Item 1 or 2.