JPH05100648A - Test pattern generating device - Google Patents

Abstract

PURPOSE:To obtain a test pattern generating device where a test pattern and various messages concerning the test pattern are displayed on a display monitor to be tested. CONSTITUTION:A font pattern showing the number, the name and the testing method, etc., of horizontal and vertical frequencies, etc., is registered in a memory 2, and the font pattern is selected and read out in accordance with output from a test pattern signal source 1. After it is converted into serial data, it is switched to a test pattern signal by a switching circuit 7 and added to be displayed on the display monitor 10. Thus, the test pattern and the message are displayed on the same screen and working efficiency is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator for testing and adjusting a display monitor used in an office computer, a personal computer or the like.

[0002]

2. Description of the Related Art Conventionally, when testing and adjusting a display monitor using a CRT, liquid crystal or the like, various reference test patterns generated by a test pattern generator are displayed on a display screen of the display monitor. The operator who tests and adjusts this makes the test and adjustment while observing.

Since the display monitor has different scanning timings such as horizontal frequency and vertical frequency depending on the model,
In the conventional test pattern generator, various timings are registered in advance so that each test pattern can be selected and generated for each timing. In this case, for example, the registration numbers 1 and 2 are used by assigning a name to each timing such as A and B, respectively.

Further, when the timing is selected, its number, name, etc. are displayed on the display section of the test pattern generator. The operator looks at this display and the timing number of the test pattern currently output,
I try to know the name.

[0005]

Since the conventional test pattern generator is constructed as described above, when the operator wants to know the number, name, etc. of the timing of the test pattern currently output, the display Just by looking at the test pattern displayed on the monitor, it is not understood,
I had to look at the display of the test pattern generator. Therefore, there is a problem in that the worker has to take his eyes off the test pattern on the display monitor and that the test pattern generator needs to be arranged as close to the display monitor as possible.

In general, the display unit of the test pattern generator has a limited display capability, and although the timing numbers and names can be displayed, the operator is required to explain the test method and adjustment method for each test pattern. Since it is not possible to display a message, if the operator has any questions about the test method or adjustment method, he / she must stop the work and check the manual, etc. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a test pattern generator capable of displaying a message directly on a display monitor.

[0008]

A test pattern generator according to the present invention is provided with a font pattern indicating contents of various messages including timing numbers, names, etc., registered in a memory and placed from a test pattern signal source. The font pattern is selectively read from the memory according to the test pattern signal generated at the timing, and the read font pattern signal is switched to the test pattern signal and displayed on the display monitor.

[0009]

The test pattern generator according to the present invention is
Since various messages are displayed in characters on the screen of the display monitor together with the test pattern, the operator does not have to look at the display section of the test pattern generator and can always work while looking at the same screen.

[0010]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 is a test pattern signal source for outputting various test pattern signals according to timing, and 2 is a memory in which font patterns are stored. Timing numbers, test procedures related to memories and test patterns, adjustment procedures, and standards. Font patterns indicating the contents of various messages such as test methods and adjustment methods including the above are stored. Reference numeral 3 is a vertical address counter for controlling the vertical address of the memory 2, and 4 is a horizontal address counter for controlling the horizontal address of the memory 2.

A control unit 5 selects a test pattern signal to be output by the test pattern signal source 1 and its timing, and controls the vertical address counter 3 and the horizontal address counter 4 in accordance with the selection, thereby causing the memory 2 to operate. Select the font pattern to be read from. The operator selects the test pattern signal and its timing, and the selection unit such as a selection switch for that purpose is included in the control unit.

A P / S converter 6 converts an 8-bit parallel font pattern signal read from the output terminals D _{0 to} D ₇ of the memory 2 into a serial font pattern signal. It is supplied from the control unit 5. A switching circuit 7 switches between the test pattern signal output from the test pattern signal source 1 and the serial font pattern signal output from the P / S converter 6.

Reference numeral 8 denotes a display position designating circuit which determines the display position of the font pattern by controlling the switching of the switching circuit 7 under the control of the control unit 5. The vertical address counter 3
It includes a counter controlled by the output pulse of. 9 is controlled by the output pulse of the horizontal address counter 4, and P /
It is a counter that controls the S converter 6. Reference numeral 10 is a display monitor for testing and adjustment, to which the output signal of the switching circuit 7 is supplied. The control unit 5, the vertical address counter 3, and the horizontal address counter 4 constitute a control means.

FIG. 2 shows a screen 10a of the display monitor 10, where l ₁ , l ₂ , l ₃ ... Are horizontal scanning lines, arrows indicate scanning directions, and dotted lines indicate blanking periods.

FIG. 3 shows a storage state of dot data forming M, E, and S as an example of the font pattern stored in the memory 2.

FIG. 4 shows a state in which the MES is displayed on the screen 10a, and many black circles are dots as pixels.

FIG. 5 shows a memory 2 including a vertical address counter 3 and a horizontal address counter 4 for displaying MES.
The address control method of FIG. Lower three bits A ₀ of the address control terminal memory 2, A _1, the lower 3 bits of the output terminal a ₀ of the vertical address counter 3 to A _2, a
Output pulses of ₁ and a ₂ are applied, and 2-bit output pulses of output terminals b ₃ and b ₄ of the horizontal address counter 4 are applied to address control terminals A ₃ and A ₄ of the memory 2.

Next, the operation will be described. On the screen 10a of the display monitor 10, as shown in FIG. 2, dots are sequentially scanned from left to right by the scanning lines l ₁ , l ₂ , l ₃ ... Therefore, when designating the display position of a dot, it can be represented in the form of what number dot from the left of what number scanning line from the top.

As an example, a case where a message "MES" is displayed on the screen 10a as shown in FIG. 4 will be described. Each of the M, E, and S font patterns is composed of 8 × 8 dots, as shown in FIG. And "M" is stored in addresses 0 to 7 of the memory 2,
“E” is stored at addresses 8 to F, and “S” is stored at addresses 10 to 17. 8-bit dot data D _{0 to} D ₇ is stored in each address.

When this is displayed from the left end of the _first scanning line l ₁ as shown in FIG. 4, the first character of the font "M" is 1.
The 8 bits at address 0 in the column are read, and then "E"
The 8 bits of the 8th address, which is the first column of the font of, are read, and the 8 bits of the 10th address, which is the first column of the font of "S", are read. On the second scanning line l ₂ , the first address, the ninth address, and the eleventh address, which are the second column, are read out. After that, reading is performed in the same manner, and finally 7
When the address, the address F, and the address 17 are read, the display of FIG. 4 is performed.

In order to perform the reading as described above, FIG.
The read control shown in is performed. In FIG. 5, the output pulse a ₀ of the vertical address counter 3 is a pulse that changes every time one scanning line advances, a ₁ is a pulse that changes every two scanning lines, and a ₂ changes when every four scanning lines advance.

The output pulse b ₀ of the horizontal address counter 4 is a pulse which changes every time one dot advances on the scanning line, b ₁ changes every time two dots advance, and b ₂ advances four dots. Every time, b ₃ changes every 8 times, and b ₄ changes every 16 times.

Initially a ₀ = a ₁ = a ₂ = 0 and b ₃ = b
_{Since 4} = 0, the address by A _{0 to} A ₅ of the memory 2 is “0000”, and the address ₀ of the first column of “M” is 8
Bit data is read out and displayed with 8 dots from the left on the _first scanning line l ₁ . When the scanning line l ₁ becomes the 9th dot, b ₃ = 1 is set, so that the address of the memory 2 becomes “01000”, and the data at the address 8 which is the first column of “E” is read out and 9 Displayed by 16th dot.

Next, when the scan reaches the 17th dot, b
_{Since 4} = 1 and b ₃ = 0, the address is "10000".
Then, the data of the 10th address, which is the first column of "S", is read out and displayed by the 17th to 24th dots.

The second row of the second scanning line l ₂ has a ₀ = 1,
a ₁ = a ₂ = 0, and as the scanning line l ₂ moves to the right, b ₃ = b ₄ = 0 → b ₃ = 1 and b ₄ = 0 → b ₃
= 0, b ₄ = 1 so that the address of the memory 2 changes from “00001” → “01001” → “10001” to 1 → 9 → 11. Therefore, "M",
The second column of each font of "E" and "S" is output. After that, when the scanning line l ₈ is moved to the 8th column in the same manner,
The display "MES" will be displayed.

The 8-bit data read from the memory 2 is converted into serial data by the P / S converter 6 shown in FIG. 1 by the clock corresponding to the dot given from the control section 5, and then the switching circuit. At 7, the test pattern signal output from the test pattern signal source 1 is switched and applied to the display monitor 10.

Further, in the example of FIG. 4, eight scanning lines l _{1 to} l
₈ were carried out the display of the "MES" in the first line as one line, permitting the capacity of the memory 2, the second row (l ₉ ~l _16),
3 line (l ₁₇ ~l ₂₅₎ and can also be performed with messages displayed on the following lines.

The counter 9 of FIG. 1 supports the P / S converter 6 to fetch new data from the memory 2 when the clock corresponding to a dot advances by 8 and becomes the next font. To do. The display position designating circuit 8 includes a counter for displaying a message on a designated line of the display screen 10a. The counter, for example, when you want to insert a message in the third line of the display (the scanning line l ₁₇ to l _24), only that periods for the switching circuit 7 test pattern signals, P /
The signal from the S converter 6 is switched and output.

[0029]

As described above, according to the present invention, the font patterns for various messages can be output by switching them from the test pattern, so that the timing and the test pattern output by the test pattern signal source can be changed. The explanation of the operator can be displayed on the display screen of the display monitor under test, which makes it possible to easily transmit a lot of information to the test operator.
The working efficiency is improved, and it is not necessary to dispose the apparatus main body near the display monitor.

[Brief description of drawings]

FIG. 1 is a block diagram of a test pattern generator according to an embodiment of the present invention.

FIG. 2 is a front view of a screen of a display monitor.

FIG. 3 is a configuration diagram showing a data storage state of a memory.

FIG. 4 is a front view showing a state in which a font pattern is displayed on a display monitor.

FIG. 5 is a block diagram showing a memory address control method.

[Explanation of symbols]

 1 Test pattern signal source 2 Memory 3 Vertical address counter 4 Horizontal address counter 5 Control unit 7 Switching circuit

Claims (1)

[Claims] 1. A test pattern signal source for generating various test pattern signals in accordance with scanning timings such as horizontal frequency and vertical frequency of a display monitor, a number of the timing, a name, various messages relating to the test pattern signal, and the like. A memory in which a font pattern indicating the content is registered, a test pattern signal to be output from the test pattern signal source and its timing are selected, and a font pattern to be read from the memory is selected according to the selection and the reading is controlled. A test pattern generator comprising a control means and a switching circuit for switching between a test pattern signal output from the test pattern signal source and a font pattern signal read from the memory.