JPH0498435A - Shared memory controller for computer system - Google Patents

Abstract

PURPOSE:To improve access speed to a shared memory by varying the access time to the shared memory while changing the pulse width of the read/write signal to the shared memory. CONSTITUTION:In a signal control part 11b, a pulse width selection signal PULW and a clock signal CLK finely adjusting the pulse width are applied from the outside, and the clock signal CLK can be changed within the prescribed frequency range. According to the processing speed of a dual port RAM 17 connected to this shared memory controller 11 and respective processors 14a and 14b, the pulse width of a write signal DPWR and a read signal DPRD to the dual port RAM17 is set to the optimum value. The pulse width of the write/read signal indicating the access processing time to the dual port RAM17 is adjusted to the slower access processing time. Thus, the waiting time of respective processors is almost eliminated, and the processing speed of the entire computer system is remarkably raised.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a computer system in which one shared memory is shared by a plurality of processors, and in particular, the present invention relates to a computer system in which one shared memory is shared by a plurality of processors. The present invention relates to a shared memory control device for a computer system.

(Prior Art) For example, when information is processed by individual processors using related common data, a shared memory is provided and each processor accesses the shared memory as necessary.

When shared memory is accessed by multiple processors, a shared memory control device is used to relay access requests output from each processor to the shared memory and to adjust the access rights of each processor in the event of conflicting access requests. is required. Diagram N3 is a block diagram showing a computer system incorporating a shared memory control device.

1st. The second processors la, lb have address buses 2a, 2b and data bus 3a, respectively.

It is connected to the shared memory control device 4 via 3b.

In addition, the write signal (WR), read signal (RD), and lock signal (LOCK) output from each processor la and lb
) and the like are input to the shared memory control device M4,
The shared memory controller 4 sends the Lahiji signals (BSYL, BS
YR), interrupt signal (INTR) is sent to each processor la, l
Reply to b.

A dual port RAM 7 as a shared memory is connected to the shared memory control device 4 via an address bus 5 and data buses 6a and 6b. Dual port RAM output from the output terminal of the shared memory control device 4
Write signal (DPWR) and read signal (DPWR) for
RD) is input to the output enable terminal (OE) and write enable terminal (WE) of the dual port RAM 7, and is also input to each chip enable terminal (CE) of the dual port RAM 7 via each gate 8.9a, 9b.
I). Further, the bus high enable signal (BHEL) of the address bus 5 is applied to the gate 9a, and the address AO of the address bus 5 is applied to the gate 9b. Further, the remainder of the address bus 5 is input to the decoder 10.

An access request signal (ACCESS>7) outputted from the shared memory control device 4 is applied to the decoder 10.

In such a shared memory control device 4, when a write or read access request is input from each processor la, lb, an access request signal is output to the decoder 10, the dual port RAM 7 is controlled to be in an operating state, and the address and In the state in which data is output, a write signal (DPWR) or a read signal (DPRD) is output. Then, data is written to dual port RAM7 (dual port)
Data is read from RAM7. The access result to the dual port RAM 7 is the data bus 3a,
3b and address buses 2a and 2b to the processors la and lb that output the access request.

Note that if an access request is generated from the other processor before the access processing for the access request from one processor is completed, a busy signal is sent to the corresponding processor. Then, when the previous access processing is completed, the busy signal is canceled and converted into a ready signal.

By using a shared memory control device having such a control function, it becomes possible for a plurality of processors to share one shared memory.

However, even in the shared memory control device configured as shown in FIG. 3, the following problems still need to be improved.

In other words, in order to increase the processing speed of the entire computer system, it is natural to use dual port RA as shared memory.
It is desired to shorten the access processing time for M7. This access processing time is affected by ■ Improvements in the processing speed of each processor ■ Improvements in the processing speed of the shared memory control device ■ Improvements in the access response speed of the dual port RAM itself. The slowest of these determines the processing speed of the entire computer system. Therefore, the processing speed can be increased most efficiently by increasing each of the speeds (1) to (4) above to the same extent. Among the above-mentioned speeds (1) to (2), a processor with a relatively high processing speed has been developed and can be easily replaced. Also,
(2) is a dual-port RAM, and as shown in FIG. 3, processing speed can be relatively easily improved by using a combination of a plurality of general RAMs and peripheral circuits.

However, in order to reduce the size and weight of the entire device and reduce manufacturing costs, the shared memory control device (2) generally uses a single IC.
embedded within the circuit element.

This IC circuit element can be integrated into existing LSI or ASIC (
It consists of ICs for specific applications.

Therefore, the circuit specifications cannot be easily changed.

Therefore, there is a problem in that the processing speed of the entire computer system cannot be easily increased.

Further, the shared memory control device is configured to detect at regular intervals whether or not an access request to the shared memory is output from each processor. However, access requests are output from each processor completely asynchronously.

Therefore, if an access request is input immediately after checking the presence or absence of an access request, this access request will not be detected at all until the next cycle, even if no access processing is being executed to the shared memory at that time. The access request is made to wait for almost one period.

Therefore, the processing speed of the entire computer system is further reduced.

(Problem 311 to be Solved by the Invention) As described above, in the conventional shared memory control device, the specifications cannot be easily changed, so that the processing capabilities of the processor and the shared memory cannot be maximized.

The present invention was made in view of these circumstances, and
By making the pulse width of the read/write signal for the shared memory variable externally, the access processing time for the shared memory can be set in accordance with the access response speed of the processor and the shared memory itself, and the processor and the shared memory are It is an object of the present invention to provide a shared memory control device that provides a computer system that can maximize its processing power and significantly increase processing speed at low cost.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention is incorporated into a computer system in which one shared memory is connected to a plurality of processors via an address bus and a data bus. , shared memory control for a computer system that receives access requests for shared memory output from each processor, accesses the shared memory, and adjusts access rights to the shared memory when access requests output from each processor conflict. In the device, a pulse width variable setting means for variably setting the pulse width of read/write signals for the shared memory, and a pulse width variable setting means inserted between the shared memory and the data bus and the address bus, and a pulse width variable setting means for variably setting the pulse width of the read/write signal to the shared memory, and a There is a conflict between the data latch means, which temporarily latches the data, writes it into the shared memory, and returns a ready signal to the processor that sent the write data in response to the write data latching operation, and the access right adjustment process. and an asynchronous adjustment means executed at the generated timing.

(Function) In the shared memory control device of the computer system configured as described above, the access time to the shared memory can be varied by changing the pulse width of the successive write/write signal to the shared memory. Therefore, by setting this pulse width to the minimum time obtained from the response speed of the shared memory, the access speed to the shared memory can be improved. Similarly, the access time may be set in accordance with the processing speed of each processor.

In addition, when the write data output from each processor is latched by the data latch means, a ready signal is immediately output to the corresponding processor, so the processor that sent the write data can check the write data. The next processing task can be started before confirming that it has actually been written to the shared memory. In other words, the waiting time for a ready signal indicating completion of writing can be reduced.

Furthermore, since the access right adjustment process is executed at the timing when a conflict occurs, there is no need to wait for one cycle as in conventional devices.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a schematic configuration of a shared memory control device according to an embodiment. This shared memory control device 11 is roughly composed of a latch selector section 11a and a signal control section 11b. These are actually incorporated into one IC circuit element. This shared memory 11 includes address buses 12a, 12b, data bus 13a,
13b through the first. Second processor 14a, 14b
It is connected to the. It is also connected to a dual port RAM 17 as a shared memory via another address bus 15 and data bus 16.

1st. The 16-bit addresses input from the second processors 14a and 14b are respectively input to the address selector 18.
is input to. Also, 1st. second processor 14a,
The bus high enable signal (B
HE) is input to the access selector 18. and,
The address selector 18 selects the address output from either one and outputs the bus high enable signal (BHE).
) via the address bus 15 with the dual port RA
Send to M17.

Furthermore, in the latch selector section 1a, there are a pair of write latch circuits 19a and 19b corresponding to the first and second processors 14a and 14b, respectively, and a pair of read latch circuits 2.
0a, 20b, and a data selector 21 are provided. That is, the first and second processors 14a, 14b
Write data input from the data buses 13a and 13b is once latched by the write latch circuits 19a and 19b, and then sent to the data selector 21. The data selector 21 selects the data output from either one and transfers it to the dual port RAM 17 via the data bus 16.
Send to. Further, the data read from the dual-port RAM 17 via the data bus 16 is selected by the data selector 21, and is once latched in the successive latch circuits 20a and 20b of the selected processor. It is then transmitted to the selected processor 14a, 14b via the data bus 13a, 13b.

In this data writing process, each processor 14a,
The data input from 14b is sent to the write latch circuit 19a,
19b, the corresponding processor 1
A ready signal indicating completion of writing is sent to 4a and 14b. Therefore, each processor 14a, 14b determines that writing is completed at the timing when this ready signal is input, and
Move to a state where you can start the next processing task. That is,
Each processor 14a, 14b does not need to confirm that data has actually been written to the dual port RAMI 7.

Also, 1st. From the second processors 14a, 14b to the signal control unit 11b of the shared memory control device 11,
A device selection signal (D
PC5), a write signal (WR), a read signal (RD), and a lock signal (LOG) are input to dedicated terminals, respectively.

Further, from the signal control unit 11b, the first. The above-mentioned signal (BUS) is transmitted to the second processors 14a and 14b.
Send Y).

The shared memory control device 11 also sends a write signal (DP) to the dual port RAM 17 via the signal control unit 11b.
WR) and a read signal (D P RD).

Furthermore, a pulse width selection signal (PULW) and a clock signal (CLK) for finely adjusting the pulse width are applied to the signal control sections 11,b from the outside. In this signal control section 11b, there is a dual port RAM.
Write signal (DPWR) and read signal (DP
There are two types of pulse width W as the pulse width of RD).
w, W N and Rw, RN are recorded. The wide pulse widths Ww and Rw correspond to the dual port RAMI 7, which has a slow access response speed.
The narrow pulse widths WN and RN correspond to the dual port RAM 17 which has a fast access response speed. Then, whether the pulse width selection signal (PULW) input from the outside is H(1)
In the case of level, a wide pulse width Ww is selected.

Further, when the pulse width selection signal (PULW) is at L (0) level, a narrow pulse width WN is selected. In addition,
Each pulse width Ww, Ws-Rw, RN is determined by a clock signal (CLK) input from the outside, for example, 10 mm.
Fine adjustment is possible within the range of S.

The above-mentioned pulse widths Ww, WN, Rw, and RN are set as shown in Table 1, for example.

Table 1 Note that the clock signal (CLK) is transmitted to each processor 14a,
It is obtained by frequency-dividing the clock used in 14b to an optimal value using a frequency divider or the like. In this embodiment, the frequency can be divided and changed within the frequency dispersion range of 8 to 16 MHz.

That is, the dual-port RAMI 7 and each processor 14g connected to this shared memory control device 11,
Dual port RAM 17 depending on the processing speed of 14b
Write signal (DPWR) and read signal (DPR) for
D) The pulse width may be set to an optimal value.

In addition, each processor 14a, 14b and dual port R
If there is a difference in access processing time between the dual port RAM 17 and the RAM 17, the pulse width of the write/read signal indicating the access processing time for the dual port RAM 17 of the shared memory control device 11 can be adjusted to match the slower access processing time. ,
The reliability of access processing can be improved.

Next, the operation of the signal control section 11b when an access request to the dual port RAMI 7 is manually issued from each processor 14a, 14b will be explained using the time chart shown in FIG.

First, from the first processor 14a to the dual-port RAM
When writing data to address 17, write the address or address 12.
a Address selector 18. It is applied to the dual port RAM 17 via the address bus 15. Further, the write data is transmitted to the write latch circuit 19 via the data bus 13a.
Once latched in data selector 21.a. It is applied to the dual port RAM 17 via the data bus 16. Then, a device selection signal (CSI L) is inputted from the first processor 14a at time t, and a write signal (WRL) is inputted at time t2.

In response to the write signal (WRL) input, a write signal (DPWR) having a pulse width W is applied to the dual port RAM 17. Therefore, write data is written to the designated address within the duration (pulse width W) of the 20 write signal (DPWR).

Then, at the timing when the write signal (DPWR) ends, a busy signal (BSYL) is sent to the first processor 14a.
) is canceled. Further, when the write signal (WRL) of the first processor 14a is completed, this shared memory control device 11 is placed in a busy state.

That is, this shared memory control device 11 always maintains a busy state (normally wait) when no access request is input from the outside.

Next, when the second processor 14b reads data from the shared memory 17, the address is the address 12b, the address selector 18. It is applied to the dual port RAM 17 via the address bus 15. Then, at time t3, the second processor 14b sends a device selection signal (CSI
R) is input, and a read signal (RDR) is input at time t4. In response to the read signal (RDR) input, a read signal (DPRD) having a pulse width R is applied to the dual port RAMI 7. Therefore, data is read from the designated address within the duration (pulse width R) of this read signal (DPRD).

The read data is then input to the second processor 14b via the data selector 21, read latch circuit 2ob, and data bus 13b.

Also, a write signal (D
PWR) is completed, the second processor 14
The busy signal (B S YR) for b is released.

Furthermore, when the second processor 14b's successive signal (RDR) ends, the shared memory control device 11 is placed in a busy state (normally wait).

Further, at time t5, the write signal (WRR) is output from the second processor 14b, and at time t6, when the write process has not yet been completed, the read signal (WRR) is output from the first processor 14g.
RDL) enters, a race condition occurs. In this case, the write signal (DPWE) for the dual port RAM 17 is output at time t5, and the busy signal (BSYR) for the second processor 14b is released at time t7 when this write signal (DPWE) ends. At the same time, a read signal (DPRD) is output to the dual port RAM 17. Then, at time t8 when this read signal (DPRD) ends, the busy signal (BSYL) for the first processor 14a is released.

In this way, when an access request indicated by a write signal or a read signal to the dual port RAM 17 is input from each processor 14a, 14b, as shown in FIG.
Since write signals and read signals are sent to the computer system, there is almost no waiting time for each processor compared to conventional devices that check whether there is an access request from each processor at regular intervals. The overall processing speed can be significantly increased.

In addition, even if access requests from each processor conflict, the access processing for the later access request starts at the timing when the access processing being executed first ends, so the processor that outputs the access request later Waiting time can be reduced to a minimum.

[Effects of the Invention] As explained above, in the shared memory control device of the present invention, the pulse width of the write signal to the shared memory can be externally changed to an arbitrary value, so that the pulse width of the write signal to the shared memory can be changed to an arbitrary value. Access processing speed can be set. In addition, the data written to the shared memory is latched once and a ready signal is output to the relevant processor at the moment it is latched, so the processor does not have to wait until the writing process to the shared memory is completely completed. do not have. Furthermore, the access requests output from each processor are checked to see if there is any conflict with other processors at the timing of the output, adjustments are made at that point, and access processing for high-priority access requests is immediately executed. . Therefore, the processing efficiency of the entire computer system can be significantly improved.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the general configuration of the shared memory control device of the computer system of the embodiment, Fig. 2 is a time chart showing the operation of the same embodiment device, and Fig. 3 is a diagram showing the structure of the shared memory control device of the computer system of the embodiment. 1 is a block diagram showing the entire computer system. 11...Shared memory control device, 12a, 12b. 15...address bus, 13a, 13b, 16...
Data bus, 14a...first processor, 14b...
...Second processor, 17...Dual port RAM
. 19a, 19b=-write latch circuit, 20a. 20b...Read latch circuit.

Claims (1)

[Scope of Claims] A computer system that is incorporated in a computer system in which one shared memory is connected to a plurality of processors via an address bus and a data bus, and receives an access request for the shared memory output from each of the processors, A shared memory control device for a computer system that accesses the shared memory and adjusts access rights to the shared memory when access requests output from the respective processors conflict, comprising: pulses of read/write signals to the shared memory; pulse width variable setting means for variably setting the width; interposed between the shared memory and the data bus and the address bus;
A data latch that temporarily latches the write data output from each processor and then writes it into the shared memory, and in response to the latching operation of the write data, returns a ready signal to the processor that sent the write data. means and
A shared memory control device for a computer system, comprising: an asynchronous adjustment unit that executes the access right adjustment processing at a timing when a conflict occurs.