JPH0498308A - Clock timing controller - Google Patents

Abstract

PURPOSE:To realize an operation in a low frequency and the reduction of power consumption by providing a clock timing controller which can generate a period which is almost the same as the data holding period of a high speed operation with the low frequency operation. CONSTITUTION:This controller has a clock timing controller A corresponding at regular operation time which corresponds to the high speed operation and a clock timing controller B for low frequency operation which corresponds to the low frequency operation and it has a switch which changes over the two controllers A and B by the high speed operation and the low frequency operation. The clock timing controller B corresponding to the low frequency operation can realize the holding period, namely, the period when an output C is '0' in the same way as the period when the high speed operation is '0' in the state of the low frequency. Then, the change-over switch selects the controller B and the clock timing is controlled by the controller B. Thus, the occurrence of an accident that the holding of data is lacked is prevented and power consumption can be reduced.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a device for controlling the clock timing of a dynamic circuit, and in particular to a clock timing control device that allows operation even at a low frequency. Regarding.

[Conventional technology]

Normally, a dynamic circuit is constructed as shown in FIG. 4, and takes in data and holds data at the timing of one clock cycle. Conventionally, a single device for controlling clock timing has realized the operation of the above-mentioned Guinamine clutch circuit using the clock outputted by this device.

Next, this operation will be explained according to FIG. First, when the clock signal C output from the clock timing control device 20 is "1'', the transfer e takes in ONL and data D, the node 01 becomes D, and D is output to the node 02. Next, the clock signal C changes from “1” to “0”
', transfer C, which had been on until now, turns off, and both points 01 retain the value of D that was taken in earlier.
D is output to node 02. When the zero-order black/litter signal C changes from "0'" to °°1, node 01 takes in new data Dg: D is output to node 502. Here, the oscillator pressure X is input to the clock timing control device 20 (:).

The operation of the above-mentioned dynamic circuit performs a sampling operation using the storage capacitance inherent in the MOS device. The clock frequency must be appropriately high in order to perform the next sampling operation before the stored information in the capacitance leaks and is lost as a current.

In addition, P channel MO5) - transistor and N channel MO
The common connection point of the series body with the S transistor is designated as node 02, and the common gate is designated as node 01.

[Problem to be solved by the invention]

When performing the above-described circuit operation in a microcomputer at a low frequency, the clock timing signal C output from the clock control device 20 to which the oscillator output X is input is the fifth clock timing signal C.
As shown in the figure, compared to normal operation, 1”, °゛0
” period becomes longer than 6.

As a result, in the operation of the dynamic circuit, the state in which the transfer e is OFF, that is, the data retention period becomes longer, and data retention loss occurs.

In addition, the gate of the next stage inverter becomes an intermediate potential, and P
Both the ch) transistor and the Nch) transistor are turned on, current flows through them, and the characteristic of low power consumption, which is an advantage of conventional low frequency operation, is lost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock timing control device which solves the above-mentioned problems and allows data retention/extraction without any risk of accidents and with low power consumption.

[Means to solve the problem]

The configuration of the clock timing control device of the present invention is characterized in that the means for selectively outputting either a clock signal corresponding to high-speed operation or a clock signal corresponding to low-frequency operation is biased.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a 20-track timing control device according to an embodiment of the present invention.

In FIG. 1, the clock timing control device of this embodiment consists of two devices: a device A that supports high-speed operation (normal operation) and a device B that supports low-frequency operation.
The clock timing signal outputted from the circuit is as shown in FIG.

However, the waveform of device A is in a high speed state, and the waveform of device B is for operation at a low frequency.

The clock timing control device of this embodiment has two devices: device A that supports high-speed operation and device B that supports low-frequency operation.
It also has a switch for switching these two devices between high-speed operation and low-frequency operation. Here, the clock timing control device A that supports high-speed operation is the sixth
The clock timing device A shown in the figure outputs an output C, and is the same as the conventional one. In addition, the clock timing control device for low frequency operation is one that outputs the sixth (2I) clock timing control device B output C, and in the low frequency state, the holding period, that is, the output C is “0”. It is possible to realize the period "0" which is almost the same as the "0" period of high-speed operation.

These devices A and B are configured such that one of the devices is selected by a changeover switch depending on the operating state. For example, switching is performed by an external signal.

Next, the operation will be explained.

First, in the case of high-speed operation, the clock timing control device 20
Device A is selected by a changeover switch, and the timing of the clock 7 is controlled by device A, and the operation of the dynamic circuit is realized by this timing.

Next, when operating at a low frequency, device B is selected by the changeover switch, and the clock timing is controlled by device B.

Here, the device B has a configuration as shown in FIG. 2 in Example 7, and passes the output X output from the oscillator, the output signal C of the output ,
Furthermore, it is possible to obtain the signal C- shown in FIG. 3 from the timing of two signals, the output X and the clock signal C, which are extracted from the clock signal C-3 via the inverter gt6.

In this case, the period during which the clock is "0" in the dynamic circuit, that is, the period during which data is held, is shortened, it is possible to prevent retention loss, and it is possible to realize circuit operation equivalent to that during high-speed operation.

That is, device B can make the holding period almost the same as that during high-speed operation by changing the duty ratio without changing the frequency of device A. Therefore,
The fall detection circuit shown in FIG. 7 may be used for the device WB, and a signal C" as shown in FIG. 8 can be obtained. Here,
The circuit of FIG. 7 includes an inverter 30. NAND gate 31
．． Inverters 32-35. It includes a delay circuit consisting of capacitors 36 to 38.

Next, when operating at a low frequency, device B is selected by the changeover switch, and the clock timing is controlled by device B. In this case, in a dynamic circuit, the period when the clock is "0", that is, the period during which data is held, is almost the same as that in high-speed operation, so it is possible to realize the same dynamic circuit operation as in high-speed operation. be.

〔Effect of the invention〕

As described above, the present invention has a lock timing control device that can generate a period that is almost the same as a data retention period in a high-speed operation at a low frequency operation. This has the effect of making it possible to operate at higher frequencies and also realizing lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a dynamic circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a device compatible with low frequency operation of the clock timing control device shown in FIG. 1, and FIG. 2 is a timing diagram of FIG. 4, 21 is a block diagram showing the conventional dynamic circuit ii'3e, FIG. 5 is a clock timing diagram of FIG. 4, 6 is a timing diagram of FIG. 8121 is a block diagram showing the other side of the apparatus in FIG. 1, and 8121 is a timing diagram in FIG. 7. A... Clock timing control device for normal operation,
B... Lock timing control device compatible with low frequency operation, C... Clocks timing control device output signal,
C'... - clock output signal of device B, D... input signal, 01... output signal of transfer, 02... output signal of inverter, X... output signal of oscillator, a, e
Transfer, g, 30.32-35...-inverter, 36-38...capacitor, d...2-man power NOR gate.

Claims (1)

[Claims] A clock timing control device comprising means for selectively outputting either a clock signal corresponding to high-speed operation or a clock signal corresponding to low-frequency operation.