JPH0496843A - Cache memory control system - Google Patents

Abstract

PURPOSE:To optimize setting of a set address field by providing a set address field varying means and dynamically managing the set address field for the tag part of a cache memory. CONSTITUTION:A set address field optimizing and cache control part 27 switches a set address field SAF for a tag part TG of a cache memory 10 in time division based on a cache hit rate indicating signal RTO detected by a comparator 25 and compares the frequency in access request based on an access request signal AREQ from a storage control part 29 with the frequency in hit based on a detected hit/miss indicating signal H/M to detect the cache hit rate and resets the set address of the tag part TG to the access address field where the highest hit rate is detected finally. Thus, the set address for the tag part of the cache memory is optimally set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a data processor having a built-in cache memory for instructions or data, and particularly relates to a technique for dynamically managing a set address field for a tag section of the cache memory. In order to optimize the settings of the cache memory, increase the cache hit rate, and speed up instruction execution processing, the cache memory has a data section and a tag section that store access data and the physical address of the data, respectively. It has a valid bit indicating whether or not a pair of address and data is valid and has a function of managing the copying of data on the main memory, and an access address field serving as the set address of the tag part is transferred to an internal address bus. The apparatus is configured to include a set address field variable means for moving all the address fields above.

[Industrial application field]

The present invention relates to a data processor having a built-in cache memory for instructions or data, and more particularly to a technique for dynamically managing a set address field for a tag section of the cache memory. The data processor with built-in cache memory of the present invention can be applied to data processing systems such as VLSI microprocessors and supercomputers that perform large-scale data processing.

[Prior art and problems to be solved by the invention]

The set associative method is most commonly used as a cache data management method to date, and the set address field for the tag portion of the cache memory is completely fixed.

Therefore, although the data hint rate for a specific area of physical space is very high, the cache hit rate is considered to drop significantly when a program is executed that has an arrangement of instructions or data whose cent address fields are the same.

Furthermore, it is considered to be extremely disadvantageous in a huge program execution environment that requires expansion of physical space and enormous processing time.

Therefore, if this cent address field can be managed dynamically, it is possible to prevent the cache hit rate from decreasing even when executing a program that has an instruction or data arrangement where the cent address field is the same. It is assumed that

The present invention was created in view of the problems in the prior art, and provides a cache memory control method that can optimize the settings of the set address field, increase the cache hit rate, and speed up instruction execution processing. is intended to provide.

[Means to solve the problem]

In order to solve the above problems, according to the present invention, in a data processor having a built-in cache memory for instructions or data, the cache memory has a data section and a tag section that respectively store access data and the physical address of the data. It has a hard bit indicating whether the address and data pair is valid and has a function of managing the copying of data on the main memory, and an access address field which is the set address of the tag part is connected to the internal address bus. A cache memory control method is provided, which is characterized by comprising a seven-node address field variable means for moving all of the above address fields, thereby dynamically managing a set address field for a tag section of a cache memory.

C Effect] According to the above-described configuration, the set address field for the tag section of the cache memory is dynamically managed, so it is possible to optimally set the set address field. Therefore, even when executing a program having an instruction or data arrangement such that the cent address fields are the same, the cache memory can be controlled without reducing the hint rate. This contributes to speeding up the instruction execution process by the data processor.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

[Embodiment] FIG. 1 shows a partial schematic diagram of the configuration of a data processor with a built-in cache memory as an embodiment of the present invention. In the figure, 10 indicates a cache memory, and two data entry areas -AYO, WAYI (64 each
entry), each of which includes a data section DP for storing access data, a tag section TG for registering (storing) the physical address of the data, and whether or not the pair of address and data is valid. It consists of a valid bit VB indicating whether the

11 is an internal address bus, 12 is an internal address bus 11
The access address (physical address) is an image representation of all the address fields above. Note that SAF indicates a set address field for the tag section TG of the cache memory 10, and PAL and PA2 indicate physical addresses other than the set address field.

13 is a decoder (DEC) that decodes the physical address of the set address field SAF; 14 is a linker that connects the physical addresses FAI and PA2 other than the set address field as needed and registers them in the tag section TG; 15 and 16 are respectively The registration address of the tag part TG in YO, WAYI to the entry multi-page area and the output address of the coupler 14 (
i.e. physical address other than the set address field)
Comparators (CMP) 17 and 18 compare the outputs of comparators 15 and 16, respectively, and AND gates 19 respond to the parindo bit VB in the corresponding entry area YO, 1IIAYI, and 19 is an AND gate 17.
．． OR gate 20.21 outputs a hit/miss indication signal H/M in response to the output of AND gate 1B;
A tri-state buffer for transmitting data from the data section DP of Y1 to AYO and W to the internal data bus 22 is shown.

Further, 23 indicates a hit counter that counts the number of hits to the internal cache based on the hint/miss instruction signal H/M, and 24 indicates an access request counter that counts the number of access requests based on the access request signal AREQ. The counter 24 outputs the current count value, and also outputs a signal MXC indicating this when the maximum count value MAX is reached.

Note that both counters 23 and 24 receive a clear signal CLR.
It is reset to O by . Furthermore, 25 is a comparator (CMP) that compares the count value of the hit count counter 23 and the count value of the access request count counter 24 and outputs the cash hit rate instruction signal RTO; 26 is the cache hit rate instruction information outputted from the comparator 25; This shows a management register (REG) that temporarily stores the .

27 is a set address field optimization and cache control unit which refers to the contents of the management register 26 and outputs a pointer signal S; , thereby time-divisionally switching the set address field SAF for the tag section TG of the cache memory 10, and resetting the set address of the tag section to the access address field in which the highest hit rate was finally detected. have. The set address field optimization and cache control unit 27 also controls the access request number counter 2.
In response to the count maximum value instruction signal MXC from 4, the clear signal CLR is supplied to the hit count counter 23 and the access request count counter 24, and the purge signal 5PII is output. It has a function of invalidating the valid focus VB corresponding to an address.

The chip further includes an instruction control unit 28 that performs everything from decoding to execution of instructions, and receives an access request signal AREQI from the instruction control unit and returns 1 to the response signal AC, and also outputs the hit/miss instruction signal H/M. A storage control unit 29 that receives an access request signal AREQ and supplies an access request signal AREQ to the access request counter 24; and a storage control unit 29 that is connected between the storage control unit and an external address bus 31 and an external data bus 32; A bus control unit 30 is provided which receives the request signal AREQ2 and returns a response signal ACK2.

FIG. 2 shows an example of the operation of each component and the operation timing of each signal explained above.

As described above, according to the cache memory control method of this embodiment, the set address field SA for the tag section TG
F is switched in a time division manner, and the number of access requests based on the access request signal AREQ from the storage control unit 29 is compared with the number of hits based on the detected hit/miss indication signal H/H to detect the cash hit rate. Based on the detection results, the set address of the tag section TG is reset to the access address field in which the highest hit rate was finally detected.

That is, by dynamically managing the set address field SAF, the individual access hit rate is detected in real time, and the setting of the set address field is thereby optimized to increase the cash hit rate.

This contributes to speeding up the instruction execution process of the data processor as a whole.

In the embodiment described above, the set address field optimization and cache control section 27 dynamically manages the set address field SAF for the tag section TG of the cache memory 10 based on the cache hit rate instruction signal RTO detected by the comparator 25. However, the configuration for moving the set address field is not limited thereto.

For example, as shown in FIG. 3, the set address field setting and cache control unit 27a is controlled by a control signal for switching the number of bits (32 bits/64 bits) from outside the chip for the internal address bus 11. l0D
E, thereby causing the cache memory 10
Set address field SAF for tag part TG of
It may be configured to switch. Note that in FIG. 3, the same reference numerals as those used in FIG. 1 represent the same constituent elements, so the explanation thereof will be omitted.

[Effects of the Invention] As explained above, according to the present invention, it is possible to optimally set the set address for the tag section of the cache memory, thereby increasing the cache hit rate and speeding up instruction execution processing. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram partially schematically showing the configuration of a data processor with a built-in cache memory as an embodiment of the present invention, FIG. 2 is an operation timing diagram of the processor shown in FIG. 1, and FIG. 3 is a block diagram of the present invention. FIG. 2 is a block diagram partially schematically showing the configuration of a data processor with a built-in cache memory as another embodiment of the present invention. (Explanation of symbols) 10... Cache memory, 11... Internal address bus, 12... Physical address, 13... Decoder (
DEC), 14...Coupler, 15.16-Comparator (CMP), 17, 18...And gate, 19
...OR gate, 20.21...Tri-state Hanwha, 22...Internal data bus, 23...Hint number counter, 24...Access request number counter,
25... Comparator (CMP), 26... Management register (REG), 27... Set address field optimization and cache control unit, 27a... Set address field setting and cache control unit, 2
8... Instruction control unit, 29... Storage control unit, 30...
・Bus control unit, 31...External address bus, 32...
- External data bus, TG... tag section, DP... data section, νB... barred pit, SAF... set address field, )I/? I...Hit/miss instruction signal, RTO...Cash hit rate instruction signal, A
REQ...Access request signal, S. ... Pointer signal, SPR". Purge signal, MODE ... Bit number switching control signal.

Claims (1)

[Claims] 1. Cache memory for instructions or data (10)
In the data processor, the cache memory includes a data part (DP) and a tag part (T) that store access data and a physical address of the data, respectively.
G) and a valid bit (VB) that indicates whether the pair of address and data is valid, and has a function of managing copying of data on the main memory, and is the set address of the tag section. It comprises set address field variable means (27, 27a) for moving the access address field (SAF) in all address fields (12) on the internal address bus (11), thereby changing the set address field for the tag part of the cache memory. A cache memory control method characterized by dynamic management. 2. The method further includes means (15-19, 23-25) for detecting a cache hit rate with respect to the number of access requests from the instruction execution control unit (28, 29, 30) based on information on valid bits of the cache memory. , the set address field variable means (27) switches the access address field to be used as the set address of the tag part in a time division manner based on the detected cache hit rate result (26), and finally changes the access address field to be the set address of the tag part. 2. The cache memory control method according to claim 1, wherein the set address of the tag section is reset to the access address field in which the hit rate has been detected. 3. The set address field variable means (27a)
2. The cache memory control method according to claim 1, wherein the access address field to be used as the set address of the tag section is switched based on a bit number switching control signal (MODE) applied from the outside to the internal address bus.