JP2003216596A - Multiprocessor system and node device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of reducing unnecessary cache coincidence control and an inter-node access by the control. <P>SOLUTION: This system is constituted by connecting a plurality of nodes 100 and 200 having one or more processors each of which has a cache memory and memories. Each node has directories 150 and 250 for registering information on data in a memory within the present node registered in a cache memory of an other node and node controllers 140 and 240 for specifying a node requiring a cache coincidence control based on information registered in the directories 150 and 250. The information registered in the directories 150 and 250 is addresses of object data and registered states of object data in the other node. Each node has a means for deciding that data requested to be registered in the cache memory is an instruction code. When the data is the instruction code, the cache coincidence control is not performed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system and a node device, and more particularly, to reducing access between nodes by coincidence control processing of a cache memory in each node which is a computer constituting the multiprocessor system. The present invention relates to a multiprocessor system and a node device capable of speeding up processing.

[0002]

2. Description of the Related Art Generally, in a multiprocessor system in which a plurality of processors having a cache memory access a common memory, when one processor issues an access to a memory, the latest data exists in the cache of another processor. It is necessary to check whether or not to guarantee cache coherency. Then, in a multiprocessor system configured by a plurality of nodes (having one or a plurality of computers), inter-node access by cache coincidence control occurs.

For this reason, with the increase in the scale and speed of computers, the reduction of access between nodes by the cache coincidence control and the latency of the cache coincidence control processing are reduced.
It has become a challenge to improve the performance of the system. As a conventional technique capable of solving such a problem, for example,
The technique described in Japanese Patent Laid-Open No. 8-16474 is known. In this conventional technique, each node has a directory, and among the data of its own node memory, the physical address of the data owned by the cache memory of another node and the status bit indicating its status are registered. Status bits are Shared, Dirty (updated data), I
The three states of nvalid are shown. According to this conventional technique, when a processor issues a memory access request, cache matching control is performed in the node to which the processor belongs, and at the same time, the directory of the node to which the memory requested to access belongs is searched to obtain the target data. Is registered in the cache memory other than that node. As a result, if the target data is not registered in another node, only cache matching control in that node is executed, and if the target data is registered in another node and the status requires cache matching control. , Broadcasts the memory address to all nodes and executes cache match control processing.

[0004]

In the prior art described in the above publication, the data requested to be read from the memory is registered in the cache memory of a node different from the node to which the memory having the target data belongs. When the cache match control is required, the memory address is broadcast to all the nodes to execute the cache match control. Therefore, this conventional technique has a problem in that inter-node access to a node in which the target data is not registered and cache matching control occurs in the node in which the target data is not registered. Further, according to this conventional technique, when a request to read data that is not registered in another node is made, cache matching control is always performed in the own node, so unnecessary cache matching control in the own node is performed. It has a problem that it occurs.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to perform cache matching control in a node that does not register the target data when reading the data registered in another node is requested. , It eliminates the need for inter-node access by that, and when the data that is not registered in another node is requested to be read, unnecessary cache matching control in its own node becomes unnecessary, and the node mutual control by the cache memory matching control process becomes unnecessary. An object of the present invention is to provide a multiprocessor system and a node device capable of reducing access between terminals and speeding up processing.

[0006]

According to the present invention, said object comprises a plurality of node devices each having one or more processors each having a cache memory and one or more memories shared by said processors. In a multiprocessor system in which the plurality of node devices are connected to each other by connection means, the node device displays information about data in a memory in its own node device registered in a cache memory of another node device. A directory to be registered, and means for specifying a node device that requires cache matching control based on the information registered in the directory, wherein the directory is an address of data registered in the cache memory of another node device. , The data registered in the cache memory of the other node device is registered. It is accomplished by comprising a plurality entries having information identifying a node apparatus having a cache memory being.

Specifically, the registration status of the target data is composed of bits corresponding to each node on a one-to-one basis. By setting "1" in the bit corresponding to the node registering the target data, Indicates which node the target data is registered. All data registration status bits are "0"
Indicates that there is neither the cache memory that registers the target data nor the other node.

The present invention is also directed to when the directory overflows to overwrite the contents of the entry, or when invalidation of data registered in the directory is requested.
By referring to the registration status of the data, the node having the target data registered has means for executing the invalidation processing of the target data, and the data requested to be registered in the cache memory is the instruction code. It has a means to determine that.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a multiprocessor system and a node device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multi-computer system according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining information regarding data registered in a directory. In FIG. 1, reference numerals 100 and 200 denote node devices (hereinafter simply referred to as nodes), 110 and 11
1, 210, 211 are cache memories, 120, 12
1, 220 and 221 are processors, 130 and 230 are memories, 140 and 240 are node controllers, 150,
Reference numeral 250 is a directory (Dir), 160 and 260 are instruction code determination units, and 300 is a crossbar switch.

A multiprocessor system according to an embodiment of the present invention includes a plurality of nodes 100, as shown in FIG.
200 are connected by a crossbar switch 300. Each node 100 has a cache memory 11
Multiple processors 120, 121 having 0, 111
And one or more memories 130 shared by the plurality of processors 120 and 121, and the node controller 1
40 and a directory 150.

Although the crossbar switch 300 is used to connect the nodes to each other in the above description, the present invention is not limited to the crossbar switch and may be a bus-like one as long as the nodes can be connected to each other. It is also possible to connect the nodes to each other using a network or a network on a ring.

The node controller 140 executes cache matching control in its own node and invalidation processing of data registered in the cache memory, and issues a cache matching control request and a data invalidation processing request to another node. To do. The node controller 140 also has an instruction code determination unit 160. The instruction code determination unit 160
When the read request from the memory includes the information indicating that the target data is the instruction code, it is determined whether the data is the instruction code.

The directory 150 is a 4-way set associative type directory (actually, an arbitrary w
information about the data of the memory 130 accessed by another node is registered in each entry. As shown in FIG. 2, the information regarding the data registered in each entry of the directory 150 is stored in the memory address 1
51 and a data registration status 152. The data registration status 152 has a bit corresponding to each node. When there is a node in which the data of the memory address 151 is registered in the cache memory, "1" is set in the bit corresponding to the node. Normally, information on the data in the memory 130 accessed by the processors 120 and 121 of the own node is not registered in the directory 150. However, when the own node accesses the memory 130 of the own node, the address of the target data is already registered in the directory 150, and all the bits of the data registration status of the target data are “0”. The node controller 140 updates the data registration status.

For memory access issued by the processor, read (Read) Tx, invalidate (Invalidate) Tx, read and invalidate (Tx), and write back (Write)
Back) There are four types of Tx. Next, the operation of the system when these Tx (transactions) are issued will be described.

FIG. 3 is a flow chart for explaining the processing operation of a node when Read Tx is input from another node. First, this will be explained.

(1) Now, from the processor 220 or 221 in the node 200 to the memory 130 of the node 100.
When the Read Tx is input to the node controller 140, the node controller 140 refers to the directory 150 (step 30).
0, 301).

(2) Directory 15 in step 302
As a result of referring to 0, it is determined whether or not the address of the target data is registered in the directory 150. If the address is not registered, the node controller 140 cache-matches the cache memories 110 and 111 of its own node 100. Execute control (steps 302, 30)
3).

(3) As a result of executing the cache matching control, it is determined whether or not the target data is registered in the cache memories 110 and 111. If the target data is not registered, the node controller 140 stores the target data in the memory 130. Sent to node 200 from directory 1
The address of the target data is registered in 50, and the bit of the data registration status corresponding to the node 200 is set to "1" (steps 304 to 306).

(4) As a result of executing the cache matching control in the judgment of step 304, the cache memory 110,
If the target data is registered in any of 111, it is determined whether or not the data is changed. If not, the node controller 140 sends the target data from the memory 130 to the node 200, The address of the target data is registered in the directory 150, and the node 1
Data registration status bit corresponding to 00 and node 200
1 is set to the bit corresponding to (steps 307 to 3)
09).

(5) If it is determined in step 307 that the data has been changed, the node controller 140
From the cache memory to the memory 130 and the node 200
The latest changed target data is sent to and the address of the target data is registered in the directory 150.
The data registration status bit corresponding to 00 is set to "1" to invalidate the data registered in the cache memory of the node 100 (steps 310 and 311).

(6) If it is determined in step 302 that the address of the target data is registered in the directory 150 as a result of referring to the directory 150, the node controller 140 displays the registration status of the target data registered in the directory. With reference to the data, it is determined whether or not the bit of the data registration status of the target data has "1" set (steps 312 and 313).

(7) If it is determined in step 313 that the bit of the data registration status of the target data is not set to "1", it means that the cache memory in which the target data is registered does not exist. , The node controller 140 does not execute cache matching control,
The target data is sent from the memory 130 to the request source processor, and "1" is set to the bit of the data registration status corresponding to the request source node of the data of the entry in which the information regarding the target data is registered (steps 314 and 315).

(8) If it is determined in step 313 that the data registration status bit of the target data is set to "1", the data registration status bit set to "1" is set to 1 If there is more than one bit, that is, if there are multiple bits for which "1" is set, the target data is in a shared state and It cannot be changed (since data in one cache is updated, data in the other cache is invalidated). Therefore, the node controller 140 sends the target data from the memory 130 to the node 200, and updates the data registration status of the entry in which information about the target data in the directory 150 is registered. As a result of the update, in addition to the plurality of bits for which “1” has been set until then, the node 200
The bit of the registration status corresponding to is also "1" (steps 316, 314, 315).

(9) If it is determined in step 316 that there is only one bit for which the data registration status is "1", that is, if the node having the cache memory in which the target data is registered is If there is only one node, the node controller 140 issues a cache matching control request to the node corresponding to the bit for which "1" is set. As a result, the cache coincidence description is performed at the target node (step 317).

(10) As a result of the cache matching control being executed by another node, whether or not there is target data in the cache memory, that is, whether the target data registered in the other node is valid or invalid. If it is invalid, the node controller 140 sends the target data from the memory 130 to the node 200, and the directory 150
Update the data registration status of the entry in which the information about the target data of is registered. As a result of updating, node 20
The bit corresponding to 0 becomes "1", and the bit corresponding to the node that has executed the cache matching control is cleared (steps 318 to 320).

(11) If the target data registered in the other node is valid in the judgment of step 318, it is judged whether or not the target data registered in the other node is changed, and the target data is changed. If not, the node controller 140 sends the target data from the memory 130 to the node 200, and updates the data registration status of the entry in which information regarding the target data in the directory 150 is registered. As a result of the update, the bit corresponding to the node 200 and the bit corresponding to the node that has executed the cache matching control become "1" (steps 321, 314,
315).

(12) If it is determined in step 321 that the target data registered in the other node has been changed, the changed target data is stored in the memory 130 and the node from the cache memory of the node that executed the cache matching control. Two
00 and sent. The node controller 140 updates the data registration status of the entry in which information about the target data in the directory 150 is registered. As a result of the update, the bit corresponding to the node 200 becomes "1", and the bit corresponding to the node that has executed the cache matching control is cleared (steps 322 and 323).

FIG. 4 is a diagram showing the operation of the system when Invalidate Tx is input from another node, and FIG. 5 is a flowchart explaining the processing operation of the node when Invalidate Tx is input from another node. Then, the flow shown in FIG. 5 will be described with reference to FIG.

(1) The node controller 140 uses the Invalidate T for the data in the memory 130 of the node 100.
If x is accepted from another node, the directory 150
(Steps 500 and 501).

(2) As a result of referring to the directory 150, it is determined whether or not the address of the target data is registered in the directory 150. If the address is not registered, the node controller 140 causes the cache memory 110 of its own node 100. , 111 are confirmed (steps 502 and 503).

(3) As a result of checking the contents of the cache memories 110 and 111, it is determined whether or not the target data is registered in the cache memory. If not, the process for invalidating the target data Is unnecessary (steps 504 and 505).

(4) In step 504, if the target data is registered in any of the cache memories 110 and 111, it is determined whether the data has been changed, and if it has not been changed, The node controller 140 invalidates the target data in the cache memory (steps 506 and 508).

(5) If it is determined in step 506 that the data in which the target data is registered in either the cache memory 110 or 111 has been changed, the node controller 140 uses the latest data in the cache memory as the memory 130. And the target data in the cache memory is invalidated (steps 507 and 508).

(6) If it is determined in step 502 that the address of the target data is registered in the directory 150, the node controller 140 refers to the registration status of the target data registered in the directory and refers to the data of the target data. If there is a bit in which the registration status is set to "1", it is determined whether there is only one bit in which the data registration status is set to "1" (steps 509 and 510). .

(7) When it is determined in step 509 that only one bit of the data registration status has "1" set, that is, when there are a plurality of bits having "1" set. , The system operates as shown in FIG. That is, the node controller 140, for the node (node 1 / node n) that has registered the target data,
An instruction is issued to invalidate the target data, and the data registration status of the entry in which the information regarding the target data is registered is updated. As a result of updating, the registration status of the target data is
All bits become "0" (steps 511, 51)
2).

(8) If it is determined in step 509 that only one bit of the data registration status has "1" set, that is, if the node having the cache memory in which the target data is registered is If there is only one node, the node controller 140 gives an instruction to invalidate the target data to the node corresponding to the bit for which "1" is set. The node controller of the node that has received the instruction to invalidate the target data confirms the contents of the cache memory (step 513).

(9) As a result of checking the contents of the cache memory, the node controller of the node that has received the instruction to invalidate the target data determines whether the target data has been changed. If the target data has not been changed, Invalidates the target data in the cache memory in the local node. On the other hand, the node controller 140 in the node 100 updates the data registration status of the entry in which the information regarding the target data in the directory 150 is registered. As a result of updating, all bits of the data registration status become "0" (steps 514, 516, 517).

(10) If the target data has been changed as a result of checking the contents of the cache memory in the determination of step 514, the node controller of the node that has received the instruction to invalidate the target data of the node controller stores in the cache memory. The latest data of is written back to the memory 130 of the node 100, and the target data in the cache memory of the own node is invalidated. On the other hand, the node controller 140 in the node 100 updates the data registration status of the entry in which the information regarding the target data in the directory 150 is registered. As a result of updating, all bits of the data registration status become "0" (steps 515 to 517).

Next, from another node, Read and Invalidat
The operation when e Tx is input will be described with reference to FIG. Read and Invalidate Tx is the Re
Tx that requires both ad Tx and Invalidate Tx behavior
Is.

Now, the processor in the node 200 reads and invalidates the memory 130 of the node 100.
When e Tx is input to the node 100, the target data by this Tx is sent to the node 200 in the same manner as the operation when Read Tx described above is input. that time,
The node controller 140 issues an invalidation request to the cache memory in which the target data has been registered, and updates the data registration status of the entry in the directory 150 in which the information regarding the target data is registered. As a result of the update, only the bit corresponding to the node 200 becomes "1", and the other bits are cleared.

Next, the operation when Write Back Tx is input from another node will be described with reference to FIG.

When a Write Back Tx for the memory 130 of the node 100 is input to the node 100 from the processor in the node 200, the target data by this Tx is written back from the cache memory of the node 200 to the memory 130 of the node 100. . Then, the node controller 140 updates the data registration status of the information regarding the target data in the directory 150. As a result of the update, the bit corresponding to the node 200 is cleared. Write Back
Since the data written back by Tx is not registered in the cache memory of another node, all bits are "0" in the registration status of the data.

FIG. 6 is a flowchart for explaining the processing operation of the node when Read Tx (or Read and Invalidate Tx) is input from the own node to the memory of the own node. Next, the flow shown in FIG. 6 will be explained. To do.

Normally, when the processor in the own node 100 accesses the own node memory 130, the node controller 140 uses the directory 150.
Does not register the address of the target data or update the data registration status. However, when the processor in the own node 100 issues Read Tx or Read and Invalidate Tx to the memory 130 of the own node, the address of the target data is registered in the directory 150, and Invalidate Tx and Write Back Tx are registered. If all the bits of the data registration status of the target data are “0”, the node controller 140 reads the data from the memory 130 and updates the data registration status of the target data. As a result of the update, only the bit corresponding to the node 100 is set to "1".

As described above, when the target data is registered in the directory 150 when the Read Tx or Read and Invalidate Tx is input to the own node memory 130, the node controller 140 updates the data registration status of the target data. . Therefore, Read Tx or Read and Read from the other node to the memory 130 of the node 100 is performed.
When the Invalidate Tx is input, if the target data is registered in the directory 150 and the data registration statuses of the target data are all “0”, the target data is also stored in the cache memory of other nodes. It is not registered in the cache memories 120 and 121 in the node 100. Therefore, the node controller 140 sends the target data from the memory 130 without executing the cache matching control in the node 100.

The processing of the node when Read Tx or Read and Invalidate Tx for the own node memory is input is performed as described above. The processing flow is
As shown in FIG. 6, it is basically the same as that described with reference to FIG. 3, and is different from the flow of FIG. 3 in that the processing of steps 305, 306, 309, and 311 in FIG. 3 is unnecessary. As a result of executing the cache matching control in the determination of 304, if the target data is not registered in any of the cache memories 110 and 111, the process shifts to the process of step 308 instead of the process of step 305, and That is, the processing of steps 601 to 603 in which the data request source node in the processing of steps 315, 320, and 323 is replaced with its own node is performed.

Next, the operation when Write Back Tx is input from the self node will be described with reference to FIG.

Write Back for own node memory 130
When Tx is input, the node controller 140 refers to the directory 150. As a result of referring to the directory 150, if the address of the target data is not registered in the directory, the node controller 140
Writes the target data back to the memory 130. Also, as a result of referring to the directory 150, if the address of the target data is registered in the directory, the data registration status of the target data is that only the bit corresponding to the own node is always “1”. 140
Writes the target data back to the memory 130 and updates the directory 150. As a result of the update, all bits of the data registration status of the target data are “0”.

FIG. 7 is a diagram for explaining the processing operation when the directory overflows. Next, this will be described. This process is performed from node 200 to node 10.
Read Tx or Read and I for 0 memory
When nvalidate Tx is input, when the target address is not registered in the directory 150 and all the entries of the same index as the target address of the directory 150 are used, it is the process of overwriting the entry that is controlled twice. The illustrated example is a case where an entry in which information about data at address A is registered is overwritten by information about data at address B.

Now, ReadTx or Rea for the address B of the memory 130 of the node 100 from another node
When d and Invalidate Tx is input, it is assumed that the address B is not registered in the directory 150 and there is no empty entry with the same index as the address B. In this case, the node controller 140 selects the entry to be overwritten, for example, the entry in which the address A is registered, from the four entries of the index. Then, in order to guarantee the coherency of the cache, the address A registered in the selected entry is
Data is invalidated. Therefore, the node controller 140 refers to the data registration status of the address A, issues a request for invalidating the data of the address A to the node that has registered the data of the address A, and then reads Read Tx for the address B, Alternatively, the Read Invalidate Tx is processed, and the entry registered at the address A is added to the address B.
Register information about.

Next, the determination of the instruction code by the instruction code determination section in FIG. 1 will be described.

The instruction code determining section 160 in the node controller 140 determines whether the target data is an instruction code when receiving the Read Tx for the memory. In general, when the system adopts an architecture that does not change the instruction code, if the target data is the instruction code, it cannot be changed even if it is registered in the cache memory. Therefore, if the data requested to be read is an instruction code, no matter what the registration status of the target data is, the node controller 1
The reference numeral 40 sends the target data from the memory 130 without executing the cache matching control.

According to the above-described embodiment of the present invention, each node has a directory for registering the address of the data registered in the other node and the information of the node registering the target data. As a result, it is possible to reduce the inter-node access to the node in which the target data is not registered and the cache match control in the node in which the target data is not registered, which occurs due to the cache match.

Further, by providing the means for judging whether or not the data requested to be read is the instruction code, it is possible to reduce the cache matching control for the data which is not changed.

[0056]

As described above, according to the present invention, in a multiprocessor system composed of a plurality of nodes, when the reading of the data registered in another node is requested, the target data is registered. It eliminates the need for cache matching control in a node that does not exist and the access between nodes due to that, and when the data that is not registered in another node is requested to be read, unnecessary cache matching control in its own node is not needed It is possible to reduce the access between the nodes by the coincidence control processing of the memory and speed up the processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multi-computer system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating information about data registered in a directory.

FIG. 3 is a flowchart illustrating a processing operation of a node when Read Tx is input from another node.

FIG. 4 is a diagram showing an operation of the system when Invalidate Tx is input from another node.

FIG. 5 is a flowchart illustrating a processing operation of a node when Invalidate Tx is input from another node.

FIG. 6 Read T from the own node to the memory of the own node
9 is a flowchart illustrating a processing operation of a node when x or Read and Invalidate Tx is input.

FIG. 7 is a diagram illustrating a processing operation when a directory overflows.

[Explanation of symbols]

100, 200 nodes 110, 111, 210, 211 cache memory 120, 121, 220, 221 processors 130, 230 memory 140, 240 node controller 150, 250 directory (Dir) 160, 260 instruction code determination unit 300 crossbar switch

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06F 15/16 645 G06F 15/16 645 (72) Inventor Atsushi Nakajima 810 Shimoimaizumi, Ebina, Kanagawa Prefecture Stock Association Company Hitachi Ltd. Internet Platform Division (72) Inventor Yuji Kuruma 1-280 Higashi Koikekubo, Kokubunji City, Tokyo F-Term (Central), Central Research Laboratory, Hitachi, Ltd. (reference) 5B005 JJ01 KK03 KK13 LL01 MM01 PP11 PP21 5B045 BB16 DD12

Claims (6)

[Claims] 1. One each having a cache memory
Alternatively, in a multiprocessor system including a plurality of node devices having a plurality of processors and one or a plurality of memories shared by the processors, the plurality of node devices being mutually connected by a connecting means, the node The device identifies a directory for registering information about the data in the memory in its own node device registered in the cache memory of another node device, and a node device requiring cache matching control based on the information registered in the directory. A node device having a cache memory in which the address of the data registered in the cache memory of the other node device and the data registered in the cache memory of the other node device are registered. Information that identifies the Multiprocessor system, characterized in that. 2. The node device has means for erasing the contents of the entry of the directory, and a node device having a cache memory in which data registered in the entry is registered, registered in the cache memory. 2. The multiprocessor system according to claim 1, further comprising means for invalidating the data that is being processed. 3. The node device, in response to an invalidation request for data registered in the directory, registers the data in the cache memory with respect to the node device having the cache memory. 2. The multiprocessor system according to claim 1, further comprising means for invalidating the existing data. 4. The node device, when the processor of the own node device requests data read from the memory of the own node device, the address of the data is registered in the directory of the own node device, and the data is stored in the directory of the own node device. 2. The multiprocessor system according to claim 1, wherein when there is no node device having a registered cache memory, the fact that the cache memory of the own node device has registered the data is registered in the directory. 5. The node device, when requested to read data from its own node memory, determines whether or not the data is an instruction code, and if not, executes cache match control. Claim 1 characterized by
The described multiprocessor system. 6. A node device in a multiprocessor system configured by connecting a plurality of node devices to each other by connecting means, wherein the node device is shared by one or a plurality of processors having a cache memory and the processor. One or a plurality of memories, a directory for registering information about the data of the memory in the own node device registered in the cache memory of another node device, and cache matching control based on the information registered in the directory are required. Means for identifying a node device, wherein the directory is a cache in which the address of the data registered in the cache memory of the other node device and the data registered in the cache memory of the other node device are registered. Information that identifies the node device that has the memory Node device characterized by comprising a plurality entries that.