JPH0496545A - Asynchronous transfer mode exchange method and asynchronous transfer mode exchange and switching circuit - Google Patents

Abstract

PURPOSE:To make internal configuration of a logic switch of each stage coincident and to make each stage in common by using the logic switch of each stage to read each logic code of a switching header and shifting the code to the tail end of the switching header. CONSTITUTION:A logic switch 300 is switched according to a head bit of a switching header HD inputted from a pre-stage header shift circuit 400 to decide an output destination of a next stage, a header shift means 400 shifts a head bit of a switching header HD to a tail end of the switching header HD and the bit to be read by a next stage logic switch 300 is transferred to a next stage while the bit is brought to a top. Thus, a header shift circuit 400 of each stage makes the same operation that the head bit is transferred to a tail end of the switching header HD and a logic switch 300 of each stage reads only the head bit of the switching header HD and is switched to transfer a cell.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an asynchronous transfer mode switching method, an asynchronous transfer mode switch, and a switching header for exchanging all kinds of data such as voice, image, facsimile, etc.

(Prior Art) In recent years, progress has been made in the development of an ATM (Asynchronous Transfer Mode) exchange system that enables the exchange of all kinds of data such as voice, images, and facsimile.

This ATM switching method adds a logical channel number for transfer to transmitted data (cells), and uses this logical channel as an ATM
This is referred to by the exchange, and the cells are guided at high speed to the outgoing line corresponding to this logical channel, and the data is transmitted to a predetermined destination.

As such an ATM switch, an ATM switch equipped with a switch circuit network such as a Batcher network or a Banyan network, which is formed by connecting logical switches in multiple stages, has been considered. (“Nikkei Electronics (published January 11, 1988, N043)
8) J, 17), pp. 132-137, see the article ``High-speed switching circuit system holds the key to practical application'').

In this ATM switch, a switching header corresponding to a logical channel is attached to the transmitted data according to the destination, and the transmitted data with this switching header added is transmitted through simple switching of the logical switch within the switch circuit network. Transfer data at high speed and send it to a desired destination using only operations.

The switching header is composed of the same number of logic codes as the number of stages of logic switches.

The switch circuit network of the ATM exchange that receives the transmission data with this switching header added performs a switching operation in the first stage logical switch according to the logical code at the head of the switching header, and thereby performs a switching operation according to the logical code at the beginning of the switching header. The switching header and transmission data are transferred to the logical switch, and then the second-stage logical switch performs a switching operation according to the second logical code of the switching header, and the data is transferred to the third-stage logical switch.

Similarly, the logic switch in each stage performs a simple switching operation in accordance with each logic code of the switching header corresponding to the number of stages, thereby leading transmission data to a desired output line at high speed.

(Problem to be Solved by the Invention) However, in the conventional technology, each logic code of the switching header is sequentially read by the logic switch in each stage, so the reading position of the switching header is different in each stage, and the switching header is read at a different position in each stage. The internal configurations of the logic switches in the two stages were different, and there was a problem in that it was not possible to standardize each stage.

Therefore, various problems arise, such as it is difficult and expensive to integrate the switch circuit network, and it is disadvantageous when attempting to expand the network.

The present invention solves these problems and allows each stage of logical switches to read the same position of the switching header. Therefore, the internal configuration of each logical switch can be shared, thereby improving expandability. It is an object of the present invention to provide an asynchronous transfer mode switching method, an asynchronous transfer mode switch, and a switching header that are highly efficient and can be integrated at low cost.

(Means for Solving the Problems) In order to solve the above problems, an asynchronous transfer mode switching method according to the present invention provides a switch circuit that transmits data to which a switching header is added when transferring data within a switch circuit network. At each stage of the network, the destination to send to the next stage is determined by reading the logical code at the beginning of the switching header, and before the transmission data is transferred to the next stage, the logical code at the beginning of the switching header is switched. By shifting to the last part of the header, the logical code to be read in the next stage is moved to the beginning of the switching header, and the logical code at the beginning of the switching header is always referred to and transferred.

The asynchronous transfer mode switch according to the present invention inputs the transmission data transferred from the previous stage logical switch between the stages of each logical switch of the switch circuit network, and adds the first part of the switching header added in front of the transmission data. Each stage is equipped with a header shift means that shifts the logic code to the last part of the switching header and transfers it to the next stage logic switch, and the logic switch at each stage shifts the transmitted data to the next stage based on the logic code at the beginning of the switching header. or transfer to the output line.

Further, in this asynchronous transfer mode switch, the header shift means inputs transmission data consisting of a switching header and subsequent data from a logical switch, and converts this transmission data into a logical code at the head of the switching header and a logical code at the beginning of the switching header. a dividing means for dividing and transmitting the subsequent code and subsequent data respectively; a storage means for temporarily storing the first logical code of the switching header and the subsequent data among the transmission data divided by the dividing means; The subsequent codes of the switching header separated by the means are sequentially read and sent out.Following these subsequent codes, the first code of the switching header stored in the storage means is read out and sent out, and further the subsequent data is read out from the storage means and sent out sequentially. It is characterized by comprising a converting and sending means for sending.

The switching header of the present invention includes a switching means that performs a switching operation based on the logical initial code at the head of the switching header to determine the output destination of input data, and a switching means that performs a switching operation based on the logical initial code at the head of the switching header, and a switching means that switches the logical code at the head of the switching header read by the switching means. The switching header is characterized by comprising a header shift means for shifting the switching header to the last part of the switching header and transferring the switching header and input data to an output destination.

Furthermore, in this switching header, the header shift means converts the input data composed of the switching header and subsequent data into a logical code at the beginning of the switching header,
A dividing means for dividing the switching header into a subsequent code and subsequent data, a storage means for respectively storing the first logical code of the switching header divided by the dividing means and the subsequent data, and this storage means. is connected to the dividing means, reads the subsequent code of the switching header divided by the dividing means and sends it first, then sends out the first code read from the storage means, and then reads out the first code read from the storage means. and converting and transmitting means for sequentially transmitting the subsequent data.

(Function) According to the present invention, switching headers corresponding to the logical switches at each stage in the switch network of the exchange are added to the transmission data input to the exchange, and the transmission data is transferred within the switch circuit network. When transmitting to a desired destination, a logical switch reads the logical code at the head of the switching header, performs a switching operation according to that value, and determines the destination of the transmitted data to the next stage. In this case, when transmitting data is transferred to the next stage, the header shift means shifts the first logical code of the switching header read by the previous stage logical switch to the last part of the switching header, so that the next stage logical switch The logical code of the switching header to be read at the stage is shifted to the top, and the shift processing is performed so that only the first code of the switching header is always read at each stage. This ensures that the same processing is performed on the switching headers at all stages of the switch network.
The circuit configuration is made uniform in all stages.

(Embodiments) Next, embodiments of an asynchronous transfer mode switching method, an asynchronous transfer mode switch, and a switching header of the present invention will be described in detail with reference to the accompanying drawings.

The asynchronous transfer mode (ATM) switch in this embodiment has a plurality of input lines 100 (100
A header addition circuit 10 (10-11 to 1O-pp) that adds a switching header to each input transmission data (cell) Ili from -11 to 100-pp), and a switching header added by this header addition circuit 10. The transmission data is sent to the desired output line 200 (200-1
1 to 200-pp).

As shown in FIG. 3(a), the transmission data Di includes a destination header AD indicating the destination terminal and data TD to be transmitted to the terminal.
It consists of

The switching connector circuit 10 receives this transmission data [
]i, the switching codes Sl, S2 . ．． ．． ．． This circuit adds a switching header III consisting of Sn, and serially sends the cell to the switch circuit network 20 from the switching code Sl as an old cell.

The switch circuit network 20 includes a plurality of logical switches 300 (
300-11 to 300-np) are connected in multiple stages,
A header shift circuit 400 (400-111 to 400-npp) is provided on the output side of each of these logic switches 300.
It is equipped with In this embodiment, the switch circuit network 10 includes logic switches 300 arranged in P rows and N columns, and a header shift circuit 400 connected between these stages.
They are becoming integrated together.

Each logic switch 300 has P input terminals and P output terminals, and has a switching header HD.
The switching codes Sl, S2. ．． ．． ．． This is a switching header that serially sends input cells as they are to a desired output terminal by performing a switching operation based on either Sn. For example, when the logic switch 300 is a unit switch with 2×2 input/output terminals, by reading 1 bit of the switching code, if the switching code is "1", one output terminal 4B switching code is set. is “0”
If so, a switching operation is performed to send out the input cell to the other output terminal. Similarly, for PxP switches,
Switching codes St, S2 . ．． ．． Sn
Read one of the P and specify it with that switching code.
A switching operation is performed on one of the output terminals of the tree to send out the input cell as it is.

The input terminals of the first-stage logic switches 300-11 to 300-1p are connected to the switching header addition circuits 10-11 to 300-1p.
-pp to input lines 100-11 to 100-pp, respectively.

The output terminals of the final stage logic switches 300-nl-300-np are connected to header shift circuits 400-nil to 400-nl, respectively.
Output lines 200-11 to 200- through 400-npp
connected to pp.

Mutual connections between each stage of the logic switches 300-11 to 300-np are provided by header shift circuits 400-111, respectively.
゜400-112. , , and are connected based on the transfer processing procedure. For example, when data is rearranged and transferred depending on the size relationship of the switching headers 200-11, 200-12. ,．．
The respective stages are connected so that they are rearranged and guided in the order of ascending powers or descending powers in the order of 200-pp.

The header shift circuit 400 receives a cell from each previous-stage logic switch 300, shifts the first switching code in the switching header HD of the cell to the last part of the switching header HD, and moves this shifted switching header HD to the first part. This is a circuit that sends the cell to the logical switch 300 at the subsequent stage.

The internal configuration of the header shift circuit 400 will be described in detail. As shown in FIG. has been done.

The dividing circuit 1 inputs cells serially sent from the logic switch 300 in the order of switching header HD, destination header AD, and data TD, sends the switching code at the beginning of the switching header HD to the buffer 2, and sends this to the buffer 2. It is a dividing means that sends out the subsequent code of the switching header HD following to the selector 4, and sends out the destination header AD and data TD to the buffer 3, respectively.

The buffer 2 is a storage means for temporarily storing the switching code at the beginning of the divided switching header, and writes the switching code based on the control signal sent from the control circuit 5.
Similarly, the stored switching code is sent to the selector 4 based on the control signal. Similarly, the buffer 3 temporarily stores the destination header AD and data TD, and sends the stored contents to the selector 4 based on a control signal sent from the control circuit.

The selector 4 starts with the subsequent code of the switching header sent from the dividing circuit 1, and then sequentially selects the subsequent logic of the switching code read from the buffer 2, the destination ladder AD and the data TO read from the buffer 3, in this order. It is a conversion and sending means that sends out to the switch 300.

The control circuit 5, based on the input timing of the input cell,
A switching signal C1 is sent to the dividing circuit 1 to control the data destination, a write signal W and a read signal R are sent to the buffer 2.3 to control reading and writing of data, and a switching signal is sent to the selector 4. This is a control means that controls sending out C2 and switching the read destination.

Next, the ATM exchange method of this embodiment will be explained together with the operation of the ATM exchange. In this example, the above A
An example in which the logical switch 300 of a TM exchange is a 2×2 unit switch will be described.

First, send data D shown in FIG. 3(a) to the ATM switch.
When i is input, the switching header addition circuit lO is
Based on the destination header AD, N-bit switching headers Sl, S2 . ．． ．． .

The cell DI with Sn added is connected to its switching header H.
The signals are sent serially from D to the first-stage logic switch 300 of the switch circuit network 20.

This first-stage logical switch 300 is a switching header H.
Read the first bit (Sl) of cell D, and if these bits 1-8l are "1", switching is performed to the two output terminals, and if it is rOJ, it is switched to the lower output terminal.
Outputs 1.

Cell D1 output from this first stage logic switch 300
is sent out from the switching additional circuit 10 in FIG.
This is the same sequence as b).

The shift circuit 400 to which this transmission data has been inputted, in the division circuit 1, selects the first bit (Sl) of the switching header HD.
Transmission data Di consisting of subsequent pins S2 to Sn of switching header HD, destination header AD and data Tll
The first bit S1 of the switching header HD
is stored in the buffer 2, and the switching headers 52 to S
n to the selector 4, and the destination header AD and data TD are stored in the buffer 3.

The selector 4 selects the input switching headers S2 to Sn.
is first sent, then the bit S1 stored in buffer 2 is read and the bit S1 is sent out, followed by the destination header and data A stored in buffer 3.
Read D and send it.

As a result, the second stage logical switch 300 has
As shown in C), switching header) 10 is connected to pin 1.
-52. S3. ..., Sn, Sl in the order of cell D2 is input.

The logic switch 300 in the second stage reads the leading pins 1-82 of the switching header HD in cell I)2, and similarly to the first stage, if the bit S2 is "1", it outputs the output to the upper output terminal. If it is "0", it switches to the lower output terminal and sends out the cell D2.

The next shift circuit 400 that receives this cell I12 converts the leading bit S2 to the switching header HD in the same way as above.
The cell D3 shown in FIG. 3(d) is sent to the third stage logic switch 300.

Similarly, the switching header input from the previous stage header shift circuit 400 is controlled by the logic switch 300)
A switching operation is performed according to the first bit of the switching header HD to determine the output destination of the next stage, and before sending it to the next stage logical switch 400, the first bit of the switching header HD is shifted to the last part of the switching header HD by the header shift means 400. Then, the bit to be read by the logic switch 300 at the next stage is transferred to the next stage with the bit to be read at the beginning.

In this way, the header shift circuit 400 at each stage performs the same operation of shifting the first bit to the last part of the switching header HD, and the logic switch 300 at each stage performs a switching operation by reading only the first bit of the switching header HD. Transfer cells.

At the final stage, the cells transferred in this way
to the desired output line 200. In this case, the cell Dn includes the final stage header shift circuits 400-nil to 400-
At 11 pP, the final bit (Sn) is shifted from the beginning of the switching header to the end, and is output as cells in the same arrangement as the input state, as shown in FIG. 3(d).

In this embodiment, a 2×2 unit switch is used for each logic switch 300, and the switching header HD is read and transferred one bit at each stage. Output logic switch 30
When using 0, switching codes Sl, S2 . ．． ．． ．． A switching header HD consisting of Sn is set, and switching codes Sl, S2 . ．． ．． ．． The transfer destination may be determined based on Sn, and the header shift circuit 400 may shift the data one unit code at a time and transfer the data.

In addition, in the above ATM exchange, the switch circuit network 2
0 was integrated, but as shown in FIG. 4, a PxP logic switch similar to the logic switch 300 in FIG.
By connecting the switching headers 500 that are integrated with the header shift circuit 400 shown in FIG. Alternatively, when expanding the above switch circuit network, the number of stages can be freely increased or decreased by connecting the switch header 500 shown in FIG. 4.

(Effects of the Invention) As explained above, according to the present invention, each logic code of the switching header is read by the logic switch of each stage and then shifted to the rearmost part of the switching header.
The reading position of each logical code is the same in each stage,
The internal configuration of the logic switches in each stage can be made the same, and each stage can be shared.

Therefore, it is possible to easily integrate the switch circuit network, and when expansion is desired, it is possible to easily expand the network by simply connecting the switching header of the present invention.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of an asynchronous transfer mode switch according to the present invention, Fig. 2 is a block diagram of a header shift circuit in the same embodiment, and Fig. 3 is an asynchronous transfer mode switch according to the present invention. A cell configuration diagram in an embodiment of the transfer mode switching method. FIG. 4 is a block diagram showing an embodiment of a switching header according to the present invention. Explanation of symbols of main parts 1101 Division circuit 2, 3.../<Sofa 410, selector 531. Control circuit 10 , Switching header addition circuit 20 , Switch network 100 , Input line 200 , Output line 300 , Logic switch 400 , Header shift circuit 500 , Switching header DiNDn, Cell HD, Switching header S1 to Sn, Switching code (logical code) Patent applicant: Oki Electric Industry Co., Ltd. Representative Number: Takao Oki

Claims (1)

[Claims] 1. A switching header for transfer is added to transmission data according to its destination, and a logical switch performs a switching operation on the transmission data to which the switching header has been added based on the switching header. In the asynchronous transfer mode exchange method, which transfers data at high speed within a switch network connected in multiple stages to the desired outgoing line and performs exchange processing, the transmitted data with a switching header is transferred within the switch network. When transmitting data, the destination to send to the next stage is determined by reading the logic code at the beginning of the switching header at each stage of the switch circuit network, and before transmitting this data to the next stage, the switching An asynchronous transfer mode exchange method characterized in that the logical code at the head of the header is shifted to the last part of the switching header, and the logical code to be read at the next stage is shifted to the head of the switching header and transferred. 2. A switching header adding means that adds a switching header for transfer based on the destination header to the transmitted data to which each destination header is attached, and a switching header adding means that is connected to the switching header adding means and transfers the transmitted data to a desired transfer destination. In an asynchronous transfer mode exchange, the switch circuit network is provided with a switch circuit network in which a logical switch in each stage performs a switching operation based on each logical code of a switching header added by the switching header adding means, The switch circuit network inputs transmission data transferred from the previous stage logical switch between stages of each logical switch,
Each of the logical switches at each stage is equipped with header shifting means for shifting the first logical code of the switching header added before the transmission data to the last part of the switching header and transferring it to the logical switch at the subsequent stage. An asynchronous transfer mode switch characterized in that transmit data is transferred to the next stage or output line based on the logical code at the head of a switching header. 3. In the asynchronous transfer mode switch according to claim 2, the header shifting means inputs the transmission data composed of a switching header and subsequent data from the preceding logical switch, and converts this transmission data into a switching header. A dividing means that divides and transmits the first logical code, the subsequent code of the switching header, and the subsequent data, and the first logical code of the switching header and the subsequent data among the transmission data divided by the dividing means. a storage means for reading and temporarily storing each; and sequentially reading and transmitting the subsequent codes of the switching header separated by the dividing means, and reading the codes stored in the storage means following the subsequent codes of the switching header. 1. An asynchronous transfer mode switching system, further comprising converting and transmitting means for reading subsequent data from said storage means and sequentially transmitting the data. 4. In a switching circuit that switches the output destination of input data based on a switching header attached to the input data, the switching circuit determines the output destination of the data by performing a switching operation based on the logical code at the beginning of the switching header. and header shifting means that shifts the leading code of the switching header read by the switching means to the last part of the switching header and transfers the switching header and input data to an output destination. switching circuit. 5. In the switching circuit according to claim 4, the header shifting means converts input data composed of a switching header and subsequent data into a logical code at the head of the switching header, a subsequent code of the switching header, and a subsequent code. a storage means for temporarily storing the leading logical code of the switching header divided by the dividing means and subsequent data; and a storage means connected to the storage means and the dividing means. , a conversion in which the subsequent code of the switching header divided by the dividing means is read and sent out first, then the code read out from the storage means is sent out, and then the subsequent data read out from the storage means is sequentially sent out. A switching circuit comprising a sending means and.