JPH0496327A - Etching method - Google Patents

Etching method

Info

Publication number
JPH0496327A
JPH0496327A JP21468190A JP21468190A JPH0496327A JP H0496327 A JPH0496327 A JP H0496327A JP 21468190 A JP21468190 A JP 21468190A JP 21468190 A JP21468190 A JP 21468190A JP H0496327 A JPH0496327 A JP H0496327A
Authority
JP
Japan
Prior art keywords
layer
etching
sidewall
thin film
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21468190A
Other languages
Japanese (ja)
Inventor
Osamu Kinoshita
修 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP21468190A priority Critical patent/JPH0496327A/en
Publication of JPH0496327A publication Critical patent/JPH0496327A/en
Pending legal-status Critical Current

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  • Physical Vapour Deposition (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To facilitate a control of shaping a tapered longitudinal section, by repeating alternately a first process for removing selectively and isotropically only the unnecessary part of an etching layer and a second process for depositing a material, different from the etching layer, to form a sidewall on the side part of a mask pattern in such a manner that the material deposits even in the undercut part removed in the first process. CONSTITUTION:After forming a sidewall 4a, an etching gas is introduced, and only an Al layer 2 is removed selectively and isotropically by using a resist pattern 1 and the sidewall 4a as masks. Moreover, this removing of the Al layer 2 is performed in its thickness direction and partially. Then, a deposition gas is introduced again, and by sputter etching, a sidewall 5a is formed on the side part of the sidewall 4a in such a manner that it extends into the undercut part of the Al layer 2. Thereafter, the etching gas is introduced again, and via a process for forming a thin film, performed are repeatedly the process for shaping the thin film into a sidewall and the process for etching the Al layer selectively, partially and in isotropic way.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造プロセスに用いられるエツ
チング方法に関し、特に、A1等の金属層や多結晶シリ
コン等の半導体層、S iO2等の絶縁層をテーパー状
に除去するエツチング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an etching method used in the manufacturing process of semiconductor devices, particularly for etching a metal layer such as A1, a semiconductor layer such as polycrystalline silicon, a semiconductor layer such as SiO2, etc. The present invention relates to an etching method for removing an insulating layer in a tapered shape.

〔従来の技術〕[Conventional technology]

かかるテーパーエツチングの方法と(7て、■レジスト
パターンの後退を利用1.たドライエツチング方法や、
■レジストパターンの形状を制御づ゛る方法(特開昭6
4−1.5933号公報参照)、■側壁に保護膜を堆積
し、なからエツチングを行う方法(特開平:l−127
687号公報参照)、■異方性エツチングと薄膜の堆積
とを交互に行う方法(特開昭63−233535号公報
参照)等が知られている。
Such taper etching method (7);
■Method for controlling the shape of resist pattern (Unexamined Japanese Patent Publication No. 6)
4-1.5933), ■ method of depositing a protective film on the side wall and etching it from scratch (Japanese Patent Application Laid-Open No. 1999:1-127).
687 (see Japanese Patent Laid-Open No. 63-233535), and (2) a method in which anisotropic etching and thin film deposition are performed alternately (see Japanese Patent Laid-Open No. 63-233535).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

17かし、上記■のレジストパターンの後退を利用した
ドライエツチング方法では、1ノジストバタ−ンを通常
よりも厚く形成しておく必要があり、線幅等が細くなる
につれ高精度のエツチングが困難になる。また、レジス
トパターンの厚みが薄くなる段差上部ではエツチング中
にレジストパターンが消失してしまい、不必要な部分ま
でエツチングされるおそれがある。
17 However, in the dry etching method using the recession of the resist pattern described in (1) above, it is necessary to form one resist pattern thicker than usual, and as the line width etc. become thinner, high precision etching becomes difficult. Become. Moreover, the resist pattern may disappear during etching at the upper part of the step where the thickness of the resist pattern is thinner, and unnecessary portions may be etched.

上記■のレジストパターンの形状を制御する方法では、
レジストパターンの形状制御のために新たな工程を付加
しなければならず、その分、工程が煩雑になる。更に、
エツチング形状はレジストパターンの形状に依存すると
ころが大きいので、素子の微細化には対応することが難
しい。
In the method of controlling the shape of the resist pattern described in ■ above,
A new process must be added to control the shape of the resist pattern, and the process becomes complicated accordingly. Furthermore,
Since the etching shape largely depends on the shape of the resist pattern, it is difficult to respond to miniaturization of elements.

上記■の側壁に保護膜を堆積しながらエツチングを行う
方法では、プラズマ中で行われる保護膜の堆積とエツチ
ングの反応が複雑であり、十分に解明されていないため
、テーパー角の制御は経験に頼らざるを得ない。このた
め、ガス系や実験条件を変更した場合には、得られる結
果を予め予測することは困難である。
In the method (2) above, in which etching is performed while depositing a protective film on the sidewalls, the reaction between the deposition of the protective film and etching that takes place in plasma is complex and not fully understood, so controlling the taper angle requires experience. I have no choice but to rely on it. Therefore, when changing the gas system or experimental conditions, it is difficult to predict in advance the results that will be obtained.

上記■の異方性エツチングと薄膜の堆積とを交互に行う
方法では、被エツチング層の不必要部分を異方的にエツ
チングする工程と、薄膜の不必要部分を除去して側壁ス
ペーサとして残す工程とが共に、不必要部分の物理的除
去が支配的となる異方性エツチングにより行われる。こ
のため、薄膜の不必要部分が除去された後、被エツチン
グ層の不必要部分を除去する場合に、薄膜から形成され
た側壁スペーサもエツチングされて後退してしまう。こ
のため、テーパー角等の断面形状の制御が難しい。
In the method (2) above, in which anisotropic etching and thin film deposition are performed alternately, there is a step of anisotropically etching unnecessary portions of the layer to be etched, and a step of removing unnecessary portions of the thin film and leaving them as sidewall spacers. Both are performed by anisotropic etching in which physical removal of unnecessary portions is dominant. Therefore, when the unnecessary portion of the layer to be etched is removed after the unnecessary portion of the thin film is removed, the sidewall spacer formed from the thin film is also etched and retreated. Therefore, it is difficult to control the cross-sectional shape such as the taper angle.

そこで、上述の事情に鑑み、本発明は、テーパー角等の
断面形状の制御が容易なエツチング方法を提供すること
を目的としている。
Therefore, in view of the above-mentioned circumstances, an object of the present invention is to provide an etching method that allows easy control of the cross-sectional shape such as the taper angle.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的を達成するため、本発明によるエツチング方
法においては、被エツチング層の不必要部分だけを等方
向にかつ部分的に除去する第1工程と、マスクパターン
の側方に第1工程で除去されたアンダカット部まで回り
込んだ側壁を被エツチング層と異なる材質で形成する第
2工程とからなり、これら第1工程及び第2工程を交互
に繰り返し行うことを特徴としている。
In order to achieve the above object, the etching method according to the present invention includes a first step in which unnecessary portions of the layer to be etched are partially removed in the same direction, and a first step in which unnecessary portions of the layer to be etched are removed in the same direction. and a second step of forming the side wall extending to the undercut portion made of a material different from that of the layer to be etched, and is characterized in that the first step and the second step are alternately repeated.

〔作用〕[Effect]

このようにしたので、被エツチング層の不必要部分が除
去される工程において、側壁がエツチングされることな
く、被エツチング層の不必要部分のみが部分的に除去さ
れるようになる。
By doing this, in the process of removing unnecessary portions of the layer to be etched, only the unnecessary portions of the layer to be etched are partially removed without etching the sidewalls.

〔実施例〕〔Example〕

以下、本発明の実施例について第1図を参照しつつ、説
明する。
Embodiments of the present invention will be described below with reference to FIG.

第1図は、本発明を適用してアルミニウム層(以下、A
、17層と称す)をテーパーエツチングする場合に、A
1層がどのようにしてテーパーエツチングされるかを工
程順にその断面をもって示した図である。
FIG. 1 shows an aluminum layer (hereinafter referred to as A) obtained by applying the present invention.
, 17 layers), A
FIG. 3 is a cross-sectional view showing how one layer is tapered etched in the order of steps.

同図(a)は、エツチング前の断面を示しており、被エ
ツチング層として半導体基板3上に形成されたA1層2
の表面には、レジストパターン1が形成されている。
Figure (a) shows a cross section before etching, and shows the A1 layer 2 formed on the semiconductor substrate 3 as a layer to be etched.
A resist pattern 1 is formed on the surface.

本発明によるエツチング方法により、このAfI層2は
次のようにしてテーパーエツチングされる。
According to the etching method according to the present invention, this AfI layer 2 is tapered etched as follows.

まず、CHCg3等のデボジッションガスを導入し、同
図(b)に示したように、レジストパターン1の上から
Al1層2上に薄膜4を形成する。次に、B1113等
のガスを導入し、物理的除去法であるスパッタエツチン
グにより、A1層表面に対して略垂直に薄膜4を除去す
る。これにより、レジストパターン1の側部に形成され
た部分を残して薄膜4が除去され、レジストパターン1
の側部に残された部分が側壁4aとなる(同図(C)参
照)。このようにして、側壁4aが形成された後、0g
2等のエツチングガスを導入し、エツチングガスの化学
的作用により、レジストパターン1及び側壁4aをマス
クにA1層2のみを選択的にかつ等方向に除去する(同
図(d)参照)。しかも、このA9層2の除去は、この
層の厚み方向において部分的に行う。そして、再度、C
HCl13等のデポジッションガスを導入し、同図(e
)に示したように、レジストパターン1及び側壁4aの
上からA1層2上に薄膜5を等方向に形成する。そ【7
て、上述1.たスパッタエツチングにより、この薄膜5
をレジストパターン1の側方に形成された部分を残1.
て物理的に除去する。これにより、側壁4aの側部にA
、11層2のアンダカット部まで回り込んだ側壁5aを
得る(同図(f)参照)、このようにL2て、レジスト
パターン1の側方に側壁5aを形成した後、再びC,l
!2等のエツチングガスを導入し、エツチングガスの化
学的作用により、1/シストパターン〕、側壁4a及び
側壁5a@マスクにAf1層2のみを選択的、部分的か
つ等方向に除去する(同図(g)参照)。そ12て、上
述した薄膜の形成工程を経て、これを側壁に整形する工
程(同図(e)及び(f)参照)と、A1層の選択的・
部分的・等方向エッチング工程(同図(g)参照)とを
繰り返し行うことにより、1層2をテーパー状に除去す
ることができる。
First, a deposition gas such as CHCg3 is introduced to form a thin film 4 on the Al1 layer 2 from above the resist pattern 1, as shown in FIG. 2B. Next, a gas such as B1113 is introduced, and the thin film 4 is removed approximately perpendicularly to the surface of the A1 layer by sputter etching, which is a physical removal method. As a result, the thin film 4 is removed leaving the portions formed on the sides of the resist pattern 1.
The portion left on the side becomes the side wall 4a (see figure (C)). After the side wall 4a is formed in this way, 0 g
An etching gas such as No. 2 is introduced, and by the chemical action of the etching gas, only the A1 layer 2 is selectively and uniformly removed using the resist pattern 1 and the side wall 4a as a mask (see FIG. 2(d)). Moreover, this A9 layer 2 is removed partially in the thickness direction of this layer. And again, C
A deposition gas such as HCl13 is introduced, and the same figure (e
), a thin film 5 is formed equidirectionally on the A1 layer 2 from above the resist pattern 1 and the side wall 4a. So [7
1. This thin film 5 was formed by sputter etching.
1. Leave the portion formed on the side of resist pattern 1.
physically remove it. As a result, A is attached to the side of the side wall 4a.
After forming the side wall 5a on the side of the resist pattern 1 with L2 in this way, the side wall 5a that wraps around to the undercut part of layer 2 is obtained (see (f) in the same figure).
! Etching gas such as No. 2 is introduced, and by the chemical action of the etching gas, only the Af1 layer 2 is selectively, partially and uniformly removed from the sidewall 4a and sidewall 5a@mask (1/cyst pattern). (see (g)). 12. After the above-mentioned thin film formation step, there is a step of shaping the thin film into a side wall (see (e) and (f) in the same figure), and selectively forming the A1 layer.
By repeating the partial and isodirectional etching process (see (g) in the same figure), one layer 2 can be removed in a tapered shape.

【7かも、半導体基板3上に残されたA1層2側面のテ
ーパー角等の形状は、側壁となる薄膜のデボジッシヲン
1ノート、スパッタエツチングによる薄膜の、エツチン
グレート、Ag層のエラチンブレ−i−に応じて各工程
(薄膜形成工程、スバッタエッチング工程、A1層のエ
ツチング工程)の周期を適当に設定、変更することによ
り、所望のテーパー角、所望の形状とすることができる
[7] The shape of the taper angle of the side surface of the A1 layer 2 left on the semiconductor substrate 3 depends on the deposition rate of the thin film that will become the sidewall, the etching rate of the thin film formed by sputter etching, and the elastin brake of the Ag layer. By appropriately setting and changing the cycles of each process (thin film forming process, sputter etching process, and A1 layer etching process), a desired taper angle and desired shape can be obtained.

なお、上述1.た実施例の説明に用いた図では、本発明
の理解を容易にするため、薄膜や側壁の厚さ及び〕1回
のエツチングでAg層が除去される深さを誇張して大き
く示1.ている。このため、半導体基板3J二に残され
たAp9層2側は、凹凸となって表現されているが、繰
り返[−、行われる各工程の周期を十分に短くすること
により、A1層2側面を滑らかに仕上げることかり能で
ある。
In addition, the above 1. In the drawings used to explain the embodiments, the thickness of the thin film and sidewalls and the depth to which the Ag layer is removed in one etching process are exaggerated to make it easier to understand the present invention.1. ing. For this reason, the Ap9 layer 2 side left on the semiconductor substrate 3J2 is expressed as uneven, but by making the cycle of each process sufficiently short, the side surface of the A1 layer 2 It is a Noh performance that has a smooth finish.

〔発明の効果〕〔Effect of the invention〕

以」二説明したように、本発明によるエツチング方法に
よれば、被エツチング層の不必要部分が除去される工程
において、被エツチング層の不必要部分のみが選択的に
除去され、この工程中に側壁がエツチングされることが
ない。したがって、被エツチング層のテーパー角やその
断面形状の制御を容易に行なうことができる。また、か
かる形状制御を側壁の厚さを調整することにより行い得
るので、レジストパターンの形状による影響をほとんど
受けずに該形状制御が可能である。
As explained below, according to the etching method of the present invention, in the step of removing unnecessary portions of the layer to be etched, only the unnecessary portions of the layer to be etched are selectively removed. Side walls are not etched. Therefore, the taper angle and cross-sectional shape of the layer to be etched can be easily controlled. In addition, since such shape control can be performed by adjusting the thickness of the sidewall, the shape can be controlled almost unaffected by the shape of the resist pattern.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるエツチング方法の工程順に被エツ
チング層がどのようにエツチングされるかをその断面を
もって示した図である。 ]・・・レジストパターン、2・・・被エツチング層と
してのA1層、3・・半導体基板、4・・・薄膜、4a
・・・側壁、5・・・薄膜、5a・・・側壁。
FIG. 1 is a cross-sectional view showing how a layer to be etched is etched in the order of steps in the etching method according to the present invention. ]...Resist pattern, 2...A1 layer as a layer to be etched, 3...Semiconductor substrate, 4...Thin film, 4a
... Side wall, 5... Thin film, 5a... Side wall.

Claims (1)

【特許請求の範囲】  表面にマスクパターンが形成された被エッチング層の
不必要部分を選択的に除去するエッチング方法であって
、 前記被エッチング層の不必要部分だけを選択的、部分的
かつ等方的に除去する第1工程と、 前記マスクパターンの側方に前記第1工程で除去された
アンダカット部まで回り込んだ側壁を前記被エッチング
層と異なる材質で形成する第2工程とからなり、 前記第1工程及び第2工程を交互に繰り返し行うことを
特徴とするエッチング方法。
[Scope of Claim] An etching method for selectively removing unnecessary portions of a layer to be etched with a mask pattern formed on its surface, the method comprising: selectively, partially, etc. removing only the unnecessary portions of the layer to be etched; A second step includes forming a sidewall on the side of the mask pattern that wraps around to the undercut portion removed in the first step using a material different from that of the layer to be etched. . An etching method, characterized in that the first step and the second step are alternately and repeatedly carried out.
JP21468190A 1990-08-14 1990-08-14 Etching method Pending JPH0496327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21468190A JPH0496327A (en) 1990-08-14 1990-08-14 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21468190A JPH0496327A (en) 1990-08-14 1990-08-14 Etching method

Publications (1)

Publication Number Publication Date
JPH0496327A true JPH0496327A (en) 1992-03-27

Family

ID=16659822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21468190A Pending JPH0496327A (en) 1990-08-14 1990-08-14 Etching method

Country Status (1)

Country Link
JP (1) JPH0496327A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710066A (en) * 1994-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Method of forming fine patterns
JP2010506385A (en) * 2006-09-30 2010-02-25 エルジーマイクロン リミテッド Method for forming fine pattern using isotropic etching
US10760163B2 (en) * 2017-10-27 2020-09-01 Hyundai Motor Company Surface treatment method of aluminum for bonding different materials
CN112053948A (en) * 2020-08-31 2020-12-08 上海华虹宏力半导体制造有限公司 Process for oxidation film

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710066A (en) * 1994-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Method of forming fine patterns
JP2010506385A (en) * 2006-09-30 2010-02-25 エルジーマイクロン リミテッド Method for forming fine pattern using isotropic etching
US8486838B2 (en) 2006-09-30 2013-07-16 Lg Innotek Co., Ltd. Method for forming a fine pattern using isotropic etching
US9209108B2 (en) 2006-09-30 2015-12-08 Lg Innotek Co., Ltd. Method for forming a fine pattern using isotropic etching
US10760163B2 (en) * 2017-10-27 2020-09-01 Hyundai Motor Company Surface treatment method of aluminum for bonding different materials
CN112053948A (en) * 2020-08-31 2020-12-08 上海华虹宏力半导体制造有限公司 Process for oxidation film

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