JPH0496221A - Device and method for manufacturing semiconductor - Google Patents
Device and method for manufacturing semiconductorInfo
- Publication number
- JPH0496221A JPH0496221A JP2207441A JP20744190A JPH0496221A JP H0496221 A JPH0496221 A JP H0496221A JP 2207441 A JP2207441 A JP 2207441A JP 20744190 A JP20744190 A JP 20744190A JP H0496221 A JPH0496221 A JP H0496221A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- etching
- mounting table
- voltage source
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 236
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 235
- 239000002245 particle Substances 0.000 claims abstract description 27
- 238000009434 installation Methods 0.000 claims description 37
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 53
- 230000006378 damage Effects 0.000 abstract description 6
- 208000027418 Wounds and injury Diseases 0.000 abstract 1
- 208000014674 injury Diseases 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 14
- 238000001312 dry etching Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000010287 polarization Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は プラズマを用いて基板を加工する装置内で静
電気的な力を利用することによって半導体基板設置台に
固定された半導体基板を半導体基板設置台より解放する
ための半導体製造装置及びそれを用いた半導体装置の製
造方法に関するものであム
従来の技術
ＤＲＡＭやＳＲＡＭ等の半導体素子（表 高集積化の一
途をたどっており、それにともなって素子を製造するた
めの微細加工技術も急速な進歩を遂げてい′；６ｏ微細
加工技術の中でも特にドライエツチングの技術と種々の
膜を堆積するためのＣＶＤ技術はその基盤となるもので
あム
例えはドライエツチング装置で実際にドライエツチング
を行う際に１表 ドライエツチング装置内の半導体基板
設置台に半導体基板を固定しなければならな（■ この
半導体基板固定の方式にも石英製のリング状つエートで
固定するものや４′導体基板を帯電させて静電気的な力
によって固定するものなど様々な方式があム 前者（表
石英製のリング状つェートがドライエツチングにより
削られるためドライエツチング装置の汚染を引き起こす
のでよい方法ではな（も 後者は そのような欠点がな
いので、優れていると考えられる力（この方法では半導
体基板設置台より半導体基板を解放するときに被エツチ
ング膜に損傷を与えてしまうという欠点があム
第６図は 従来技術におけるドライエツチング装置の構
成図を示すものであも 基板処理室５０内部に 表面に
絶縁膜２で覆われた半導体基板設置台３を設（す、その
基板設置台３に半導体基板１が設置されたのちに直流電
圧源８が半導体基板設置台３に印加される。次にガスボ
ンベ１９からエツチングガスか導入されて高周波電源７
が半導体基板設置台３に印加されるとプラズマが発生し
てエツチングが始まると同時に半導体基板膜；ａ台３に
半導体基板１が静電気的に固定されも 高周波電源７を
半導体基板設置台３から切り放すとプラズマが消滅して
エツチングが終了すム
第７図（よ 従来技術で用いられている半導体基板設置
台に静電気的に半導体基板を固定及び解放する場合の原
理を説明するものであム 第７図（ａ）は エツチング
開始前の状態のエツチング装置を模式的に示したもので
あム エツチング室内の半導体基板設置台３（よ 絶縁
物２で被覆されており、この半導体基板設置台３には
高周波電源７と正の直流電圧源８が並列に接続されてい
もスイッチ５を閉じて正の直流電圧源８を半導体基板設
置台３に印加すると、半導体基板設置台３１上正電荷Ｑ
９が生じて正に帯電し それにともなって半導体基板ｌ
（よ わずかに誘電分極をする。それによって生じる静
電気力では半導体基板１を半導体基板設置台３上に固定
することはできな賎次に第７図（ｂ）に エツチング中
の状態を示す。エツチング（飄 エツチング室内をエツ
チングガスで満たしたのちに スイッチ４を閉じて高周
波電源７を半導体基板設置台３に印加することによって
、ブラスマ１０を発生させて行う。プラズマ１０が発生
してエツチングが開始されると、半導体基板ｌにプラズ
マ１０より電子１１が供給されるたべ 半導体基板設置
台３の正電荷Ｑ９に応じて負電荷Ｑ’１２が半導体基板
１に蓄積されムしたがって正電荷Ｑ９と負電荷Ｑ′ １
２との間にζよ 静電気力が生し ウェハ１は半導体基
板設置台３上に固定されも
第７図（ｃ）ζ友 エツチング終了後の状態を示す。ス
イッチ４を開いて高周波電源７を半導体基板設置台３か
ら取り除くと、放電が停止してプラズマｌＯが消失すム
そして次にスイッチ５を開いて正の直流電圧源８を半
導体基板設置台３から取り除き、スイッチ６を閉じて半
導体基板設置台３を接地すると、半導体基板設置台３上
の正電荷Ｑ９は半導体基板ｌの負電荷Ｑ′ １２のため
に正電荷量Ｑ′ １３にまで減少する力（零にすること
はできな（ｔ そのために半導体基板ｌ内の負電荷Ｑ゛
１２と半導体基板設置台３の正電荷Ｑ゛ １３との間
の静電気力は消失せず、半導体基板１を半導体基板設置
台３より解放することができな（を第７図（ｄ）ｉ、ｔ
、 半導体基板１に接地端子１７を接触させた状態を
示していも この隊 接地端子１７と半導体基板３との
間の電気回路の抵抗値と容量値によって正電荷Ｑ′ １
３と負電荷Ｑ１２の消失に要する時間は異なム この抵
抗値と容量値が大きくなれば消失に要する時間は長くな
り、正電荷Ｑ° １３と負電荷ＱＩ２が完全に消失しな
い間に半導体基板１を半導体基板設置台３から外部より
機械的な力を加えて解放しなければならな（Ｘｏ ま
た 半導体基板上の膜は半導体基板上に蓄積された電荷
を、その電荷が消失する経路のなす等価電気回路の容量
値で割った値に相当する損傷を受けることになる。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a semiconductor substrate mounting table in which a semiconductor substrate fixed to a semiconductor substrate mounting table is fixed to a semiconductor substrate mounting table by using electrostatic force in an apparatus that processes a substrate using plasma. Conventional technology Semiconductor devices such as DRAM and SRAM (see table) The microfabrication technology for manufacturing is also making rapid progress; among the 6o microfabrication technologies, dry etching technology and CVD technology for depositing various films are the basis of this. When actually performing dry etching with an etching device, it is necessary to fix the semiconductor substrate on the semiconductor substrate installation stand in the dry etching device (Table 1). There are various methods, such as those that are fixed, and those that charge the 4' conductor substrate and fix it using electrostatic force. This is not a good method because it causes damage (although the latter is considered superior because it does not have such drawbacks) (this method causes damage to the film to be etched when releasing the semiconductor substrate from the semiconductor substrate mounting table). Although FIG. 6 shows a configuration diagram of a conventional dry etching apparatus, there is a drawback that a semiconductor substrate mounting table 3 whose surface is covered with an insulating film 2 is installed inside the substrate processing chamber 50. After the semiconductor substrate 1 is installed on the substrate installation stand 3, a DC voltage source 8 is applied to the semiconductor substrate installation stand 3. Next, etching gas is introduced from the gas cylinder 19 and the high frequency power source 7
When is applied to the semiconductor substrate mounting table 3, plasma is generated and etching begins at the same time as the semiconductor substrate film; When released, the plasma disappears and etching ends. Figure 7 (This figure explains the principle of electrostatically fixing and releasing a semiconductor substrate from a semiconductor substrate mounting stand used in the prior art.) Figure 7(a) schematically shows the etching apparatus in a state before starting etching. teeth
Even if the high frequency power supply 7 and the positive DC voltage source 8 are connected in parallel, if the switch 5 is closed and the positive DC voltage source 8 is applied to the semiconductor substrate installation stand 3, a positive charge Q on the semiconductor substrate installation stand 31
9 is generated and becomes positively charged, and as a result, the semiconductor substrate l
(There is a slight dielectric polarization.The electrostatic force generated by this cannot fix the semiconductor substrate 1 on the semiconductor substrate mounting table 3.) Next, Figure 7(b) shows the state during etching.Etching (After filling the etching chamber with etching gas, the switch 4 is closed and the high frequency power source 7 is applied to the semiconductor substrate mounting table 3 to generate plasma 10. The plasma 10 is generated and etching is started. Then, electrons 11 are supplied from the plasma 10 to the semiconductor substrate l. Negative charges Q'12 are accumulated in the semiconductor substrate 1 in accordance with the positive charges Q9 of the semiconductor substrate mounting table 3. Therefore, the positive charges Q9 and the negative charges Q ' 1
An electrostatic force is generated between the wafer 2 and the wafer 1, and the wafer 1 is fixed on the semiconductor substrate mounting table 3. However, FIG. 7(c) shows the state after etching is completed. When the switch 4 is opened and the high-frequency power source 7 is removed from the semiconductor substrate installation stand 3, the discharge stops and the plasma IO disappears.Next, the switch 5 is opened and the positive DC voltage source 8 is removed from the semiconductor substrate installation stand 3. When the semiconductor substrate mounting table 3 is grounded by closing the switch 6, the positive charge Q9 on the semiconductor substrate mounting table 3 is reduced to the amount of positive charge Q'13 due to the negative charge Q'12 of the semiconductor substrate l. Therefore, the electrostatic force between the negative charge Q'12 in the semiconductor substrate l and the positive charge Q'13 on the semiconductor substrate mounting stand 3 does not disappear, and the semiconductor substrate 1 is It cannot be released from the board installation stand 3 (see Figure 7(d) i, t).
, even though the ground terminal 17 is shown in contact with the semiconductor substrate 1, a positive charge Q' 1 is generated due to the resistance and capacitance of the electric circuit between the ground terminal 17 and the semiconductor substrate 3.
The time required for the disappearance of the positive charge Q13 and the negative charge Q12 is different.The larger the resistance value and capacitance value, the longer the time required for the disappearance of the negative charge Q12. must be released from the semiconductor substrate mounting table 3 by applying mechanical force from the outside ( The damage will be equal to the value divided by the capacitance of the electrical circuit.
第８図（ａ）（よ 静電気的に半導体基板を固定及び解
放する場合の従来の技術のドライエツチング装置の動作
の流れ図を示すものである。この図について簡単に説明
すも
半導体基板を装置内の半導体基板設置台に搬送すム エ
ツチングガスをエツチング室に流ｔ 半導体基板設置台
に接続された正の直流電圧源回路によって半導体基板を
半導体基板設置台に静電気的に固定すも この状態で半
導体基板設置台に高周波電源を印加してエツチングを開
始すム エツチングが終了すると半導体基板設置台より
高周波電源を切り放し エツチング室へのエツチングガ
スの流入を止めも 正の直流電圧源を半導体基板設置台
より切り放し 半導体基板設置台と半導体基板を接地し
て半導体基板を半導体基板設置台から解放すも
以上のように構成された従来の半導体製造装置において
（よ 半導体製造装置内の半導体基板設置台に静電気的
に固定された半導体基板にドライエツチングを施した後
に半導体基板設置台と半導体基板を接地することにより
半導体基板設置台及び半導体基板の電荷を減少させるこ
とによって半導体基板設置台より半導体基板を解放して
いる。FIG. 8(a) shows a flowchart of the operation of a conventional dry etching apparatus when a semiconductor substrate is electrostatically fixed and released. The etching gas is flowed into the etching chamber to be transported to the semiconductor substrate installation stand.The semiconductor substrate is electrostatically fixed to the semiconductor substrate installation stand by a positive DC voltage source circuit connected to the semiconductor substrate installation stand. Etching is started by applying high frequency power to the substrate mounting table.When etching is completed, the high frequency power is cut off from the semiconductor substrate mounting table.The flow of etching gas into the etching chamber is stopped.A positive DC voltage source is applied from the semiconductor substrate mounting table. In conventional semiconductor manufacturing equipment configured as described above, the semiconductor substrate installation stand and the semiconductor substrate are grounded and the semiconductor substrate is released from the semiconductor substrate installation stand. After performing dry etching on the semiconductor substrate fixed to the semiconductor substrate, the semiconductor substrate mounting table and the semiconductor substrate are grounded to reduce the electric charges on the semiconductor substrate mounting table and the semiconductor substrate, thereby releasing the semiconductor substrate from the semiconductor substrate mounting table. There is.
発明が解決しようとする課題
しかしなから前記のような構成では 半導体基板に存在
する電荷を半導体基板の裏面から抜き取ることによって
消失させているので、半導体基板上に製造されている種
々の膜に損傷を与えてしまうた敦 素子製造上好ましく
更に半導体基板設置台及び半導体基板に存在する電荷を
完全に消失せしめて容易に半導体基板を半導体基板設置
台より解放することは不可能であるという問題点を有し
ていに
本発明はかかる点に鑑ぺ 半導体基板設置台に静電気的
に固定された半導体基板を容易に しかも半導体基板上
の膜に損傷を与えずに解放するための半導体製造装置と
半導体装置の製造方法を提供することを目的とすム
課題を解決するための手段
本発明（よ プラズマを用いた基板処理室内の半導体基
板設置台に 静電気的に固定された半導体基板に存在す
る電荷を荷電粒子源より発生させた荷電粒子を半導体基
板に照射することにより、または半導体基板を固定する
ために用いた直流電圧源とは極性の異なる直流電圧源を
半導体基板設置台に印加することによって消失せしめて
、容易にかつ膜に損傷を与えることなく半導体基板を半
導体基板設置台より解放することを特徴とするものであ
る。Problems to be Solved by the Invention However, in the above-described configuration, the electric charge existing in the semiconductor substrate is removed by extracting it from the back side of the semiconductor substrate, which may cause damage to various films manufactured on the semiconductor substrate. It is preferable in terms of device manufacturing that it is impossible to completely eliminate the charge existing in the semiconductor substrate mounting table and the semiconductor substrate and easily release the semiconductor substrate from the semiconductor substrate mounting table. In particular, the present invention has been made in view of this point.A semiconductor manufacturing apparatus and a semiconductor device for easily releasing a semiconductor substrate electrostatically fixed to a semiconductor substrate mounting stand without damaging a film on the semiconductor substrate. The present invention aims to provide a method for manufacturing a semiconductor substrate that is electrostatically fixed to a semiconductor substrate mounting table in a substrate processing chamber using plasma. Disappear by irradiating the semiconductor substrate with charged particles generated by a particle source, or by applying a DC voltage source with a polarity different from the DC voltage source used to fix the semiconductor substrate to the semiconductor substrate mounting table. Accordingly, the semiconductor substrate can be easily released from the semiconductor substrate mounting stand without damaging the film.
作用
本発明は前記した構成により、半導体基板設置台を接地
したのちに荷電粒子源より荷電粒子を半導体基板設置台
に静電気的に固定された半導体基板に照射することによ
って、またはエツチング終了後半導体基板設置台を接地
する代わりに半導体基板を固定するために用いた直流電
圧源とは極性の異なる直流電圧源を半導体基板設置台に
印加することによって半導体基板内の電荷が消失するの
で、半導体基板を半導体基板設置台に固定している静電
気力（よ 消失することになり、半導体基板を半導体基
板設置台より容易にかつ半導体基板上の膜に損傷に与え
ることなく解放することができる。According to the above-described structure, the present invention can be applied by irradiating charged particles from a charged particle source to the semiconductor substrate electrostatically fixed to the semiconductor substrate mounting table after the semiconductor substrate mounting table is grounded, or by irradiating the semiconductor substrate after etching is completed. Instead of grounding the mounting base, by applying a DC voltage source with a polarity different from the DC voltage source used to fix the semiconductor substrate to the semiconductor substrate mounting base, the charge in the semiconductor substrate disappears, and the semiconductor substrate can be fixed. The electrostatic force that is fixed to the semiconductor substrate mounting table is dissipated, and the semiconductor substrate can be released from the semiconductor substrate mounting table more easily and without damaging the film on the semiconductor substrate.
実施例
第１図（ａ）Ｊｔ 本発明の第１の実施例における半
導体製造装置の構成図であム 本実施例では本発明をＲ
ＩＥ方式のドライエツチング装置に適用した例であム
基板処理室５０内部に表面に絶縁膜２を有する半導体基
板設置台３を設け、その基板設置台３上に半導体基板ｌ
を設置し 半導体基板設置台３に直流電圧源８と高周波
電源７を印加して、ガスボンベ１９からエツチングガス
を供給することによってプラズマを発生させてエツチン
グすると同時に半導体基板ｌを半導体基板設置台３に固
定すムエッチングが終了すると半導体基板設置台３から
直流電圧源８と高周波電源７を切り放し エツチング室
内に設置された荷電粒子発生装置１４から荷電粒子を半
導体基板１に照射することによって半導体基板】及び半
導体装置基板３の電荷を消失させて半導体基板ｌを半導
体基板設置台から解放する。Embodiment FIG. 1 (a) Jt is a configuration diagram of a semiconductor manufacturing apparatus in a first embodiment of the present invention.
This is an example applied to an IE type dry etching apparatus. A semiconductor substrate mounting table 3 having an insulating film 2 on the surface is provided inside the substrate processing chamber 50, and a semiconductor substrate l is placed on the substrate mounting table 3.
By applying a DC voltage source 8 and a high frequency power source 7 to the semiconductor substrate mounting table 3 and supplying etching gas from the gas cylinder 19, plasma is generated and etching is performed, and at the same time, the semiconductor substrate l is placed on the semiconductor substrate mounting table 3. When the fixed etching is completed, the DC voltage source 8 and high frequency power source 7 are disconnected from the semiconductor substrate installation stand 3, and the semiconductor substrate 1 is irradiated with charged particles from the charged particle generator 14 installed in the etching chamber. The charges on the semiconductor device substrate 3 are dissipated and the semiconductor substrate 1 is released from the semiconductor substrate mounting table.
第１図（ｂ）は荷電粒子発生装置１４かエツチング室外
に設置されていることだけ力（第１図（ａ）と異なる。FIG. 1(b) differs from FIG. 1(a) in that the charged particle generator 14 is installed outside the etching chamber.
第２図は本発明の第１の実施例における半導体製造装置
の半導体基板設置台に静電気的に半導体基板を固定およ
び解放するための原理を示すものであも
第２図（ａ）において、エツチング開始前の状態を示す
。スイッチ５を閉じて半導体基板設置台３に正の直流電
圧源８を印加して半導体基板設置台３に正の電荷Ｑ９を
誘起すム この電荷Ｑ９に応じて半導体基板１に誘電分
極による電荷が生じる力（この電荷だけでは半導体基板
１を半導体基板設置台３に固定するには不十分である。FIG. 2 shows the principle of electrostatically fixing and releasing a semiconductor substrate on a semiconductor substrate mounting table of a semiconductor manufacturing apparatus in the first embodiment of the present invention. Indicates the state before starting. Close the switch 5 and apply a positive DC voltage source 8 to the semiconductor substrate mounting base 3 to induce a positive charge Q9 on the semiconductor substrate mounting base 3.According to this charge Q9, a charge due to dielectric polarization is generated in the semiconductor substrate 1. The generated force (this charge alone is insufficient to fix the semiconductor substrate 1 to the semiconductor substrate mounting base 3).
次に第２図（ｂ）において、スイッチ４を閉じて高周波
電源７を半導体基板設置台３に印加してブラスマｌＯを
発生させてエツチングを開始する。Next, in FIG. 2(b), the switch 4 is closed and the high frequency power source 7 is applied to the semiconductor substrate mounting table 3 to generate plasma lO and start etching.
プラズマ１０より電子１１が半導体基板１に入射して半
導体基板ｌに（戴 負電荷Ｑ’１２が蓄積されて正電荷
Ｑ９との間に静電気力が生じも この静電気力によって
半導体基板Ｉ Ｉ−Ｌ 半導体基板設置台３上に固定
される。Electrons 11 are incident on the semiconductor substrate 1 from the plasma 10 and the negative charge Q'12 is accumulated on the semiconductor substrate 1, and an electrostatic force is generated between it and the positive charge Q9. It is fixed on the semiconductor substrate installation stand 3.
次に第２図（ｃ）にエツチング終了後の状態を示す。エ
ツチングの終了時に（よ スイッチ４は開き高周波電源
７は印加されないためにプラズマζよ消失す４ これに
よってプラズマ１０からの電子１１の流入はなくなａ
この状態でスイッチ５を開きスイッチ６を閉じると、半
導体基板設置台３の正電荷Ｑ ９ Ｌｔ、 半導体基
板に蓄積された負電荷Ｑ° １２と同じ絶対値であるが
極性の異なる正電荷Ｑ’１３にまで減少する力（零には
ならな（℃そこで第２図（ｄ）に示すようにエツチング
室内または室外に設けられたイオン源１４より発生する
希ガスや不活性ガスなどの荷電粒子１５を半導体基板１
に照射して半導体基板ｌ上の負電荷Ｑ′ １２を消失さ
せる。この負電荷Ｑ゛ １２が消失すると同時に半導体
基板設置台３の正電荷Ｑ’ １３も消失する。しかっ
て、負電荷Ｑ’１２と正電荷Ｑ’１３の間に生じていた
静電気力も消失して半導体基板設置台３に固定された半
導体基板１を容易に しかも半導体基板３上の膜に損傷
を与えることなく解放することができる。Next, FIG. 2(c) shows the state after etching is completed. At the end of etching (Y), the switch 4 is opened and the high-frequency power source 7 is not applied, so the plasma ζ disappears. As a result, the electrons 11 from the plasma 10 no longer flow
When the switch 5 is opened and the switch 6 is closed in this state, the positive charge Q 9 Lt on the semiconductor substrate installation stand 3 and the positive charge Q' having the same absolute value as the negative charge Q° 12 accumulated on the semiconductor substrate but with a different polarity. As shown in FIG. 2(d), the charged particles 15 of rare gas or inert gas generated from the ion source 14 installed in or outside the etching chamber are The semiconductor substrate 1
The negative charge Q' 12 on the semiconductor substrate l is irradiated with the negative charge Q'12. At the same time as this negative charge Q'12 disappears, the positive charge Q'13 on the semiconductor substrate mounting table 3 also disappears. Therefore, the electrostatic force generated between the negative charge Q'12 and the positive charge Q'13 also disappears, and the semiconductor substrate 1 fixed on the semiconductor substrate mounting stand 3 is easily moved, and the film on the semiconductor substrate 3 is not damaged. It can be released without giving away.
第８図（ｂ）に この実施例の装置動作の流れ図を示す
。この図について簡単に説明する。半導体基板Ｉをエツ
チング室内の半導体基板設置台３に搬送し 設置すム
エツチングガスをエツチング室に流す。半導体基板設置
台３に正の直流電圧８を印加すム この状態で半導体基
板設置台３に高周波電源７を印加してエツチングを開始
すムエッチングが開始されると半導体基板１は半導体基
板設置台３に静電気的に固定されも エツチングが終了
すると半導体基板設置台３より高周波電源７を切り放し
エツチング室へのエツチングガスの流入を止めム 正
の直流電圧源８を半導体基板設置台３より切り放し 半
導体基板設置台３を接地し 半導体基板１に荷電粒子を
照射して、半導体基板上の電荷を消失させて半導体基板
１を半導体基板設置台３から解放すも
第３図に荷電粒子発生装置１４力丈 半導体製造装置内
に設置されている場合の実施例を示す。第３図（ａ）３
表 ドライエツチング終了後に荷電粒子源１４と接続さ
れた円筒状のノズル３０が半導体基板上にまで移動して
半導体基板１に荷電粒子を照射する装置例であム
第３図（ｂ）ｌ；ｔ、 ドライエツチング終了後に荷
電粒子源１４と接続された円盤状の荷電粒子照射板３１
か半導体基板１の近くにまで移動して、半導体基板１に
荷電粒子を照射する装置例であム第３図（ｃ）ｌ；Ｌ
ドライエツチング終了後に荷電粒子源１４と接続され
た円環状の荷電粒子照射ノズル３２力（半導体基板上に
移動して荷電粒子を照射する装置例である。FIG. 8(b) shows a flow chart of the device operation of this embodiment. This figure will be briefly explained. Transfer the semiconductor substrate I to the semiconductor substrate installation stand 3 in the etching chamber and install it.
Flow the etching gas into the etching chamber. A positive DC voltage 8 is applied to the semiconductor substrate mounting table 3. In this state, a high frequency power source 7 is applied to the semiconductor substrate mounting table 3 to start etching. When etching is started, the semiconductor substrate 1 is When etching is completed, the high frequency power source 7 is disconnected from the semiconductor substrate mounting table 3 to stop the etching gas from flowing into the etching chamber, and the positive DC voltage source 8 is disconnected from the semiconductor substrate mounting table 3. The installation stand 3 is grounded and the semiconductor substrate 1 is irradiated with charged particles to eliminate the charge on the semiconductor substrate and release the semiconductor substrate 1 from the semiconductor substrate installation stand 3. An example will be shown in which the device is installed in a semiconductor manufacturing device. Figure 3(a)3
Table 3 shows an example of an apparatus in which a cylindrical nozzle 30 connected to a charged particle source 14 moves onto the semiconductor substrate and irradiates the semiconductor substrate 1 with charged particles after dry etching is completed. , a disk-shaped charged particle irradiation plate 31 connected to the charged particle source 14 after dry etching is completed;
This is an example of a device that moves close to the semiconductor substrate 1 and irradiates the semiconductor substrate 1 with charged particles.
After completion of dry etching, an annular charged particle irradiation nozzle 32 is connected to the charged particle source 14 (this is an example of a device that moves onto the semiconductor substrate and irradiates the charged particles with it).
以上のようにこの実施例によれば 半導体装置内外に荷
電粒子発生装置１４を設けることにより、半導体基板設
置台の半導体基板に半導体基板内の電荷と極性の異なる
荷電粒子を照射して半導体基板及び半導体基板設置台の
電荷を消失させることによって静電気力で半導体基板設
置台に固定された半導体基板を容易へ しかも半導体基
板上の膜や素子に損傷を与えることなく解放することか
でき る。As described above, according to this embodiment, by providing the charged particle generator 14 inside and outside the semiconductor device, the semiconductor substrate on the semiconductor substrate mounting table is irradiated with charged particles having a polarity different from the charge in the semiconductor substrate. By dissipating the charge on the semiconductor substrate mounting table, the semiconductor substrate fixed to the semiconductor substrate mounting table by electrostatic force can be easily released without damaging the films or elements on the semiconductor substrate.
第４図（友 本発明の第２の実施例における半導体製造
装置の構成図である。本実施例もまた本発明をＲＩＥ方
式のドライエッヂング装置に適用していム 表面に絶縁
膜２を有する半導体基板設置台３上に半導体基板１を設
置し 半導体基板設置台３に直流電圧源８と高周波電源
７を印加して、ガスボンベ１９からエツチングガスを供
給することによってプラズマを発生させてエツチングす
ると同時に半導体基板１を半導体基板設置台３に固定す
ム エツチングが終了すると半導体基板設置台３から直
流電圧源８と高周波電源７を切り放し半導体基板設置台
３に負の直流電圧源１６を印加して半導体基板設置台３
に存在する電荷を引き抜く。従って、静電気力は消失し
て、半導体基板１は半導体基板設置台３から開放されも
第５図は本発明の第２の実施例における半導体製造装置
の半導体基板設置台に静電気的に固定せれた半導体基板
を解放するための原理を図に示すものである。第５図（
ａ）（表 エツチング開始前の状態を示すものである。FIG. 4 is a configuration diagram of a semiconductor manufacturing apparatus according to a second embodiment of the present invention. This embodiment also applies the present invention to an RIE type dry etching apparatus. A semiconductor substrate 1 is placed on a substrate installation stand 3, a DC voltage source 8 and a high frequency power source 7 are applied to the semiconductor substrate installation stand 3, and an etching gas is supplied from a gas cylinder 19 to generate plasma and simultaneously etch the semiconductor. When the etching of fixing the substrate 1 to the semiconductor substrate mounting table 3 is completed, the DC voltage source 8 and the high frequency power source 7 are disconnected from the semiconductor substrate mounting table 3, and the negative DC voltage source 16 is applied to the semiconductor substrate mounting table 3, and the semiconductor substrate is fixed to the semiconductor substrate mounting table 3. Installation stand 3
extracts the charge present in Therefore, although the electrostatic force disappears and the semiconductor substrate 1 is released from the semiconductor substrate mounting stand 3, FIG. The principle for releasing the semiconductor substrate is illustrated in the figure. Figure 5 (
a) (Table shows the state before the start of etching.
スイッチ５を閉じて半導体基板設置台３に正の直流電圧
源８を印加して半導体基板設置台３に正の電荷の９を誘
起する。The switch 5 is closed and a positive DC voltage source 8 is applied to the semiconductor substrate mounting table 3 to induce a positive charge 9 in the semiconductor substrate mounting table 3.
この電荷Ｑ９に応じて応じて半導体基板１に誘電分極に
よる電荷が生じる力交 半導体基板１を半導体基板設置
台３に固定するには不十分であ４次に第５図（ｂ）にお
いて、スイッチ４を閉じて高周波電源７を半導体基板設
置台３に印加してプラズマ１０を発生させてエツチング
を開始す４プラズマ１０より電子１１が半導体基板１に
入射して半導体基板１には 負電荷Ｑ゛ １２が蓄積さ
れて正電荷Ｑ９との間に静電気力が生じる。この静電気
力によって半導体基板ｌは 半導体基板設置台３上に固
定されも
次に第５図（ｃ）にエツチング終了後の状態を示す。エ
ツチングの終了時に１ｉ、スイッチ４は開き高周波電源
７は半導体基板設置台３に印加されなくなるためにプラ
ズマ１０は消失する。これによってプラズマ１０からの
電子１１の流入はなくなる。この状態でスイッチ５を開
き正の直流電圧源８を半導体基板設置台３より切り放し
スイッチ６を閉じると半導体基板設置台３には負の直
流電圧源１６が印加されて半導体基板設置台３の正電荷
Ｑ９は消失して、同時に半導体基板ｌに蓄積された負電
荷Ｑ° １２も消失すム ただしここで負の直流電圧源
の電圧１表 正の直流電圧源の電圧よりも大きいものを
用いる。したがって、半導体基板１の負電荷Ｑ” １２
と半導体基板設置台３の正電荷Ｑ９との間に生じていた
静電気力は消失して、半導体基板１を半導体基板設置台
３より容易に解放することができも この方法で（よ
半導体基板上の膜にバイアス電圧を与えていないので、
半導体基板上の膜に損傷を与えずに半導体基板ｌを半導
体基板設置台３から解放することができる。The force exchange that generates a charge due to dielectric polarization on the semiconductor substrate 1 in accordance with this charge Q9 is insufficient to fix the semiconductor substrate 1 to the semiconductor substrate mounting stand 3. Next, in FIG. 4 is closed and the high-frequency power supply 7 is applied to the semiconductor substrate mounting table 3 to generate plasma 10 and start etching. 4 Electrons 11 are incident on the semiconductor substrate 1 from the plasma 10, and the semiconductor substrate 1 is charged with a negative charge Q. 12 is accumulated and an electrostatic force is generated between it and the positive charge Q9. The semiconductor substrate 1 is fixed on the semiconductor substrate mounting table 3 by this electrostatic force, and the state after etching is shown in FIG. 5(c). At the end of etching 1i, the switch 4 is opened and the high frequency power source 7 is no longer applied to the semiconductor substrate mounting table 3, so that the plasma 10 disappears. This eliminates the inflow of electrons 11 from plasma 10. In this state, the switch 5 is opened to disconnect the positive DC voltage source 8 from the semiconductor substrate installation stand 3. When the switch 6 is closed, the negative DC voltage source 16 is applied to the semiconductor substrate installation stand 3, and the positive DC voltage source 8 is disconnected from the semiconductor substrate installation stand 3. The charge Q9 disappears, and at the same time the negative charge Q°12 accumulated in the semiconductor substrate l also disappears.However, here, a voltage of the negative DC voltage source that is larger than the voltage of the positive DC voltage source is used. Therefore, the negative charge Q” 12 of the semiconductor substrate 1
The electrostatic force generated between Q9 and the positive charge Q9 on the semiconductor substrate mounting table 3 disappears, and the semiconductor substrate 1 can be easily released from the semiconductor substrate mounting table 3.
Since no bias voltage is applied to the film on the semiconductor substrate,
The semiconductor substrate l can be released from the semiconductor substrate mounting table 3 without damaging the film on the semiconductor substrate.
第８図（ｃ）に この実施例の装置動作の流れ図を示す
。この図について簡単に説明する。半導体基板を装置内
の半導体基板設置台に搬送すムエッチングガスをエツチ
ング室に流す。半導体基板設置台に接続された正の直流
電圧源回路によって半導体基板を半導体基板設置台に静
電気的に固定する。この状態で半導体基板゛設置台に高
周波電源を印加してエツチングを開始する。エツチング
が終了すると半導体基板設置台より高周波電源を切り放
し エツチング室へのエツチングガスの流人を止めも
正の直流電圧源を半導体基板設置台より切り放し 半導
体基板設置台をに正の直流電圧源より大きな電圧を持つ
負の直流電圧源を印加し 半導体基板設置台の電荷を消
失させて半導体基板を半導体基板設置台から解放する。FIG. 8(c) shows a flow chart of the device operation of this embodiment. This figure will be briefly explained. Etching gas is flowed into the etching chamber to transport the semiconductor substrate to the semiconductor substrate installation stand within the apparatus. The semiconductor substrate is electrostatically fixed to the semiconductor substrate mounting table by a positive DC voltage source circuit connected to the semiconductor substrate mounting table. In this state, a high frequency power source is applied to the semiconductor substrate mounting table to start etching. When etching is completed, the high frequency power source is cut off from the semiconductor substrate installation stand to stop the etching gas from flowing into the etching chamber.
The positive DC voltage source is disconnected from the semiconductor substrate mounting base, and a negative DC voltage source with a voltage higher than the positive DC voltage source is applied to the semiconductor substrate mounting base, thereby dissipating the charge on the semiconductor substrate mounting base and converting the semiconductor substrate into a semiconductor. Release from the board installation stand.
以上のようにこの実施例によれば 半導体装置内に半導
体基板を半導体基板設置台に固定するための正の直流電
圧源より大きな電圧を持つ負の直流電圧源を設けること
により、半導体基板設置台の正電荷を消失させることが
できるたぬ 静電気力で半導体基板設置台に固定された
半導体基板を容易に半導体基板上の膜に損傷を与えるこ
となく解放することができる。As described above, according to this embodiment, by providing a negative DC voltage source having a higher voltage than the positive DC voltage source for fixing the semiconductor substrate to the semiconductor substrate mounting table in the semiconductor device, the semiconductor substrate mounting table can be fixed. A semiconductor substrate fixed to a semiconductor substrate mounting table by electrostatic force can be easily released without damaging the film on the semiconductor substrate.
な耘 以上の説明で高周波電源と正の直流電圧源の半導
体基板設置台への印加及び切り離しの順序を前後させて
も得られる効果（表 同じである。In the above explanation, the same effect can be obtained even if the order of applying and disconnecting the high frequency power source and the positive DC voltage source to the semiconductor substrate mounting table is changed.
また本実施例では本発明をＲＩＥ方式のドライエツチン
グ装置に適用した力（ＥＣＲ方式等のドライエツチング
装置 プラズマＣＶＤ装置 プラズマスパッタ装置等の
プラズマを用いて基板を加エする装置であれば適用可能
であ本
発明の詳細
な説明したよう＋、＝ 本発明によれば 半導体製造
装置内で静電気的に半導体基板設置台に固定された半導
体基板を容易に しかも半導体基板上に形成した膜や素
子に損傷を与えることなく半導体基板設置台より解放す
ることができ、その実用的効果は犬き（℃In addition, in this embodiment, the present invention is applied to an RIE type dry etching apparatus (it can be applied to any apparatus that processes a substrate using plasma, such as an ECR type dry etching apparatus, a plasma CVD apparatus, or a plasma sputtering apparatus). As explained in detail about the present invention, +, = According to the present invention, it is possible to easily fix a semiconductor substrate electrostatically to a semiconductor substrate mounting table in a semiconductor manufacturing apparatus, and also prevent damage to films and elements formed on the semiconductor substrate. It can be released from the semiconductor substrate mounting stand without giving any
第１図は本発明の第１の実施例における装置構成は 第
２図は第１の実施例における半導体基板の固定と解放の
原理説明医 第３図は荷電粒子源の例を示す構成は 第
４図は第２の実施例における装置構成医 第５図は第２
の実施例における半導体基板の固定と解放の原理医 第
６図は従来の装置の構成医 第７図は従来の装置におけ
る半導体基板の固定と解放の原理医 第８図は従来 実
施例１、実施例２の装置動作流れ図である。
ｌ・・・半導体基板、 ２・・・絶縁＃扱 ３・・・半
導体基板設置台、 ４，５．６・・・スイッチ、 ７・
・・高周波重縁８、・・正の直流電圧＃ ９・・・正電
荷Ｑ、１０・・・ブラズス １１・・・電子、 １２・
・・負電荷Ｑ’１３・・・正電荷Ｑ゛ １４・・・荷
電粒子発生装置 １５・・・荷電粒子、 １６・・・負
の直流電圧＃ ５０・・・基板処理家代理人の氏名 弁
理士 粟野重孝 はか１名第 １ 図
第 ２ 図
（ＣＬ）工・す子ンフ閉杓前
（ｂ）エーノチンク中
第
図
（Ｃフエ・ン千ンク軒了１＆
（（Ｌノ
ウェハの′Ｍ族
第
第
図
（ａ）エツチンクＭ妨約
（ｂ）
工・ンテンク中
第
図
ＣＣ）エリチンフ於了１＆
第
図
第
図
（Ｃ）工・ソチンク終了１々
！
（ｄ）
ウェハの解放
第
図
（ａｒ１７チンフ聞妨約
第
図
（ａ）
ｔｂ＋
従来す法
貨屈 １列ノ
（Ｃ１
ｅ−）％Ｙシ・ノ２FIG. 1 shows the configuration of the device in the first embodiment of the present invention. FIG. 2 shows the principle of fixing and releasing the semiconductor substrate in the first embodiment. FIG. 3 shows the configuration of the charged particle source. Figure 4 shows the device configuration doctor in the second embodiment. Figure 5 shows the device configuration doctor in the second embodiment.
Fig. 6 shows the principle of fixing and releasing the semiconductor substrate in the conventional device. Fig. 7 shows the principle of fixing and releasing the semiconductor substrate in the conventional device. Fig. 8 shows the principle of fixing and releasing the semiconductor substrate in the conventional device. 12 is a flowchart of device operation in Example 2. l...Semiconductor substrate, 2...Insulation # handling 3...Semiconductor board installation stand, 4,5.6...Switch, 7.
...High frequency double edge 8, ...Positive DC voltage #9...Positive charge Q, 10...Blasus 11...Electron, 12.
...Negative charge Q'13...Positive charge Q゛ 14...Charged particle generator 15...Charged particles 16...Negative DC voltage #50...Name of substrate processor agent Patent attorney Shigetaka Awano Haka 1 person Figure 1 Figure 2 (CL) Before the closing of the engineering/suko nfu (b) Eno chinku middle diagram (C Hue nsenku eaves ryo 1 & ((L no waha's M group Figure (a) Etching M interruption (b) During construction and maintenance Figure CC) Elimination completed 1 & Figure (C) Construction and maintenance completed 1! (d) Wafer release diagram (AR17 Discontinuation diagram (a) tb+ Conventional legal tender 1st column (C1 e-)%Yshino2
Claims (3)
内部に設けられ表面に絶縁膜を有する半導体基板設置台
と、この設置台に接続された高周波電源と、前記設置台
に接続された直流電圧源と、前記設置台に隣接する荷電
粒子発生装置とを具備する半導体製造装置。(1) A substrate processing chamber using plasma, a semiconductor substrate installation stand provided inside the substrate processing chamber and having an insulating film on the surface, a high frequency power supply connected to this installation stand, and a high frequency power source connected to the installation stand. A semiconductor manufacturing apparatus comprising a DC voltage source and a charged particle generator adjacent to the installation stand.
、この半導体基板設置台に接続された直流電圧源を印加
する工程と、プラズマを発生させる工程と、前記半導体
基板に荷電粒子を照射する工程とを含むことを特徴とす
る半導体装置の製造方法。(2) A step of installing a semiconductor substrate on a semiconductor substrate installation stand, a step of applying a DC voltage source connected to the semiconductor substrate installation stand, a step of generating plasma, and a step of irradiating the semiconductor substrate with charged particles. A method for manufacturing a semiconductor device, comprising the steps of:
、この半導体基板設置台に接続された直流電圧源を印加
する工程と、プラズマを発生させる工程と、前記直流電
圧源とは極性の異なる直流電圧源を半導体基板設置台に
印加する工程を含むことを特徴とする半導体装置の製造
方法。(3) A step of installing a semiconductor substrate on a semiconductor substrate installation stand, a step of applying a DC voltage source connected to the semiconductor substrate installation stand, and a step of generating plasma, the polarity of which is different from that of the DC voltage source. A method for manufacturing a semiconductor device, comprising the step of applying a DC voltage source to a semiconductor substrate mounting table.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20744190A JP2507155B2 (en) | 1990-08-03 | 1990-08-03 | Semiconductor manufacturing apparatus and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20744190A JP2507155B2 (en) | 1990-08-03 | 1990-08-03 | Semiconductor manufacturing apparatus and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0496221A true JPH0496221A (en) | 1992-03-27 |
| JP2507155B2 JP2507155B2 (en) | 1996-06-12 |
Family
ID=16539823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20744190A Expired - Fee Related JP2507155B2 (en) | 1990-08-03 | 1990-08-03 | Semiconductor manufacturing apparatus and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2507155B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303265A (en) * | 2005-04-22 | 2006-11-02 | Dainippon Printing Co Ltd | Film forming system and method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53116076A (en) * | 1977-03-22 | 1978-10-11 | Hitachi Ltd | Plasma processing method and its unit |
| JPS5923415U (en) * | 1982-08-05 | 1984-02-14 | 日本フルハ−フ株式会社 | Waterproof covering device for the center of the roof of a fully-opening side truck |
| JPS5967629A (en) * | 1982-10-12 | 1984-04-17 | Nippon Kogaku Kk <Nikon> | Electrostatic attracter |
| JPS62255039A (en) * | 1986-11-21 | 1987-11-06 | Kureha Chem Ind Co Ltd | Receasing method of attracted body from electrostatic attracting device |
| JPH02130915A (en) * | 1988-11-11 | 1990-05-18 | Anelva Corp | Plasma processing equipment |
| JPH033251A (en) * | 1989-05-30 | 1991-01-09 | Sumitomo Metal Ind Ltd | Sample holder |
| JPH03236255A (en) * | 1990-02-14 | 1991-10-22 | Hitachi Ltd | Method for removing charge from electrostatic chuck |
| JPH0451542A (en) * | 1990-06-19 | 1992-02-20 | Fujitsu Ltd | Electrostatically attracting method |
-
1990
- 1990-08-03 JP JP20744190A patent/JP2507155B2/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53116076A (en) * | 1977-03-22 | 1978-10-11 | Hitachi Ltd | Plasma processing method and its unit |
| JPS5923415U (en) * | 1982-08-05 | 1984-02-14 | 日本フルハ−フ株式会社 | Waterproof covering device for the center of the roof of a fully-opening side truck |
| JPS5967629A (en) * | 1982-10-12 | 1984-04-17 | Nippon Kogaku Kk <Nikon> | Electrostatic attracter |
| JPS62255039A (en) * | 1986-11-21 | 1987-11-06 | Kureha Chem Ind Co Ltd | Receasing method of attracted body from electrostatic attracting device |
| JPH02130915A (en) * | 1988-11-11 | 1990-05-18 | Anelva Corp | Plasma processing equipment |
| JPH033251A (en) * | 1989-05-30 | 1991-01-09 | Sumitomo Metal Ind Ltd | Sample holder |
| JPH03236255A (en) * | 1990-02-14 | 1991-10-22 | Hitachi Ltd | Method for removing charge from electrostatic chuck |
| JPH0451542A (en) * | 1990-06-19 | 1992-02-20 | Fujitsu Ltd | Electrostatically attracting method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303265A (en) * | 2005-04-22 | 2006-11-02 | Dainippon Printing Co Ltd | Film forming system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2507155B2 (en) | 1996-06-12 |
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| LAPS | Cancellation because of no payment of annual fees |