JPH0494177A - Josephson junction element and its production - Google Patents

Abstract

PURPOSE:To microminiaturize an element while maintaining reliability by directly providing a wiring layer on an upper electrode top plane exposed on an insulating layer which has a flat top plane. CONSTITUTION:Josephson junction structure, which has the lamination of a super conductive bottom electrode 2, an insulating barrier layer 3 and a super conductive top electrode 4 in such order on a substrate 1, is formed. An insulating layer 11 is laminated on the substrate, on which the Josephson junction structure is formed, by bias sputtering method, and the Josephson junction structure is buried in the insulating layer 11 whose top plane 12 is flat. The insulating layer 11 is etched back until the top plane 13 of the upper electrode 4 of the buried Josephson junction structure is exposed. At such step, the top plane 13 of the upper electrode 4 and the top plane 12' of the insulating layer 11 are flattened. A wiring layer 14 are formed on the exposed upper electrode top plane 13.

Description

[Detailed Description of the Invention] [Summary] Regarding a Josephson junction element and a manufacturing method thereof, the present invention aims to provide a Josephson junction element and a manufacturing method thereof that enable miniaturization while ensuring reliability. In the Josephson junction device of the present invention, a Josephson junction in which a lower electrode of a superconductor, a barrier layer of an insulator, and an upper electrode of a superconductor are laminated in this order is formed by an insulating layer with a flat top surface. The Josephson junction manufacturing method of the present invention is configured such that only the upper surface of the upper electrode is exposed and buried, and the wiring layer is formed directly on the upper surface of the upper electrode. a lower electrode, an insulator barrier layer,
A step of forming a Josephson junction structure in which an upper electrode of a superconductor is laminated in this order, and by depositing an insulating layer on the substrate by bias sputtering, the Josephson junction structure is formed with an insulating layer having a flat top surface. etch-packing the insulating layer until the upper surface of the upper electrode of the buried Josephson junction structure is exposed; and forming a wiring layer on the exposed upper surface of the upper electrode. Configure.

[Industrial application field]

The present invention relates to a Josephson junction device and a method for manufacturing the same.

Josephson junction devices have a structure in which a superconductor lower electrode, an insulator barrier layer, and a superconductor upper electrode are laminated in this order, and are said to be extremely fast and consume extremely low power. Because of these characteristics, the development of integrated circuits using Josephson junction devices is currently underway.

[Conventional technology]

The current and common Josephson junction has a Nb/A1oX/Nb structure in which Nb is used as the superconductor forming the upper and lower electrodes, and A10K is used as the insulator forming the barrier layer between these electrodes. It is typical to have

Conventionally, Kono N b / A 10 X / N b W
A Josephson combination device with an I structure is typically a third
It was manufactured through the steps shown in Figures (1) to (6).

Step (1): The substrate 1 is removed using a vacuum cleaner, etc. in a vacuum device.
On top, there is a lower Nb layer 2 with the lower part serving as a pole, and a barrier layer.

l! An OX layer 3 and an upper Nb layer 4 serving as an upper electrode are laminated in this order.

Step (2): After forming a resist layer 5 corresponding to a predetermined Josephson junction pattern on the upper Nb layer, using this resist layer 5 as a mask, dry the upper Nb layer 4 with a CF4-5%0□-based gas. After etching (reactive ion etching), the AftX layer 3 is sputtered, etched, and etched using Ar gas, thereby forming the upper Nb electrode portion 4 and the A! ○The Ubaria layer portion 3 is formed at the same radius W1.

Step (3) After removing the resist layer 5, a new resist layer 6 corresponding to a predetermined lower electrode pattern is formed. Using the resist layer 6 as a mask, the lower Nb layer 2 is dry-etched with CF, -5%0□-based gas.
Electrode portion 2 (width W) is formed. At this stage, the formation of the Josephson junction structure is completed. Normally, the width w2 of the lower electrode 2 is set to the barrier layer 3 and the upper electrode in order to improve step coverage in the subsequent process. Wider than the width w1 of 4.

Step (4) Cover the Josephson junction structure with an insulating layer 31 using varnish or the like.

Step (5): forming a resist layer 33 on the insulating layer 31,
A contact hole pattern 32 is formed in this resist layer 33 to be used for electrically connecting a wiring layer to be formed later and the upper electrode 4.

Step (6): By sputtering Nb, an Nb layer 34 that will become a wiring layer is deposited on the insulating layer 31, and the contact hole 35 is filled with Nb.
After forming a resist layer 36 corresponding to a predetermined wiring pattern on the Nb layer 34, dry etching is performed using a CF 4-5% Oz based gas using the resist layer 36 as a mask, thereby electrically connecting the upper electrode 4. Wiring layer 3 connected to
form 4.

As described above, in the conventional Josephson junction element formation, it is necessary to form the contact hole 35 with the wiring on the upper electrode 4 of the Josephson junction. At this time, the contact hole 35 must be smaller in area than the upper surface of the upper electrode 4 and must be formed at a position that will surely fit within the upper surface of the upper electrode 4 (FIG. 4(a)). If the contact hole 35 is not formed in such an area and position, the upper electrode 4 and the lower electrode 2 will short-circuit as shown in FIG. 4(b), and the Josephson junction element will not function properly. This causes a significant deterioration in the reliability of the entire integrated circuit in which the element is incorporated.

Therefore, it is very important to accurately align the contact hole with respect to the Josephson junction to ensure reliability.

However, as integrated circuits become more highly integrated and devices become smaller, not only does it become extremely difficult to accurately align contact holes, but it also becomes difficult to form microscopic contact holes themselves, making it difficult to achieve high reliability. There was a problem that it was not possible to achieve miniaturization and high integration while maintaining the reliability.

[Problem B to be Solved by the Invention] The present invention aims to solve the above-mentioned conventional problems and provide a Josephson junction element that can be miniaturized while ensuring reliability and a method for manufacturing the same. purpose.

[Means to solve the problem]

According to the present invention, a Josephson junction in which a lower electrode of a superconductor, a barrier layer of an insulator, and an upper electrode of a superconductor are laminated in this order is formed by forming an insulating layer with a flat top surface. This is achieved by a Josephson junction element characterized in that only the upper surface of the upper electrode is exposed and buried, and the wiring layer is formed directly on the upper surface of the upper electrode.

According to the present invention, the Josephson junction device of the present invention includes, on a substrate, a lower electrode of a superconductor and a barrier layer of an insulator.
A step of forming a Josephson junction structure in which an upper electrode of a superconductor is laminated in this order, and by depositing an insulating layer on the substrate by bias sputtering, the Josephson junction structure is formed with an insulating layer having a flat top surface. etch-packing the insulating layer until the upper surface of the upper electrode of the buried Josephson junction structure is exposed; and forming a wiring layer on the exposed upper surface of the upper electrode. It is manufactured by a method for manufacturing a Josephson junction element characterized by:

[Effect]

In the Josephson junction element of the present invention, the wiring layer is formed directly on the top surface of the upper electrode exposed on the insulating layer with a flat top surface, so that there is no contact hole in the form of a branch from the wiring layer as in the conventional case. unnecessary.

Since the wiring can be formed in the area of the upper surface of the upper electrode, there is no need for the high alignment accuracy required for conventional contact holes, which are formed smaller than the upper surface of the upper electrode, and there is no difficulty in forming small contact holes. Therefore, elements can be miniaturized while ensuring reliability.

The manufacturing procedure of the Josephson junction device of the present invention will be explained with reference to FIGS. 1 (1) to (6).

Process for forming the Josephson junction structure itself (1)
~ [3) is the process of the conventional method (
This is the same as 1) to (3). That is, steps (1) to (3)
), on the substrate 1, a lower electrode 2 of a superconductor,
A Josephson junction structure is formed in which a barrier layer 3 made of an insulator and an upper electrode 4 made of a superconductor are laminated in this order.

The method of the present invention includes steps (4) for forming the insulating layer 11.
(5) is characteristic.

Step (4) The insulating layer 11 is deposited by bias sputtering on the substrate on which the Josephson junction structure is formed, thereby embedding the Josephson junction structure with the insulating layer 11 having a flat upper surface 12.

Step (5): Stretch the insulating layer 11 until the upper surface 13 of the buried upper electrode 4 of the Josephson junction structure is exposed.
to have sex back. At this stage, the upper surface 1 of the upper electrode 4
3 and the upper surface 12' of the insulating layer 11 are planarized.

Step (6): A wiring layer 14 is formed on the exposed upper surface 13 of the upper electrode. In the Josephson junction device of the present invention, the upper surface of the insulating layer embedding the Josephson junction structure is substantially planarized with the upper surface of the upper electrode. Various processes can be considered as methods for obtaining such a final flattened state. Among these, the bias sputtering method is used as a method for burying and planarizing the Josephson junction. If an insulating layer such as 5iO7 is deposited by a bias sputtering method, planarization can be performed without affecting the characteristics of the Josephson junction.

In order to efficiently perform buried planarization by bias sputtering, it is advantageous to make the thickness of the lower electrode thinner than the thickness of the upper electrode. In general, what is important in planarization by bias sputtering is that the thickness of the insulating layer required for planarization depends on the width of the pattern to be planarized. In a Josephson junction, as described above, the pattern width of the lower electrode is usually wider than that of the upper electrode (WZ > w) in order to improve step coverage. Therefore, normally planarization is performed in accordance with the large lower electrode pattern width W2, and the insulating layer 11 is made considerably thicker as shown in FIG. 2(1). However, considering that it is sufficient to flatten only the area around the upper electrode,
Planarization is possible with a thinner insulating layer 11 than in FIG. 2(1). In this way, the insulating layer 1
By forming the insulating layer 11 thinly, the efficiency of the deposition process and the etch-back process of the insulating layer 11 can be improved.

A desirable embodiment of the present invention for improving the efficiency of the planarization process by making the lower electrode thinner than the upper electrode as described above will be described below.

After etching back the insulating layer 11 to the upper surface I3 of the upper electrode 4, a wiring layer 14 is formed on the upper surface 13 of the upper electrode (FIG. 2(2)). Thickness d8 of insulating layer 11 to be etch-packed
is expressed by the following formula (■).

de=d+ (dz +d:+)...■Here, dl: Total deposition thickness of the insulating layer 11, dz: Thickness of the insulating layer 11 from the bottom surface of the wiring layer 14 to the top surface of the lower electrode 2 (- Thickness of upper electrode 4 + thickness of barrier layer 3) d3: Thickness of lower electrode 2 In general, in order to improve the reliability of the circuit in a Josephson junction, it is necessary to reduce the insulation between the wiring layer 14 and the lower electrode 2. layer 11
It is necessary to make the thickness dz as large as possible.

In order to make the thickness dl (total deposition thickness) of the insulating layer 11 as thin as possible and to make dz as large as possible,
The thickness d3 of the lower electrode 2 is made as small as possible. More specifically, the thickness d3 of the lower electrode 2 is made thinner than at least the total thickness dz of the upper electrode 4 and the barrier layer 3, and more preferably thinner than the thickness of the upper electrode 4.

In the preferred embodiment of the present invention, the width W of the upper electrode 4
, and the width W2 of the lower electrode, it is possible to further improve the efficiency of forming the Josephson junction element of the present invention.

The total deposition thickness dl can be generally expressed by the following formula (2).

di = cL + (WZ /2) tan α・・−
■Here, α is the tilt angle determined by the self-bias voltage.

On the other hand, in order for the upper electrode 4 to be flattened with the total deposition thickness of dl, it is necessary that the following equation (2) holds true.

di d:+≧dz 10(V/+/2) ta
n α...■ Therefore, for this purpose, it is necessary that the relationship of the following formula (■) be established between Wl and w2.

W2≧W, +2d2/lanα... ■Under the condition that the above relationship (■) holds true, as shown in Fig. 2 (3), the second
Even if the insulating layer 11 is much thinner than that shown in Figure (1), the insulating layer 11
Planarization can be performed at the time of deposition.

If the above relationship does not hold, 2) will not be satisfied and dl
Since the relationship is d3 < dz + (W+ /2) tan cx, the upper electrode 4 portion is not completely flattened when the insulating layer 11 is deposited, resulting in a state as shown in FIG. 3 (4). It ends up. If etchback is performed from this state, the upper electrode 4 and the area near it will become protruding as shown in FIG. The insulating layer 11 has an etched shape and the thickness of the insulating layer 11 becomes thinner (-a4). In this state,
When the wiring layer 14 is formed to cover the upper surface 13 of the upper electrode 4 as shown in FIG. In that case, the thickness d2 of the insulating layer 11 between the wiring layer 14 and the lower electrode 2 becomes substantially smaller than the thickness d4, and the core properties of the circuit deteriorate.

Note that for boat fishing, it is advantageous to make the width W2 of the lower electrode 2 as small as possible in order to increase the efficiency of flattening by the high-pass spacing method. Of course, this fact can also be utilized in the present invention.

The present invention will be explained in more detail with reference to Examples below.

〔Example〕

Referring to the first part, an example of manufacturing a Josephson junction element according to a preferred embodiment of the present invention will be described.

In the steps (1) to (3) in FIG. 1, the Nb layer 110. /Nb Josephson junction structure (2, 3, 4) is formed.

Thereafter, the steps (4) to (6) in FIG. 1 are performed.

Step (9): By depositing the insulating layer 11 by bias sputtering on the substrate 1 on which the Josephson junction structure is formed, a SiO□ insulating layer 11 with a flat upper surface 12 is formed.
embed this Josephson junction structure.

At that time, bias sputtering is performed, for example, under the following conditions.

Bias sputtering - Deposition material: SiO□ Sputtering gas: Ar (pressure 10 mTorr) Bias voltage: 180 V Rf power = 21 W/Cm2 For example, the thickness of the upper electrode 4 is 300 nm and the thickness of the lower electrode 2 is 200 nm. Then, the thickness 1d of the Sin□ layer 11 necessary for flattening at the time of deposition by bias sputtering is 120' Onm, and the pattern width W of the upper electrode 4 and the pattern width W2 of the lower electrode 2 that satisfy the formula (2) The relationship is Wl-2.0 μm, Wz =1.5 μm.

Between steps: until the upper surface 13 of the buried upper electrode 4 of the Josephson junction structure is exposed,
to have sex back. At this stage, the upper surface 1 of the upper electrode 4
3 and the upper surface 12' of the insulating layer 11 are planarized.

At that time, the etchback is performed under the following conditions, for example.

An example of etch bank Etchant: CHF, -20%0□ Pressure: 15 mTorr Rf power: 100 W Sin, etchback amount: approximately 700 nm After depositing the layer to a thickness of 500 nm, the Nb layer is patterned by conventional photolithography to form the Nb wiring layer 14.

Through the above steps (1) to (6), the lower electrode 2 of the superconductor, the barrier layer 3 of the insulator, and the upper electrode 3 of the superconductor are formed.
A Josephson junction in which
is embedded in a flat insulating layer 11 with only the upper electrode upper surface 1 exposed, and the wiring layer 14 is embedded in the upper electrode upper surface 1.
A Josephson junction element of the present invention is fabricated directly on 3.

[Effects of the Invention] As described above, according to the present invention, it is possible to miniaturize a Josephson junction element while ensuring its physical properties.

[Brief explanation of the drawing]

Figures 1 (1) to (6) are cross-sectional views showing the process of manufacturing the Josephson junction structure of the present invention, and Figures 2 (1) to (5) are pattern dimensions and planarization of the Josephson junction structure. Cross-sectional view showing the relationship between
~(6) are cross-sectional views showing typical steps for manufacturing conventional Josephson junction elements, and FIGS. 4(a) and (b).
) is a cross-sectional view showing the alignment state of contact portions in a conventional Josephson junction element. ■... Substrate, 2... Lower electrode layer, 3...
... Barrier layer, 4... Upper electrode layer, 5.6
...Resist layer, 11...Insulating layer, 12.12
°...Top surface of insulating layer 11, 13...Top surface of upper electrode 4, 14... Wiring layer, 31... Insulating layer, 32
...Contact hole pattern, 33...Resist layer, 34...Wiring layer, 35
...Contact hole, 36...Resist layer, W,...
・Width of upper electrode, W2 ・Width of lower electrode, dl・
...Total deposition thickness of insulating layer, d2 ...Total thickness of upper electrode and barrier layer, d3...
Thickness of the lower electrode, d4...Thickness of the insulating layer in the over-etched region.

Claims (1)

[Scope of Claims] 1. A Josephson junction in which a lower electrode of a superconductor, a barrier layer of an insulator, and an upper electrode of a superconductor are laminated in this order, the upper electrode is formed by an insulating layer with a flat top surface. A Josephson junction element characterized in that it is buried with only its top surface exposed, and a wiring layer is formed directly on the top surface of the top electrode. 2. The Josephson junction device according to claim 1, wherein the thickness of the lower electrode is thinner than the thickness of the upper electrode. 3. Between the width W_1 of the upper electrode, the width W_2 of the lower electrode, and the total thickness d_2 of the upper electrode and the barrier layer, there is a relationship of W_2≧W_1+2d_2/tanα, using the inclination angle α determined by the self-bias voltage as a parameter. The Josephson junction element according to claim 1 or 2, wherein the Josephson junction element is satisfied. 4. Forming a Josephson junction structure in which a superconductor lower electrode, an insulator barrier layer, and a superconductor upper electrode are laminated in this order on the substrate, bias sputtering on the substrate. By depositing an insulating layer by
embedding the Josephson junction structure with an insulating layer having a flat top surface; etching back the insulating layer until a top surface of the top electrode of the buried Josephson junction structure is exposed; and the exposed top electrode. A method of manufacturing a Josephson junction device, comprising the step of forming a wiring layer on an upper surface. 5. The method according to claim 4, wherein in the Josephson junction structure forming step, the lower electrode is formed thinner than the upper electrode. 6. Between the width W_1 of the upper electrode, the width W_2 of the lower electrode, and the total thickness d_2 of the upper electrode and the barrier layer, there is a relationship of W_2≧W_1+2d_2/tanα, with the inclination angle α determined by the self-bias voltage as a parameter. The method according to claim 4 or 5, characterized in that the upper electrode, the barrier layer and the lower electrode are formed so as to be formed.