JPH0494150A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0494150A
JPH0494150A JP21225790A JP21225790A JPH0494150A JP H0494150 A JPH0494150 A JP H0494150A JP 21225790 A JP21225790 A JP 21225790A JP 21225790 A JP21225790 A JP 21225790A JP H0494150 A JPH0494150 A JP H0494150A
Authority
JP
Japan
Prior art keywords
cavity
semiconductor substrate
substrate
mirror
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21225790A
Other languages
Japanese (ja)
Other versions
JP2841780B2 (en
Inventor
Mitsutaka Katada
満孝 堅田
Masaki Matsui
正樹 松井
Kazuhiro Tsuruta
和弘 鶴田
Seiji Fujino
藤野 誠二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soken Inc
Original Assignee
Nippon Soken Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Soken Inc filed Critical Nippon Soken Inc
Priority to JP21225790A priority Critical patent/JP2841780B2/en
Publication of JPH0494150A publication Critical patent/JPH0494150A/en
Application granted granted Critical
Publication of JP2841780B2 publication Critical patent/JP2841780B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To form an oxide film in a cavity by charging high-purity oxidizing gas into the cavity formed by the recess of the first semiconductor substrate and the second semiconductor substrate, and then heat-treating it. CONSTITUTION:One part of the mirror face 1a of an N<->-type first semiconductor substrate 1, which is polished into a mirror face, is etched selectively, and a recess 2, 0.2-2mum in thickness is made, and a groove 3, which opens at the end of the substrate, is made. The fellow mirror faces 1a and 5a of the first semiconductor substrate 1 and the second N<+>-type semiconductor substrate 5, which is also polished into a mirror face, are stuck together. The recess 2 is not joined, and by the recess 2 and the mirror face 5a of the second semiconductor substrate 5, a cavity 4 is formed. The joined substrate 10 is arranged in a vacuum vessel 6, and it is maintained for thirty minutes or more after a vacuum system becomes 10Pa or less. After the inside of the cavity 4 is vacuumized, O2 gas is supplied into the vessel 6, and immediately it is put in a heat treatment vessel 7 so as to do heat-treat the joined substrate 10 in oxidizing atmosphere, thus an oxide film 11 is made at the surface of the groove 3 and inside the cavity 4.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、素子分離された半導体装置の製造方法に関し
、特に高耐圧な素子分離構造を有、する半導体装置の製
造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device with element isolation, and more particularly to a method for manufacturing a semiconductor device having a high breakdown voltage element isolation structure.

「従来の技術] 従来、例えば高耐圧パワー素子と論理回路を1チップに
搭載する場合のように特別な高耐圧を有する素子分離に
は、PN接合による分離法と絶縁体による分離法が用い
られている。
``Prior art'' Conventionally, isolation methods using PN junctions and isolation methods using insulators have been used to isolate elements with special high voltage resistance, such as when a high voltage power element and a logic circuit are mounted on one chip. ing.

PN接合を用いた分離法は、P型半導体基板上にN型エ
ピタキシャル層を形成し、該エピタキシャル層表面から
上記P型基板に達するP 層を拡散形成してパワー素子
部と論理回路部を分離するものである。これにより論理
回路部をP 層によって包んでPN接合が形成され、こ
のPN接合に逆バイアスをかけることにより空乏層がで
きて論理回路部を他の領域と電気的に分離する。この方
法は安価に行なえるが、300■以上のパワー素子を形
成するためには拡散深さが40μm以上必要で素子分離
に長時間を要し、また横方向の拡散幅が増大するため素
子の集積密度は低い。
In the isolation method using a PN junction, an N-type epitaxial layer is formed on a P-type semiconductor substrate, and a P layer extending from the surface of the epitaxial layer to the P-type substrate is formed by diffusion to separate the power element part and the logic circuit part. It is something to do. As a result, a PN junction is formed by surrounding the logic circuit section with the P layer, and by applying a reverse bias to this PN junction, a depletion layer is created to electrically isolate the logic circuit section from other regions. This method can be carried out at low cost, but in order to form a power device of 300 μm or more, the diffusion depth must be 40 μm or more, which requires a long time to separate the devices, and the lateral diffusion width increases, so the device The accumulation density is low.

一方、絶縁体を用いた分離法には、N型半導体基板の所
定領域を選択的にエツチングして渭を形成した後、表面
に熱酸化膜を形成し、さらに多結晶シリコンを堆積した
後、基板裏面より溝に達するまで研磨してN型層を絶縁
分離する方法、あるいは、絶縁膜を介して2枚の半導体
基板を接合し、接合基板の一方の面を選択的にエツチン
グして絶縁膜に達する分離溝を形成して、熱酸化膜を形
成し、多結晶シリコンを堆積して溝を埋めた後、表面の
多結晶シリコン層を除去する方法がある。
On the other hand, in the isolation method using an insulator, a predetermined region of an N-type semiconductor substrate is selectively etched to form a ridge, a thermal oxide film is formed on the surface, and polycrystalline silicon is further deposited. There is a method of insulating and separating the N-type layer by polishing from the back side of the substrate until it reaches the groove, or a method of bonding two semiconductor substrates through an insulating film and selectively etching one side of the bonded substrate to form an insulating film. There is a method of forming an isolation trench that reaches up to 100 cm, forming a thermal oxide film, depositing polycrystalline silicon to fill the trench, and then removing the polycrystalline silicon layer on the surface.

これらの方法は高い分離耐圧を実現するが、いずれも基
板の一方の主面が絶縁されており、裏面を電流経路とす
る縦型パワー素子には不向きであるという問題があった
Although these methods achieve a high isolation voltage, they all have the problem that one main surface of the substrate is insulated, making them unsuitable for vertical power devices with a current path on the back surface.

そこで、近年、シリコン基板の直接接合技術を用いて、
基板内部に熱酸化膜を選択的に埋め込む方法が注目され
ている。その−例として、特開昭61−42154号公
報には、鏡面研磨された第1の半導体基板の表面に酸素
導入用の講を形成するとともに、上記溝と連通する浅い
凹部を形成し、これに鏡面研磨された第2の半導体基板
を直接接合して内部に空洞を形成した後、上記溝に沿っ
て内部の空洞に酸化性ガスを供給することにより、熱酸
化膜を埋め込み形成する方法が提案されている。この方
法によれば、任意の箇所に任意の形状の酸化膜を埋め込
むことができる。
Therefore, in recent years, using direct bonding technology of silicon substrates,
A method of selectively embedding a thermal oxide film inside a substrate is attracting attention. As an example, Japanese Patent Application Laid-Open No. 61-42154 discloses that a hole for introducing oxygen is formed on the surface of a mirror-polished first semiconductor substrate, and a shallow recess communicating with the groove is formed. There is a method of directly bonding a mirror-polished second semiconductor substrate to form a cavity therein, and then supplying an oxidizing gas to the interior cavity along the groove to form a buried thermal oxide film. Proposed. According to this method, an oxide film of any shape can be embedded in any location.

U発明が解決しようとする課題] しかしながら、特開昭61−42154号公報の方法に
おいて、熱酸化膜を埋め込む空洞の深さは高々1.5μ
m、酸素導入用の溝は幅、深さが高々100μmと極め
て狭いものにならざるを得ない。一方、基板の接合は通
常大気中にて行なわれるため、空洞内には空気(窒素:
酸素=4:1)が残留しており、窒素の滞留により酸素
の供給がいっそう阻害されて、均一な酸化膜の成長が困
難となり、埋め込みに時間を要する。また、ウェハ径が
大きくなるほどこの傾向が強くなる。
Problems to be Solved by the Invention] However, in the method of JP-A-61-42154, the depth of the cavity in which the thermal oxide film is buried is at most 1.5 μm.
m, the groove for oxygen introduction must be extremely narrow, with a width and depth of at most 100 μm. On the other hand, since bonding of substrates is usually performed in the atmosphere, there is air (nitrogen:
Oxygen (4:1) remains, and the accumulation of nitrogen further inhibits the supply of oxygen, making it difficult to grow a uniform oxide film and requiring time for embedding. Moreover, this tendency becomes stronger as the wafer diameter becomes larger.

本発明は上記の問題点に鑑みてなされたものであり、酸
化膜を均一に、しかも短時間で成長させ、高耐圧な素子
分離領域を容易に形成することを目的とするものである
The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to grow an oxide film uniformly and in a short time to easily form a high voltage isolation region.

[課題を解決をするための手段] 本発明の半導体装置の製造方法は、少なくとも一方の面
が鏡面研磨された第1半導体基板の鏡面に凹部を形成し
、この凹部の側縁に沿って凹部より深い酸化性ガス導入
用の溝部を形成する工程と、第1半導体基板の上記鏡面
と、少なくとも一方の面が鏡面研磨された第2半導体基
板の鏡面とを直接接合する工程と、 得られた接合基板を真空引きした後、第1半導体基板の
上記凹部と第2半導体基板とで形成される空洞部内に、
上記溝部を介して高純度の酸化性ガスを充填する工程と
、 この接合基板を酸化性ガス雰囲気中で熱処理することに
よって上記空洞部内に酸化膜を埋設する工程を有する。
[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes forming a recess in the mirror surface of a first semiconductor substrate having at least one surface mirror-polished, and forming recesses along the side edges of the recess. a step of forming a deeper groove for introducing an oxidizing gas, and a step of directly bonding the mirror surface of the first semiconductor substrate to the mirror surface of a second semiconductor substrate having at least one surface mirror-polished; After the bonded substrate is evacuated, a cavity formed by the recessed portion of the first semiconductor substrate and the second semiconductor substrate,
The method includes a step of filling a high-purity oxidizing gas through the groove, and a step of embedding an oxide film in the cavity by heat-treating the bonded substrate in an oxidizing gas atmosphere.

あるいは、凹部および溝部を形成した第1半導体基板と
、第2半導体基板とを高純度の酸化性ガス雰囲気中に配
置し、これらの鏡面どうしを密着させて直接接合して接
合基板を形成すると同時に、第1半導体基板の上記凹部
と第2半導体基板とで形成される空洞部内に高純度の酸
化性ガスを充填し、しかる後、得られた接合基板を酸化
性ガス雰囲気中で熱処理することによって、上記空洞部
内に酸化膜を形成してもよい。
Alternatively, a first semiconductor substrate having a recess and a groove formed therein and a second semiconductor substrate are placed in a high-purity oxidizing gas atmosphere, and their mirror surfaces are brought into close contact with each other and directly bonded to form a bonded substrate. , by filling the cavity formed by the recess of the first semiconductor substrate and the second semiconductor substrate with a high-purity oxidizing gas, and then heat-treating the obtained bonded substrate in an oxidizing gas atmosphere. , an oxide film may be formed within the cavity.

[作用] 半導体基板を大気中で直接接合すると、接合後の基板に
形成される空洞部内は空気で満たされることになる。こ
の接合基板を真空引きすることにより、空洞部内の空気
を除去し、その後、真空系内に高純度の酸化性ガスを供
給すれば、溝部を介して空洞部内は酸化性ガスで溝たさ
れる。あるいは接合を酸化性ガス雰囲気中で行なうこと
によっても空洞部内を酸化性ガスで満たすことが可能で
ある。
[Operation] When semiconductor substrates are directly bonded in the atmosphere, the cavity formed in the bonded substrate is filled with air. By evacuating this bonded substrate, the air inside the cavity is removed, and then, by supplying high-purity oxidizing gas into the vacuum system, the inside of the cavity is filled with oxidizing gas through the groove. . Alternatively, the cavity can be filled with oxidizing gas by performing the bonding in an oxidizing gas atmosphere.

この接合基板を熱処理すれば、空洞部内は酸化性ガスの
みで満たされているので、酸化反応が円滑に進み、空洞
部表面に酸化膜が成長する。また、窒素等未反応ガスが
滞留することがなく、外部から順次酸化性ガスが供給さ
れるので、酸化速度が増大し、短時間で酸化膜を埋め込
むことができる。
When this bonded substrate is heat-treated, since the inside of the cavity is filled only with oxidizing gas, the oxidation reaction proceeds smoothly and an oxide film grows on the surface of the cavity. Further, since unreacted gas such as nitrogen does not remain and oxidizing gas is sequentially supplied from the outside, the oxidation rate increases and the oxide film can be embedded in a short time.

[第1実施例コ 以下、本発明の実施例を図面を参照して説明する。第1
図は本実施例の半導体装置の製造工程を示す断面図であ
る。
[First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a cross-sectional view showing the manufacturing process of the semiconductor device of this example.

まず、第1図(a)の如く、少なくとも一方の面を鏡面
研磨したN−型の第1半導体基板1の鏡面1aの一部を
、化学エツチングあるいは反応性イオンエツチング(以
下RIEという)により選択的にエツチングし、深さ0
.2〜2μmの凹部2を形成する。
First, as shown in FIG. 1(a), a part of the mirror surface 1a of an N-type first semiconductor substrate 1 whose at least one surface is mirror-polished is selected by chemical etching or reactive ion etching (hereinafter referred to as RIE). etching, depth 0
.. A recess 2 of 2 to 2 μm is formed.

次に第1図(b)に示すように、凹部2の側縁2a(第
1図(a))に沿って、基板端部に開口する溝3を化学
エツチング、RIEあるいはダイシングにより形成する
。このとき、溝3は凹部2より深くすることが望ましく
、具体的には幅2μm以上、深さ2μm以上とする。
Next, as shown in FIG. 1(b), a groove 3 opening at the edge of the substrate is formed along the side edge 2a of the recess 2 (FIG. 1(a)) by chemical etching, RIE, or dicing. At this time, it is desirable that the groove 3 is deeper than the recess 2, and specifically, the width is 2 μm or more and the depth is 2 μm or more.

この第1半導体基板1と、少なくとも一方の面を鏡面研
磨したN+型の第2半導体基板5とを、例えばトリクレ
ン煮沸、アセトン超音波洗浄、NH3:H2O2:H2
0=1 : 1 :4の混合液による有機物の除去、H
C,I! :H2O2:H20=1 : 1 :4の混
合液による金属汚染の除去、および純水洗浄を順次施す
ことにより、充分洗浄する。その後、さらにHF : 
H20=1 : 50の混合液により表面の自然酸化膜
を除去した後、例えば)!2 SO2: H2O2=3
 : 1の1合Mによ’)基板表面に15A以下の酸化
膜を形成し、親水性を持たせて、純水にて洗浄する。
This first semiconductor substrate 1 and an N+ type second semiconductor substrate 5 whose at least one surface is mirror-polished are subjected to, for example, trichlene boiling, acetone ultrasonic cleaning, NH3:H2O2:H2
Removal of organic matter with a mixture of 0=1:1:4, H
C, I! :H2O2:H20=1:1:4 mixture to remove metal contamination and clean with pure water in order to thoroughly clean. After that, more HF:
After removing the natural oxide film on the surface with a mixture of H20=1:50, for example)! 2 SO2: H2O2=3
: 1.1) Form an oxide film of 15A or less on the surface of the substrate to make it hydrophilic, and wash it with pure water.

次に、乾燥窒素等による乾燥を行ない、基板表面に吸着
する水分量を制御した後、第1図(c)の如く2枚の基
板1.5の鏡面1a、5aどうしを密着させる。これに
より、2枚の基板1.5は表面に形成されたシラノール
基および表面に吸着した水分子の水素結合により接着す
る。さらに、この接着した基板1.5を10 丁orr
以下の真空中にて乾燥させる。このとき、基板1.5の
反りを補償するため、30g重/重恩−の荷重を印加し
てもよい。
Next, after drying with dry nitrogen or the like to control the amount of moisture adsorbed on the substrate surface, the mirror surfaces 1a and 5a of the two substrates 1.5 are brought into close contact with each other as shown in FIG. 1(c). As a result, the two substrates 1.5 are bonded together by hydrogen bonding between the silanol groups formed on the surfaces and the water molecules adsorbed on the surfaces. Furthermore, this bonded substrate 1.5
Dry in vacuum below. At this time, in order to compensate for the warpage of the substrate 1.5, a load of 30 g/weight may be applied.

この後、基板1.5を、例えば窒素、アルゴン等の不活
性ガス雰囲気中で、1100℃以上、1時間以上の熱処
理を施すことにより、接着面において脱水縮合反応が起
きてシリコン(Si)と酸素(0)(7)結合(Si−
0−3i)ができ、さらに酸素が基板に拡散してSi原
子どうしの結合ができて(Si−3i)−2枚の基板1
.5か直接接合された接合基板10が形成される。この
とき上記凹部2は接合しておらず、凹部2と第2半導体
基板5の鏡面5aとで空洞部4が形成される。
Thereafter, the substrate 1.5 is heat-treated at 1100°C or higher for 1 hour or more in an inert gas atmosphere such as nitrogen or argon, so that a dehydration condensation reaction occurs on the adhesive surface and forms silicon (Si). Oxygen (0) (7) bond (Si-
0-3i) is formed, and further oxygen diffuses into the substrate to form bonds between Si atoms, (Si-3i) - two substrates 1
.. A bonded substrate 10 is formed by directly bonding the substrates 5 and 5. At this time, the recess 2 is not joined, and a cavity 4 is formed between the recess 2 and the mirror surface 5a of the second semiconductor substrate 5.

なお、この工程では1100℃以上の高温熱処理を不活
性ガス雰囲気中で行なうため、熱処理中に空洞部4内の
酸素は消費され、空洞部4には外部から不活性ガスが侵
入、充填されることになる。
Note that in this step, high-temperature heat treatment at 1100° C. or higher is performed in an inert gas atmosphere, so oxygen in the cavity 4 is consumed during the heat treatment, and the cavity 4 is infiltrated and filled with inert gas from the outside. It turns out.

本実施例では、酸化膜成長の阻害要因となる不活性ガス
を空洞部4内から除去するため、第1図(d)の工程で
、真空容器6中に接合基板10を配し、真空ポンプ61
により真空容器6内を排気する。このとき真空ポンプ6
1に連通する真空バルブ62は開、酸化性雰囲気ガスに
連通ずる真空バルブ63は閉状態とする。また真空到達
度は、次工程の酸化膜成長の際に残留不活性ガスの膨張
による阻害をなくすために空洞内のガスはほぼ完全に除
去する必要がある。具体的には真空到達度を10Pa以
下とすることが望ましい。真空引きの時間は、高々1μ
m程度の間隙しかない空洞部4を排気する必要から、圧
損あるいは空洞部4に面する基板表面に吸着したガスを
完全に除去するために、できるだけ長い時間性なう必要
がある。
In this embodiment, in order to remove the inert gas that inhibits the growth of the oxide film from inside the cavity 4, the bonded substrate 10 is placed in the vacuum container 6 in the step shown in FIG. 61
The inside of the vacuum container 6 is evacuated. At this time, the vacuum pump 6
The vacuum valve 62 communicating with the oxidizing atmosphere gas 1 is open, and the vacuum valve 63 communicating with the oxidizing atmosphere gas is closed. Further, regarding the degree of vacuum attainment, it is necessary to almost completely remove the gas in the cavity in order to eliminate the inhibition caused by the expansion of the residual inert gas during the next step of growing an oxide film. Specifically, it is desirable that the degree of vacuum attainment is 10 Pa or less. Vacuuming time is at most 1μ
Since it is necessary to evacuate the cavity 4 which has a gap of only about m, it is necessary to wait as long as possible in order to completely remove the pressure loss or the gas adsorbed on the surface of the substrate facing the cavity 4.

具体的には真空容器6の真空系が10Pa以下となって
から30分以上とすることが望ましい。さらにこの真空
引き中に接合基板10をヒータ64により加熱し、基板
表面に吸着したガスの排気の促進を行なってもよい。こ
の時の加熱温度としては100℃以上とすることが望ま
しい。
Specifically, it is desirable to wait for 30 minutes or more after the vacuum system of the vacuum container 6 becomes 10 Pa or less. Furthermore, during this evacuation, the bonded substrate 10 may be heated by the heater 64 to promote exhaustion of the gas adsorbed on the substrate surface. The heating temperature at this time is preferably 100° C. or higher.

このようにして空洞部4内を真空引きした後、バルブ6
2を閉じ、バルブ63を開けて02ガスあるいは02.
H2混合ガスを容器6内に供給する。このとき02,8
2等酸化性ガス以外の不活性ガスが混入すると空洞部4
内の酸化の妨げとなるため、使用するガスは、不活性ガ
スの混入率が1%以内の高純度の酸化性ガスとすること
が望ましい。このようにして真空容器6に酸化性ガスを
大気圧以上の圧力になるまで供給する。空洞部4内は前
記の如く非常に狭い領域であるので、圧損を考慮して大
気圧以上の圧力に到達してから1分以上保持することが
望ましい。
After evacuating the inside of the cavity 4 in this way, the valve 6
2 and open valve 63 to supply 02 gas or 02.
H2 mixed gas is supplied into the container 6. At this time 02,8
If an inert gas other than a secondary oxidizing gas gets mixed in, the cavity 4
It is desirable that the gas used be a high-purity oxidizing gas with an inert gas content of 1% or less. In this way, oxidizing gas is supplied to the vacuum container 6 until the pressure reaches atmospheric pressure or higher. Since the interior of the cavity 4 is a very narrow area as described above, it is desirable to maintain the pressure for at least one minute after reaching the atmospheric pressure or higher, taking pressure loss into consideration.

このように空洞部4内に酸化性ガスを充填した後、直ち
にこの接合基板10を800℃以上に加熱可能なヒータ
71を有する熱処理容器7に入れる(第1図(e))。
Immediately after filling the cavity 4 with the oxidizing gas, the bonded substrate 10 is placed in a heat treatment container 7 having a heater 71 capable of heating to 800° C. or higher (FIG. 1(e)).

次いで、接合基板10を例えばドライo2、ウェット0
2.H2,,02混合気体等の酸化性雰囲気中で800
℃以上、1時間以上の熱処理を施す。これにより、溝3
を通して空洞部4内に酸化性ガスが供給され、講3表面
および空洞部4内に酸化膜11を形成する。ただしこの
酸化工程は、空洞部4が成長する酸化膜11によって完
全に埋設、充填されるまで最低性なう。
Next, the bonding substrate 10 is subjected to, for example, dry O2, wet O2
2. 800 in an oxidizing atmosphere such as H2,,02 mixed gas
Heat treatment is performed at ℃ or higher for 1 hour or longer. As a result, groove 3
An oxidizing gas is supplied into the cavity 4 through the tube 3 to form an oxide film 11 on the surface of the tube 3 and inside the cavity 4. However, this oxidation step is continued until the cavity 4 is completely buried and filled with the growing oxide film 11.

なお、空洞部4の酸化速度を上げるなめ、接合前、つま
り第1図(a>または(b)の工程で、酸化促進のため
酸素をイオン注入しておいてもよい。イオン注入条件と
しては、例えば02 を用いてドーズ量を5X1014
/−とし、第1半導体基板の鏡面1aおよび第2半導体
基板の鏡面5aいずれかあるいは両方の面に注入すれば
、ウェハ表面が非晶質化され、この状態で上記(、C)
の接合工程を実施すればS i −8i接合部で固相成
長が起こり、より結晶性の良好なS i −3i接合状
態を得ることが可能となる。
In order to increase the oxidation rate of the cavity 4, oxygen ions may be implanted to promote oxidation before bonding, that is, in the step shown in FIG. 1 (a> or (b)).Ion implantation conditions are as follows. , for example, using 02 and increasing the dose to 5X1014
/-, and if it is implanted into either or both of the mirror surface 1a of the first semiconductor substrate and the mirror surface 5a of the second semiconductor substrate, the wafer surface becomes amorphous, and in this state, the above (,C)
If the above bonding step is carried out, solid phase growth will occur at the Si-8i junction, making it possible to obtain an Si-3i bonding state with better crystallinity.

また(d)から(e)への工程に移るときは、空洞部4
内への外気の混入を避けるため、できるだけ短時間に処
理する必要があり、大気に曝す時間は1時間以内とする
ことが望ましい。さらに(d)、(e)の処理が同一装
置で実施可能であれば大気に曝されることがなくなるた
めより望ましい。また、熱処理容器7中の雰囲気は大気
圧より高い圧力を保持できれば空洞部4内へ酸化性ガス
がより容易に供給できる。
Also, when moving from step (d) to step (e), the cavity 4
In order to avoid mixing of outside air into the interior, it is necessary to perform the treatment in as short a time as possible, and it is desirable that the time of exposure to the atmosphere be within one hour. Furthermore, it is more desirable if the processes (d) and (e) can be carried out in the same apparatus, since exposure to the atmosphere can be avoided. Further, if the atmosphere in the heat treatment container 7 can maintain a pressure higher than atmospheric pressure, the oxidizing gas can be more easily supplied into the cavity 4.

このように、空洞部4内に高純度の酸化性ガスを充填し
た状態で処理を行なえば、空洞部内のガスは全て酸化膜
11の形成に使用されるため、外気と空洞部4内の圧力
差により熱処理容器7内の酸化性ガスは溝3を通って容
易に供給され、極めて短時間に空洞部表面の酸化膜11
の成長、埋設が可能となる。
In this way, if the process is performed with the cavity 4 filled with high-purity oxidizing gas, all the gas in the cavity is used to form the oxide film 11, so the pressure between the outside air and the inside of the cavity 4 is reduced. Due to the difference, the oxidizing gas in the heat treatment container 7 is easily supplied through the groove 3, and the oxide film 11 on the surface of the cavity is quickly removed.
growth and burial becomes possible.

本実施例では、前述したように、基板接合後、不活性ガ
ス雰囲気中で熱処理を行なっているため、空洞部4内の
酸素は消費されて不活性ガスが充填されている。この空
洞部4は間隙が高々1μm程度しかないため、単に外気
に放置しただけでは空洞内の不活性ガスが外気と混合し
てこれと完全に置換するには相当の長時間を要し、例え
ば24時間の放置でも十分ではない。仮に、このように
不活性ガスが空洞部4内に滞留した状態で熱処理容器7
に入れ、工程(e)の酸化処理を行なったとすると、通
常この酸化処理工程は1000℃以上の高温中で行なわ
れるため、空洞部4内に残留する不活性ガスが熱膨張し
く常温の4.3倍)、空洞部4内が不活性ガスで充満し
てしまう。こうなると、容易に酸化性ガスが内部に侵入
できず、酸化膜の成長速度を著しく低下させることにな
る。
In this embodiment, as described above, since the heat treatment is performed in an inert gas atmosphere after the substrates are bonded, the oxygen in the cavity 4 is consumed and the cavity 4 is filled with inert gas. This cavity 4 has a gap of about 1 μm at most, so if it is simply left in the outside air, it will take a considerable amount of time for the inert gas inside the cavity to mix with the outside air and completely replace it. Even leaving it for 24 hours is not enough. Suppose that the heat treatment container 7 is opened in a state where the inert gas remains in the cavity 4 in this way.
When the oxidation treatment in step (e) is performed, the oxidation treatment step is usually performed at a high temperature of 1000° C. or higher, so the inert gas remaining in the cavity 4 expands thermally and becomes oxidized at room temperature. 3 times), the inside of the cavity 4 is filled with inert gas. In this case, oxidizing gas cannot easily enter the inside, which significantly reduces the growth rate of the oxide film.

第2図は3インチウェハにおいて、幅30μm、深さ3
0μmの溝を形成した場合の空洞部内に酸化性ガスを充
填した場合(本実施例)と大気を充填した場合(比較例
)とで空洞部の埋設状態がどう変わるかを測定した結果
である。図に明らかなように、本実施例の方法では2時
間という短時間の熱処理によって空洞部の埋設率がほぼ
100%に達している。これに対し、比較例では反応速
度が遅い上、10時間という長時間の熱処理を施しても
ウェハ全面での埋設は不可能であり、本発明方法が非常
に有効であることが判明した。
Figure 2 shows a 3-inch wafer with a width of 30 μm and a depth of 3
These are the results of measuring how the buried state of the cavity changes when a 0 μm groove is formed and the cavity is filled with oxidizing gas (this example) and when it is filled with air (comparative example). . As is clear from the figure, in the method of the present example, the filling rate of the cavity reaches almost 100% by heat treatment for a short time of 2 hours. On the other hand, in the comparative example, the reaction rate was slow and it was impossible to embed the entire surface of the wafer even after heat treatment for a long time of 10 hours, proving that the method of the present invention is very effective.

次に、第1図(f>に示すように、第1半導体基板1の
表面上すに、溝3が開口するまで研磨またはエツチング
する。そしてさらに第1図(g>の如く、例えばCVD
法により例えば多結晶シリコン13を堆積させ、溝3を
埋める。ただしこの際の充填物質は酸化物や窒化ケイ素
物等の絶縁物でもよく、充填方法もスパッタ、蒸着、S
OG等でもよい。また溝3は表面の開口部が閉じられれ
ば必ずしも完全に多結晶シリコン13で埋められていな
くてもよく、空洞部が残ってもよい。
Next, as shown in FIG. 1 (f), the entire surface of the first semiconductor substrate 1 is polished or etched until a groove 3 is opened. Then, as shown in FIG.
For example, polycrystalline silicon 13 is deposited by a method to fill the groove 3. However, the filling material in this case may be an insulating material such as oxide or silicon nitride, and the filling method may also be sputtering, vapor deposition, S
It may be OG etc. Further, the groove 3 does not necessarily have to be completely filled with polycrystalline silicon 13 as long as the opening on the surface is closed, and a cavity may remain.

そして、例えばラップポリッシュあるいはエツチングバ
ック等により、表面の堆積物を除去し、平坦化すること
により多結晶シリコン13および酸化膜11で他の領域
と電気的に完全に分離された領域12を有する半導体基
板10を得る。、二の半導体基板10に所定の素子を形
成することにより所望の半導体装置を得ることができる
Then, by removing deposits on the surface and flattening it by lap polishing or etching back, for example, the semiconductor has a region 12 that is completely electrically isolated from other regions by the polycrystalline silicon 13 and the oxide film 11. A substrate 10 is obtained. , a desired semiconductor device can be obtained by forming predetermined elements on the second semiconductor substrate 10.

第3図は、縦型パワートランジスタ8およびトランジス
タ8を制御する論理回路9を、1チツプの半導体基板1
0に搭載した例である。
FIG. 3 shows a vertical power transistor 8 and a logic circuit 9 that controls the transistor 8 on a single-chip semiconductor substrate 1.
This is an example installed in 0.

ここで、半導体基板10はN−型の低不純物濃度の第1
半導体基板1とN 型の第2半導体基板5とを直接接合
したもので、上記第1図の工程により作製された絶縁分
離領域12を有する。縦型パワートランジスタ8は、基
板1の端面にソース電極81、ゲート電極82が形成さ
れ、また第2半導体基板5の端面にはドレイン電極83
が形成されている。論理回路9は、基板1の領域12内
に、ソース、トレイン、ゲートの各電極が形成してあり
、シリコン酸化膜11と多結晶シリコン13によって基
板のその他の部分と絶縁分離されている。
Here, the semiconductor substrate 10 is an N-type first semiconductor substrate with a low impurity concentration.
The semiconductor substrate 1 and the N-type second semiconductor substrate 5 are directly bonded, and have an insulating isolation region 12 produced by the process shown in FIG. 1 above. In the vertical power transistor 8, a source electrode 81 and a gate electrode 82 are formed on the end surface of the substrate 1, and a drain electrode 83 is formed on the end surface of the second semiconductor substrate 5.
is formed. In the logic circuit 9, source, train, and gate electrodes are formed in a region 12 of the substrate 1, and are insulated and separated from other parts of the substrate by a silicon oxide film 11 and polycrystalline silicon 13.

本実施例では、上記絶縁分離領域12が単結晶基板によ
り形成されているため、素子特性が良好であり、また酸
化11allによってトランジスタ8と絶縁分離されて
いるため、分離耐圧が大きく、耐熱性にも優れている。
In this embodiment, since the isolation region 12 is formed of a single crystal substrate, the device characteristics are good, and since it is insulated from the transistor 8 by oxidation 11all, the isolation region 12 has a high isolation voltage and has good heat resistance. is also excellent.

さらに、分離溝3が表面に露出するため、分離領域12
と、表面に形成する素子との位置合わせが容易である。
Furthermore, since the separation groove 3 is exposed on the surface, the separation region 12
This makes it easy to align the elements formed on the surface.

[第2実施例] 第4図は本発明の第2の実施例の製造工程を示す。本実
施例において第4図(a>(b)の工程は上記第1実施
例と同様であり、N−型第1半導体基板1の鏡面研磨面
に深さ0.2〜2μmの凹部2と凹部2の側縁2aに沿
って基板端部に開口する溝3を形成する。
[Second Embodiment] FIG. 4 shows the manufacturing process of a second embodiment of the present invention. In this embodiment, the steps in FIG. 4 (a>(b)) are the same as in the first embodiment, and a recess 2 with a depth of 0.2 to 2 μm is formed on the mirror-polished surface of the N-type first semiconductor substrate 1. A groove 3 is formed along the side edge 2a of the recess 2 and opens at the end of the substrate.

次に、(C)の工程で、この第1半導体基板1と、少な
くとも一方の面を鏡面研磨したN 型第2半導体基板5
とを、第1実施例と同様の方法で洗浄、表面処理した後
、接着しない状態で真空容器6内に入れ、真空ポンプ6
1により真空容器6内を排気する。真空バルブ62は開
、真空バルブ63は閉とする。到達真空度は、前述の如
<10Pa以下とすることが望ましい。しかる後、真空
バルブ62を閉じて、真空バルブ63を開け、高純度の
02ガスあるいはH2,0,2混合ガスを容器に充填す
る。このとき容器6内の圧力は大気圧以上が望ましい。
Next, in the step (C), this first semiconductor substrate 1 and an N-type second semiconductor substrate 5 whose at least one surface has been mirror-polished
After washing and surface treating the same in the same manner as in the first embodiment, they were placed in a vacuum container 6 without being bonded, and the vacuum pump 6
1, the inside of the vacuum container 6 is evacuated. The vacuum valve 62 is open and the vacuum valve 63 is closed. The ultimate degree of vacuum is desirably <10 Pa or less as described above. Thereafter, the vacuum valve 62 is closed, the vacuum valve 63 is opened, and the container is filled with high purity 02 gas or H2,0,2 mixed gas. At this time, the pressure inside the container 6 is preferably at least atmospheric pressure.

この状態で2枚の基板1.5の鏡面1a、5aどうしを
密着させる。これにより、2枚の基板1.5は表面に形
成されたシラノール基および表面に吸着した水分子の水
素結合により接着し、第1半導体基板1の凹部2と第2
半導体基板5の表面5aとで形成される空洞部内は高純
度の酸化性ガスが充填された状態となる。
In this state, the mirror surfaces 1a and 5a of the two substrates 1.5 are brought into close contact with each other. As a result, the two substrates 1.5 are bonded together by hydrogen bonds between the silanol groups formed on the surfaces and the water molecules adsorbed on the surfaces, and the recesses 2 of the first semiconductor substrate 1 and the second substrate 1.5 are bonded together.
The cavity formed by the surface 5a of the semiconductor substrate 5 is filled with highly pure oxidizing gas.

そして第4図(d)において、速やかにこの接合基板1
0を800°C以上に加熱可能なヒータ71を有する熱
処理容器7に入れ、例えばドライo2、ウェット02,
82.02混合燃焼気体等の酸化性雰囲気中で800°
C以上、1時間以上の熱処理を施し、溝3表面および空
洞部4内を酸化して、酸化膜11を形成する。この場合
も第1実施例同様、空洞部4が酸化膜11によって完全
に埋設、充填されるまで最低行なう。
Then, in FIG. 4(d), this bonded substrate 1 is immediately
For example, dry O2, wet O2,
82.02 800° in an oxidizing atmosphere such as mixed combustion gas
A heat treatment is performed for one hour or more at a temperature of C or more to oxidize the surface of the groove 3 and the inside of the cavity 4 to form an oxide film 11. In this case, as in the first embodiment, the process is continued until the cavity 4 is completely buried and filled with the oxide film 11.

続いて第4図(e)の工程で、基板1の表面1bに溝3
を開口させ、第1図(f)において多結晶シリコン13
を堆積させる。
Subsequently, in the step shown in FIG. 4(e), grooves 3 are formed on the surface 1b of the substrate 1.
In FIG. 1(f), the polycrystalline silicon 13 is opened.
deposit.

本実施例においても、高純度の酸化性ガスで充填した状
態で熱処理するため、第1実施例同様、極めて短時間で
空洞部4内に酸化膜11を埋設することが可能である。
In this embodiment as well, since the heat treatment is performed in a state filled with high-purity oxidizing gas, it is possible to embed the oxide film 11 in the cavity 4 in an extremely short time, as in the first embodiment.

上記第1、第2実施例においては、基板1.5の組み合
わせとしてN−型基板とN+型基板の場合で説明したが
、これらの基板の濃度は任意であり、異なる伝導型であ
ってもよい。
In the first and second embodiments described above, the combination of the substrates 1.5 is an N- type substrate and an N+ type substrate, but the concentration of these substrates can be arbitrary, and even if they are of different conductivity types. good.

さらに、これらの基板の一部分あるいは全面に不純物を
拡散させたものや、2枚以上の基板を接合した基板を用
いてもよい。従って、任意の基板で形成可能であるなめ
、従来のエピタキシャル法では得られないような低い不
純物濃度で厚い低濃度層の形成が可能で、素子の高耐圧
化にも容易に対応できる。
Furthermore, it is also possible to use a substrate in which impurities are diffused in a part or the entire surface of these substrates, or a substrate in which two or more substrates are bonded together. Therefore, since it can be formed on any substrate, it is possible to form a thick, low-concentration layer with a low impurity concentration that cannot be obtained by conventional epitaxial methods, and it can easily correspond to higher breakdown voltages of devices.

また、第1実施例において形成される素子は絶縁ゲート
型素子で示したが、これに限るものではなく、例えばダ
イオード、バイポーラ素子、サイリスク等の素子でもよ
い。
Further, although the element formed in the first embodiment is an insulated gate type element, the present invention is not limited to this, and may be, for example, a diode, a bipolar element, a silice, or the like.

[発明の効果] 以上のように、本発明方法によれば、接合基板の空洞部
内に酸化系ガスを充填することにより、続く酸化処理に
おける酸化反応が円滑に進み、従来のように空洞部内に
未反応ガスが滞留して熱酸化膜の成長が阻害されること
がない。従って、酸化膜が均一にかつ短時間で成長し、
高耐圧の絶縁分離領域が容易に形成できるので、大口径
のウェハにも充分適用可能である。しかも埋設時間が極
めて短時間であるので、半導体基板に対する熱負荷が小
さく、基板内の欠陥発生が少なくなり、不良率を著しく
低減することができる。
[Effects of the Invention] As described above, according to the method of the present invention, by filling the cavity of the bonded substrate with an oxidizing gas, the oxidation reaction in the subsequent oxidation treatment proceeds smoothly, and the process of filling the cavity in the cavity as in the conventional method Growth of the thermal oxide film is not inhibited due to accumulation of unreacted gas. Therefore, the oxide film grows uniformly and in a short time,
Since an insulating isolation region with high breakdown voltage can be easily formed, it is fully applicable to large-diameter wafers. Moreover, since the embedding time is extremely short, the heat load on the semiconductor substrate is small, the occurrence of defects in the substrate is reduced, and the defect rate can be significantly reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は本発明の一実施例を示し、第1図(a
)〜(g>は半導体装置の製造工程を示す断面図、第2
図は熱処理時間と空洞部埋設率の関係を示す図、第3図
は本実施例の工程により製造された半導体装置の断面図
であり、第4図(a)〜(f>は本発明の第2の実施例
の製造工程を示す断面図である。 1・・・・・・第1半導体基板 1a・・・・・・鏡面 2・・・・・・凹部 4・・・・・・空洞部 5・・・・・・第2半導体基板 5a・・・・・・鏡面 6・・・・・・真空容器 7・・・・・・熱処理容器 10・・・・・・接合基板 第1図 (a) (b) (C) (d) 第1 図 (e) (f) 第2図 本 実 施 例 熱 処 理 時 間 (hr ) 第4図 (a) (b) (C) a
1 to 3 show an embodiment of the present invention, and FIG.
) to (g> are cross-sectional views showing the manufacturing process of the semiconductor device, the second
The figure shows the relationship between heat treatment time and cavity filling rate, FIG. 3 is a cross-sectional view of a semiconductor device manufactured by the process of this example, and FIGS. It is a cross-sectional view showing the manufacturing process of the second example. 1... First semiconductor substrate 1a... Mirror surface 2... Concavity 4... Cavity Part 5...Second semiconductor substrate 5a...Mirror surface 6...Vacuum container 7...Heat treatment container 10...Bonded substrate Fig. 1 (a) (b) (C) (d) Fig. 1 (e) (f) Fig. 2 Heat treatment time of this example (hr) Fig. 4 (a) (b) (C) a

Claims (2)

【特許請求の範囲】[Claims] (1)少なくとも一方の面が鏡面研磨された第1半導体
基板の鏡面に凹部を形成し、この凹部の側縁に沿って凹
部より深い酸化性ガス導入用の溝部を形成する工程と、 第1半導体基板の上記鏡面と、少なくとも一方の面が鏡
面研磨された第2半導体基板の鏡面とを直接接合する工
程と、 得られた接合基板を真空引きした後、第1半導体基板の
上記凹部と第2半導体基板とで形成される空洞部内に、
上記溝部を介して高純度の酸化性ガスを充填する工程と
、 この接合基板を酸化性ガス雰囲気中で熱処理することに
よつて上記空洞部内に酸化膜を埋設する工程とを有する
ことを特徴とする半導体装置の製造方法。
(1) forming a recess in the mirror surface of a first semiconductor substrate, at least one surface of which has been mirror-polished, and forming a groove for introducing an oxidizing gas deeper than the recess along the side edge of the recess; a step of directly bonding the mirror surface of the semiconductor substrate to the mirror surface of a second semiconductor substrate whose at least one surface has been mirror-polished; In the cavity formed by the two semiconductor substrates,
The method comprises the steps of filling a high-purity oxidizing gas through the groove, and embedding an oxide film in the cavity by heat-treating the bonded substrate in an oxidizing gas atmosphere. A method for manufacturing a semiconductor device.
(2)少なくとも一方の面が鏡面研磨された第1半導体
基板の鏡面に凹部を形成し、この凹部の側縁に沿って凹
部より深い酸化性ガス導入用の溝部を形成する工程と、 上記第1半導体基板と、少なくとも一方の面が鏡面研磨
された第2半導体基板とを高純度の酸化性ガス雰囲気中
に配置し、鏡面どうしを密着させて直接接合すると同時
に、第1半導体基板の上記凹部と第2半導体基板とで形
成される空洞部内に高純度の酸化性ガスを充填する工程
と、 得られた接合基板を酸化性ガス雰囲気中で熱処理するこ
とによって上記空洞部内に酸化膜を埋設する工程とを有
することを特徴とする半導体装置の製造方法。
(2) forming a recess in the mirror surface of the first semiconductor substrate, at least one surface of which has been mirror-polished, and forming a groove for introducing an oxidizing gas deeper than the recess along the side edge of the recess; A first semiconductor substrate and a second semiconductor substrate whose at least one surface is mirror-polished are placed in a high-purity oxidizing gas atmosphere, and the mirror surfaces are brought into close contact with each other and directly bonded. and a step of filling a high-purity oxidizing gas into a cavity formed by the first semiconductor substrate and the second semiconductor substrate, and embedding an oxide film in the cavity by heat-treating the obtained bonded substrate in an oxidizing gas atmosphere. A method for manufacturing a semiconductor device, comprising the steps of:
JP21225790A 1990-08-09 1990-08-09 Method for manufacturing semiconductor device Expired - Lifetime JP2841780B2 (en)

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Publication number Priority date Publication date Assignee Title
JP2009066864A (en) * 2007-09-12 2009-04-02 Mimaki Engineering Co Ltd Ink-jet printer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009066864A (en) * 2007-09-12 2009-04-02 Mimaki Engineering Co Ltd Ink-jet printer

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