EP0916156B1 - Method of manufacturing a semiconductor device having "shallow trench isolation" - Google Patents

Method of manufacturing a semiconductor device having "shallow trench isolation" Download PDF

Info

Publication number
EP0916156B1
EP0916156B1 EP98903262A EP98903262A EP0916156B1 EP 0916156 B1 EP0916156 B1 EP 0916156B1 EP 98903262 A EP98903262 A EP 98903262A EP 98903262 A EP98903262 A EP 98903262A EP 0916156 B1 EP0916156 B1 EP 0916156B1
Authority
EP
European Patent Office
Prior art keywords
silicon
oxide
deposited
silicon oxide
densified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP98903262A
Other languages
German (de)
French (fr)
Other versions
EP0916156A1 (en
Inventor
Pierre Hermanus Woerlee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP98903262A priority Critical patent/EP0916156B1/en
Publication of EP0916156A1 publication Critical patent/EP0916156A1/en
Application granted granted Critical
Publication of EP0916156B1 publication Critical patent/EP0916156B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Definitions

  • the invention relates to a method of manufacturing a semiconductor device, in which method trenches are formed in a surface of a silicon body the trenches are filled with silicon oxide which is deposited from the gas phase and, subsequently, the silicon oxide is densified by means of a thermal treatment in a nitrogen-containing atmosphere.
  • the silicon-oxide-filled trenches are used as field-isolation regions enclosing active regions.
  • semiconductor elements such as MOS-transistors and EPROM-cells can be formed. This manner of isolating active regions from each other is referred to as "shallow trench isolation".
  • the silicon oxide can be deposited from the gas phase in various, conventional ways.
  • the gas phase may comprise, for example, tetraethoxy silane (TEOS) or a gas mixture containing, for example, silane and oxygen, and the deposition operation can be carried out at atmospheric or sub-atmospheric pressure. It is also possible to accelerate the deposition process by means of a plasma.
  • TEOS tetraethoxy silane
  • a gas mixture containing, for example, silane and oxygen it is also possible to accelerate the deposition process by means of a plasma.
  • a "High Density Plasma Chemical Vapor Deposition" process a layer of silicon oxide can be deposited at a low temperature, for example, of 400 °C. Silicon oxides formed by deposition can very easily be etched in customary hydrogen-fluoride etching baths. They are etched at a much higher rate than silicon oxides formed by thermal oxidation of silicon. This causes practical problems in the manufacture of semiconductor devices. This is the reason why, in practice
  • the deposited silicon oxide can be densified such that it is etched almost as rapidly in customary etching baths with hydrogen fluoride as is silicon oxide formed by thermal oxidation.
  • said oxidation of the side walls of the trenches does not take place so that the formation of crystal defects during densification is precluded.
  • the thermal treatment takes up far too much time.
  • silicon wafers are treated one by one. For such "single wafer processing", a thermal treatment which takes 1 hour is unsuitable.
  • the method mentioned in the opening paragraph is characterized in that the deposited silicon oxide is densified in an NO or N 2 O-containing atmosphere.
  • the deposited-silicon oxide is densified by subjecting the silicon body in an NO or N 2 O-containing atmosphere to a thermal treatment at a temperature of 1000 to 1150 °C for 0.5 to 3 minutes.
  • the etching rate of the resultant, densified silicon oxide in hydrogen-fluoride etching baths is similar to that of silicon oxide formed by thermal oxidation.
  • the deposited silicon oxide is densified by heating the silicon body in an NO or N 2 O-containing atmosphere at a pressure of 1 atmosphere.
  • the deposited silicon oxide can then be densified in a customary "rapid thermal processing" reactor.
  • Fig. 1 is a schematic, cross-sectional view of a silicon body 1 having a surface 2 on which an approximately 10 nm thick layer of silicon oxide 3 and an approximately 150 nm thick layer of silicon nitride 4 are formed by thermal oxidation and deposition, respectively.
  • a photoresist mask 5 is formed in a customary manner on the silicon-nitride layer 4. This photoresist mask 5 covers the silicon-nitride layer 4 at the locations where active regions 13 must be formed in the silicon body, and is provided with windows 6, within which the layer of silicon nitride 4 is exposed, at the locations where field-oxide regions 12 must be formed in the silicon body 1.
  • the semiconductor body 1 is subjected to a customary etching treatment.
  • this treatment as shown in Fig. 2, the parts of the silicon-nitride layer 4 and the silicon-oxide layer 3 situated within the windows 6 of the photoresist mask 5 are removed from the surface 2, and trenches 7 having a depth of approximately 400 nm and a width of approximately 500 nm are formed in the silicon body 1.
  • a thick layer of silicon oxide 11 is deposited.
  • the silicon-oxide layer 11 is deposited in such a thickness that the trenches 7 are completely filled with silicon oxide. In this example, said thickness is approximately 750 nm.
  • the silicon-oxide layer 11 can be deposited from the gas phase in various, customary ways.
  • the gas phase may comprise, for example, tetraethoxy silane (TEOS) or a gas mixture containing, for example, silane and oxygen, and the deposition process may be carried out at atmospheric or sub-atmospheric pressure. It is also possible to accelerate the deposition process by means of a plasma.
  • TEOS tetraethoxy silane
  • a "High Density Plasma Chemical Vapor Deposition" process can be used to deposit a layer of silicon oxide at a low temperature, for example, of 400 °C.
  • the silicon-oxide layer 11 is subjected to a customary chemical-mechanical polishing treatment. This treatment is continued until the layer of silicon nitride 4 is exposed. Thus, the trenches 7 are filled with silicon oxide. Subsequently, the silicon-nitride layer 4 and the silicon-oxide layer 3 are removed, resulting in the formation of field-oxide regions 12 which enclose the active regions 13 of the semiconductor body 1.
  • the surface 2 of the active regions 13 is cleaned.
  • a thermal-oxidation operation is carried out in which an approximately 200 nm thick layer of silicon oxide 14 as shown in Fig. 6 is formed, which is subsequently etched away again in a hydrogen-fluoride etching solution.
  • the silicon-oxide layer 14 is a layer of "sacrificial oxide".
  • etching away of the silicon-oxide layer 14 a layer of the deposited and subsequently polished oxide 11 of the field-oxide regions 12 is also etched away.
  • Deposition-formed silicon oxides are readily etched in customary hydrogen-fluoride etching baths. They are etched much more rapidly than silicon oxides formed by thermal oxidation of silicon. This causes practical problems in the manufacture of semiconductor devices.
  • the silicon-oxide layer 11 formed by deposition which is used to form field-oxide regions 12, could be subject, for example during etching away the "sacrificial oxide" layer 14 formed by thermal oxidation, to a very strong etching effect. To ensure that the flat structure shown in Fig. 7 is obtained, the deposited silicon-oxide layer 11 is densified by means of a thermal treatment prior to the chemical-mechanical polishing treatment.
  • the rate at which the deposited silicon-oxide layer 11 is etched in a hydrogen-fluoride bath is almost equal to that of a silicon-oxide layer formed by thermal oxidation, such as the "sacrificial oxide” layer 14.
  • a silicon-oxide layer formed by thermal oxidation such as the "sacrificial oxide” layer 14.
  • this "sacrificial oxide” layer only a very thin layer of the deposited and polished silicon-oxide layer 11 is etched away. In this manner, the flat structure shown in Fig. 7 is obtained.
  • the deposited silicon oxide 11 is densified in an NO or N 2 O-containing atmosphere.
  • an NO or N 2 O-containing atmosphere In practice it has been found that by carrying out the densification operation in an NO or N 2 O-containing atmosphere, said densification can be realized in a very short period of time and, in addition, the thermal treatment does not cause crystal defects.
  • the silicon side walls of the trenches are nitrided and oxidation of the side walls during densification of the deposited oxide does not take place. Said oxidation would take place if the densification is carried out by means of a thermal treatment in vapor. Apart from the densification of the deposited oxide, oxidation of the side walls of the trenches would take place.
  • the formation of this silicon oxide whose volume is larger than that of the silicon from which it is formed, causes stresses. Such stresses may cause crystal defects which may give rise to leakage currents in semiconductor elements formed in the active regions.
  • the deposited silicon oxide 11 is densified by heating the silicon body in an NO or N 2 O-containing atmosphere for 0.5 to 3 minutes at a temperature in the range from 1000 to 1150 °C.
  • the etching rate of the densified silicon oxide in hydrogen-fluoride etching baths is similar to that of silicon oxide formed by thermal oxidation.
  • the high temperature also mechanical stresses induced in the deposited silicon oxide during deposition are completely relaxed.
  • semiconductor elements in this example MOS transistors, are formed in the active regions.
  • the active regions 12 are then provided with a desired dopant 16 whereafter an approximately 10 nm thick gate-oxide layer 16 is formed by thermal oxidation on the active regions 12.
  • gate electrodes 18 are formed in a customary manner from polycrystalline silicon by means of ion-implantation source and drain zones 19, and said gate electrodes 18 are provided with an edge isolation 20 for example in the form of spacers of silicon oxide.
  • MOS-transistors semiconductor elements other than MOS-transistors can be formed in the active regions 12.
  • integrated circuits may also comprise, for example, memory elements, such as EPROM-cells, and also, for example, bipolar transistors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method of manufacturing semiconductor device, in which trenches (7) are formed in a surface (2) of a silicon body (1), which trenches are filled with silicon oxide (11). The filled trenches are used as field-oxide regions (12) in integrated circuits. The silicon oxide is deposited from a gas phase and is subsequently densified by means of a thermal treatment in an NO or N2O-containing atmosphere. The deposited silicon oxide can be densified in a very short period of time, and, in addition, the thermal treatment does not cause crystal defects. The method can suitably be used for 'single wafer processing'.

Description

The invention relates to a method of manufacturing a semiconductor device, in which method trenches are formed in a surface of a silicon body the trenches are filled with silicon oxide which is deposited from the gas phase and, subsequently, the silicon oxide is densified by means of a thermal treatment in a nitrogen-containing atmosphere.
In practice, the silicon-oxide-filled trenches are used as field-isolation regions enclosing active regions. In the active regions thus isolated from each other, semiconductor elements, such as MOS-transistors and EPROM-cells can be formed. This manner of isolating active regions from each other is referred to as "shallow trench isolation".
The silicon oxide can be deposited from the gas phase in various, conventional ways. The gas phase may comprise, for example, tetraethoxy silane (TEOS) or a gas mixture containing, for example, silane and oxygen, and the deposition operation can be carried out at atmospheric or sub-atmospheric pressure. It is also possible to accelerate the deposition process by means of a plasma. Using a "High Density Plasma Chemical Vapor Deposition" process, a layer of silicon oxide can be deposited at a low temperature, for example, of 400 °C. Silicon oxides formed by deposition can very easily be etched in customary hydrogen-fluoride etching baths. They are etched at a much higher rate than silicon oxides formed by thermal oxidation of silicon. This causes practical problems in the manufacture of semiconductor devices. This is the reason why, in practice, deposition-formed silicon oxides which are used to form field-oxide regions are densified by means of a thermal treatment.
From "An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI)", H.S. Lee et al., Digest of Technical Papers of the IEEE Symposium on VLSI Technology, 1996, pp. 158-159, a method of the type mentioned in the opening paragraph is known, in which the densification of silicon oxide formed by deposition is carried out by means of a thermal treatment in nitrogen. In this process, the silicon body is heated for 1 hour at a temperature of 1150 °C. By carrying out the thermal treatment in nitrogen, oxidation of the silicon situated next to the trenches during the thermal treatment is precluded. Oxidation could lead to mechanical stresses in the silicon. This would be the case if the densification operation is carried out by means of a thermal treatment in vapor. Apart from the densification of the deposited oxide, the side walls of the trenches are also oxidized in said operation. The formation of this silicon oxide, whose volume is larger than that of the silicon from which it is formed, causes said stresses. Such stresses may cause crystal defects which may give rise to leakage currents in semiconductor elements formed in the active regions.
By heating it in nitrogen, the deposited silicon oxide can be densified such that it is etched almost as rapidly in customary etching baths with hydrogen fluoride as is silicon oxide formed by thermal oxidation. In this case, said oxidation of the side walls of the trenches does not take place so that the formation of crystal defects during densification is precluded. For practical applications, however, the thermal treatment takes up far too much time. In current processes for the manufacture of highly-integrated semiconductor devices (VLSI), silicon wafers are treated one by one. For such "single wafer processing", a thermal treatment which takes 1 hour is unsuitable.
It is an object of the invention to provide a method in which silicon oxide deposited in the trenches can be densified in a much shorter period of time, and which method can consequently be used in the manufacture of semiconductor devices by means of "single wafer processing".
To achieve this, the method mentioned in the opening paragraph is characterized in that the deposited silicon oxide is densified in an NO or N2O-containing atmosphere.
In practice it has been found that by carrying out the densification operation in an NO or N2O-containing atmosphere, said densification can be realized in a very short time period, and, in addition, the thermal treatment does not lead to crystal defects. When use is made of an NO or N2O-containing atmosphere, the silicon side walls of the trenches are nitrided and oxidation of the side walls during densification of the deposited oxide does not take place.
Preferably, the deposited-silicon oxide is densified by subjecting the silicon body in an NO or N2O-containing atmosphere to a thermal treatment at a temperature of 1000 to 1150 °C for 0.5 to 3 minutes. The etching rate of the resultant, densified silicon oxide in hydrogen-fluoride etching baths is similar to that of silicon oxide formed by thermal oxidation. By virtue of said high temperature, also mechanical stresses induced in the deposited silicon oxide during deposition are completely relaxed.
In addition, preferably, the deposited silicon oxide is densified by heating the silicon body in an NO or N2O-containing atmosphere at a pressure of 1 atmosphere. The deposited silicon oxide can then be densified in a customary "rapid thermal processing" reactor.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
In the drawings:
  • Figs. 1 through 8 are schematic, cross-sectional views of a few stages in the manufacture of a semiconductor device using the method in accordance with the invention.
    • Fig. 1 is a schematic, cross-sectional view of a silicon body 1 having a surface 2 on which an approximately 10 nm thick layer of silicon oxide 3 and an approximately 150 nm thick layer of silicon nitride 4 are formed by thermal oxidation and deposition, respectively. A photoresist mask 5 is formed in a customary manner on the silicon-nitride layer 4. This photoresist mask 5 covers the silicon-nitride layer 4 at the locations where active regions 13 must be formed in the silicon body, and is provided with windows 6, within which the layer of silicon nitride 4 is exposed, at the locations where field-oxide regions 12 must be formed in the silicon body 1.
    Subsequently, the semiconductor body 1 is subjected to a customary etching treatment. In this treatment, as shown in Fig. 2, the parts of the silicon-nitride layer 4 and the silicon-oxide layer 3 situated within the windows 6 of the photoresist mask 5 are removed from the surface 2, and trenches 7 having a depth of approximately 400 nm and a width of approximately 500 nm are formed in the silicon body 1. After the walls 8 and the bottom 9 of the grooves 7 have been provided with an approximately 10 nm thick layer of silicon oxide 10 formed by thermal oxidation, a thick layer of silicon oxide 11, as shown in Fig. 3, is deposited. The silicon-oxide layer 11 is deposited in such a thickness that the trenches 7 are completely filled with silicon oxide. In this example, said thickness is approximately 750 nm.
    The silicon-oxide layer 11 can be deposited from the gas phase in various, customary ways. The gas phase may comprise, for example, tetraethoxy silane (TEOS) or a gas mixture containing, for example, silane and oxygen, and the deposition process may be carried out at atmospheric or sub-atmospheric pressure. It is also possible to accelerate the deposition process by means of a plasma. A "High Density Plasma Chemical Vapor Deposition" process can be used to deposit a layer of silicon oxide at a low temperature, for example, of 400 °C.
    Subsequently, as shown in Fig. 4, the silicon-oxide layer 11 is subjected to a customary chemical-mechanical polishing treatment. This treatment is continued until the layer of silicon nitride 4 is exposed. Thus, the trenches 7 are filled with silicon oxide. Subsequently, the silicon-nitride layer 4 and the silicon-oxide layer 3 are removed, resulting in the formation of field-oxide regions 12 which enclose the active regions 13 of the semiconductor body 1.
    Subsequently, the surface 2 of the active regions 13 is cleaned. For this purpose, a thermal-oxidation operation is carried out in which an approximately 200 nm thick layer of silicon oxide 14 as shown in Fig. 6 is formed, which is subsequently etched away again in a hydrogen-fluoride etching solution. The silicon-oxide layer 14 is a layer of "sacrificial oxide". During etching away of the silicon-oxide layer 14, a layer of the deposited and subsequently polished oxide 11 of the field-oxide regions 12 is also etched away.
    Deposition-formed silicon oxides are readily etched in customary hydrogen-fluoride etching baths. They are etched much more rapidly than silicon oxides formed by thermal oxidation of silicon. This causes practical problems in the manufacture of semiconductor devices. The silicon-oxide layer 11 formed by deposition, which is used to form field-oxide regions 12, could be subject, for example during etching away the "sacrificial oxide" layer 14 formed by thermal oxidation, to a very strong etching effect. To ensure that the flat structure shown in Fig. 7 is obtained, the deposited silicon-oxide layer 11 is densified by means of a thermal treatment prior to the chemical-mechanical polishing treatment. As a result thereof, the rate at which the deposited silicon-oxide layer 11 is etched in a hydrogen-fluoride bath is almost equal to that of a silicon-oxide layer formed by thermal oxidation, such as the "sacrificial oxide" layer 14. During etching away this "sacrificial oxide" layer, only a very thin layer of the deposited and polished silicon-oxide layer 11 is etched away. In this manner, the flat structure shown in Fig. 7 is obtained.
    The deposited silicon oxide 11 is densified in an NO or N2O-containing atmosphere. In practice it has been found that by carrying out the densification operation in an NO or N2O-containing atmosphere, said densification can be realized in a very short period of time and, in addition, the thermal treatment does not cause crystal defects. When use is made of an NO or N2O-containing atmosphere, the silicon side walls of the trenches are nitrided and oxidation of the side walls during densification of the deposited oxide does not take place. Said oxidation would take place if the densification is carried out by means of a thermal treatment in vapor. Apart from the densification of the deposited oxide, oxidation of the side walls of the trenches would take place. The formation of this silicon oxide, whose volume is larger than that of the silicon from which it is formed, causes stresses. Such stresses may cause crystal defects which may give rise to leakage currents in semiconductor elements formed in the active regions.
    Preferably, the deposited silicon oxide 11 is densified by heating the silicon body in an NO or N2O-containing atmosphere for 0.5 to 3 minutes at a temperature in the range from 1000 to 1150 °C. As a result, the etching rate of the densified silicon oxide in hydrogen-fluoride etching baths is similar to that of silicon oxide formed by thermal oxidation. By virtue of the high temperature, also mechanical stresses induced in the deposited silicon oxide during deposition are completely relaxed.
    Preferably, the deposited silicon oxide 11 is subsequently densified by heating the silicon body in an NO or N2O-containing atmosphere at a pressure of 1 atmosphere (1 atmosphere = 1.013 x 105 Pa). Densification of the deposited silicon oxide can then be carried out in a customary "rapid thermal processing" reactor.
    After removal of the "sacrificial oxide" layer, semiconductor elements, in this example MOS transistors, are formed in the active regions. The active regions 12 are then provided with a desired dopant 16 whereafter an approximately 10 nm thick gate-oxide layer 16 is formed by thermal oxidation on the active regions 12. Subsequently, gate electrodes 18 are formed in a customary manner from polycrystalline silicon by means of ion-implantation source and drain zones 19, and said gate electrodes 18 are provided with an edge isolation 20 for example in the form of spacers of silicon oxide.
    Of course, also semiconductor elements other than MOS-transistors can be formed in the active regions 12. Apart from MOS-transistors, integrated circuits may also comprise, for example, memory elements, such as EPROM-cells, and also, for example, bipolar transistors.

    Claims (3)

    1. A method of manufacturing a semiconductor device, in which method trenches are formed in a surface of a silicon body the trenches are filled with silicon oxide which is deposited from the gas phase and, subsequently, the silicon oxide is densified by means of a thermal treatment in a nitrogen-containing atmosphere, characterized in that the deposited silicon oxide is densified in an NO or N2O-containing atmosphere.
    2. A method as claimed in claim 1, characterized in that the deposited silicon oxide is densified by subjecting the silicon body to a thermal treatment at a temperature of 1000 to 1150 °C for 0.5 to 3 minutes in the NO or N2O-containing atmosphere.
    3. A method as claimed in claim 2, characterized in that the deposited silicon oxide is densified by heating the silicon body in the NO or N2O-containing atmosphere at a pressure of 1.013 x 105 Pa (1 atmosphere).
    EP98903262A 1997-04-07 1998-03-05 Method of manufacturing a semiconductor device having "shallow trench isolation" Expired - Lifetime EP0916156B1 (en)

    Priority Applications (1)

    Application Number Priority Date Filing Date Title
    EP98903262A EP0916156B1 (en) 1997-04-07 1998-03-05 Method of manufacturing a semiconductor device having "shallow trench isolation"

    Applications Claiming Priority (4)

    Application Number Priority Date Filing Date Title
    EP97201020 1997-04-07
    EP97201020 1997-04-07
    EP98903262A EP0916156B1 (en) 1997-04-07 1998-03-05 Method of manufacturing a semiconductor device having "shallow trench isolation"
    PCT/IB1998/000281 WO1998045877A1 (en) 1997-04-07 1998-03-05 Method of manufacturing a semiconductor device having 'shallow trench isolation'

    Publications (2)

    Publication Number Publication Date
    EP0916156A1 EP0916156A1 (en) 1999-05-19
    EP0916156B1 true EP0916156B1 (en) 2004-06-09

    Family

    ID=26146336

    Family Applications (1)

    Application Number Title Priority Date Filing Date
    EP98903262A Expired - Lifetime EP0916156B1 (en) 1997-04-07 1998-03-05 Method of manufacturing a semiconductor device having "shallow trench isolation"

    Country Status (2)

    Country Link
    EP (1) EP0916156B1 (en)
    WO (1) WO1998045877A1 (en)

    Family Cites Families (3)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    KR970009863B1 (en) * 1994-01-22 1997-06-18 금성일렉트론 주식회사 Forming method of insulated film in the semiconductor device
    JPH09162185A (en) * 1995-12-05 1997-06-20 Mitsubishi Electric Corp Fabrication of semiconductor device
    US5939763A (en) * 1996-09-05 1999-08-17 Advanced Micro Devices, Inc. Ultrathin oxynitride structure and process for VLSI applications

    Also Published As

    Publication number Publication date
    EP0916156A1 (en) 1999-05-19
    WO1998045877A1 (en) 1998-10-15

    Similar Documents

    Publication Publication Date Title
    US6118168A (en) Trench isolation process using nitrogen preconditioning to reduce crystal defects
    US5989978A (en) Shallow trench isolation of MOSFETS with reduced corner parasitic currents
    US6759302B1 (en) Method of generating multiple oxides by plasma nitridation on oxide
    US4561172A (en) Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
    EP0428283A2 (en) Method for local oxidation of silicon
    EP0129265B1 (en) Methods of manufacturing semiconductor devices with reduction in the charge carrier trap density
    JPH06314777A (en) Manufacture of semiconductor device
    JPH09321132A (en) Separating semiconductor device trench elements
    US4538343A (en) Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
    US20030027402A1 (en) Method for reducing stress of sidewall oxide layer of shallow trench isolation
    US5966616A (en) Method of manufacturing a semiconductor device having "shallow trench isolation"
    US5371036A (en) Locos technology with narrow silicon trench
    KR100419689B1 (en) Method for forming a liner in a trench
    US6670690B1 (en) Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages
    US6503815B1 (en) Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation
    EP0916156B1 (en) Method of manufacturing a semiconductor device having "shallow trench isolation"
    US5998277A (en) Method to form global planarized shallow trench isolation
    KR100381493B1 (en) Semiconductor device and manufacturing method thereof
    KR100478367B1 (en) Method of manufacturing a semiconductor device having "shallow trench isolation"
    US20030008474A1 (en) Method of forming shallow trench isolation
    US20030027403A1 (en) Method for forming sacrificial oxide layer
    US20030194870A1 (en) Method for forming sidewall oxide layer of shallow trench isolation with reduced stress and encroachment
    KR100257764B1 (en) Semiconductor device and manufacturing method
    KR100376875B1 (en) Method for forming isolation layer in semiconductor device
    US20060030118A1 (en) Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolation material

    Legal Events

    Date Code Title Description
    PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

    Free format text: ORIGINAL CODE: 0009012

    AK Designated contracting states

    Kind code of ref document: A1

    Designated state(s): DE FR GB IT NL

    17P Request for examination filed

    Effective date: 19990415

    GRAP Despatch of communication of intention to grant a patent

    Free format text: ORIGINAL CODE: EPIDOSNIGR1

    GRAS Grant fee paid

    Free format text: ORIGINAL CODE: EPIDOSNIGR3

    GRAA (expected) grant

    Free format text: ORIGINAL CODE: 0009210

    AK Designated contracting states

    Kind code of ref document: B1

    Designated state(s): DE FR GB IT NL

    PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

    Ref country code: NL

    Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

    Effective date: 20040609

    Ref country code: IT

    Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

    Effective date: 20040609

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: FG4D

    REF Corresponds to:

    Ref document number: 69824368

    Country of ref document: DE

    Date of ref document: 20040715

    Kind code of ref document: P

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: 746

    Effective date: 20040630

    NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
    ET Fr: translation filed
    PLBE No opposition filed within time limit

    Free format text: ORIGINAL CODE: 0009261

    STAA Information on the status of an ep patent application or granted ep patent

    Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: D6

    26N No opposition filed

    Effective date: 20050310

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: 732E

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: 732E

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: TP

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: GC

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: 732E

    Free format text: REGISTERED BETWEEN 20090618 AND 20090624

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: GC

    PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

    Ref country code: FR

    Payment date: 20100324

    Year of fee payment: 13

    PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

    Ref country code: GB

    Payment date: 20100303

    Year of fee payment: 13

    PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

    Ref country code: DE

    Payment date: 20100312

    Year of fee payment: 13

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: 732E

    Free format text: REGISTERED BETWEEN 20101007 AND 20101013

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: GC

    REG Reference to a national code

    Ref country code: GB

    Ref legal event code: 732E

    Free format text: REGISTERED BETWEEN 20111013 AND 20111019

    GBPC Gb: european patent ceased through non-payment of renewal fee

    Effective date: 20110305

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: ST

    Effective date: 20111130

    PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

    Ref country code: FR

    Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

    Effective date: 20110331

    Ref country code: DE

    Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

    Effective date: 20111001

    REG Reference to a national code

    Ref country code: DE

    Ref legal event code: R119

    Ref document number: 69824368

    Country of ref document: DE

    Effective date: 20111001

    PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

    Ref country code: GB

    Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

    Effective date: 20110305

    REG Reference to a national code

    Ref country code: FR

    Ref legal event code: AU

    Effective date: 20120126