JPH0493987A - Graphic display device - Google Patents

Abstract

PURPOSE:To eliminate the need for the code conversion of drawing data and to improve the drawing performance by converting a color code given by a processor to data format which matches a frame buffer. CONSTITUTION:A look-up table (LUT) address control circuit 111 is provided. The circuit 111 converts display picture element information in color code format given by the processor into address data of an LUT 107 according to an operation mode prescribed in a color mode register 110 and the LUT 107 uses display picture element information as address information to output gradation codes individually by red, blue, and green. Then the frame buffer 104 is stored with the display picture element information in the format of gradation codes by the respective colors where planes from the LUT 107 are made to correspond to one bit of red, blue, or green. Then a dot shifter 106 converts the display picture element information, which is read out of the frame buffer 104, into picture element serial information, so the drawing performance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a graphic display device, and particularly to a display control section of a graphic display device.

[Conventional technology]

Conventionally, this type of device has been constructed of blocks as shown in FIG. The microprocessor 301 is a microprogram execution unit, the memory 302 is a microprogram and data storage unit, and the interface control unit 303 is a unit that controls the interface with a host device.

The frame buffer 304 is a part that stores display pixel information, and constructs data in the form of a color code in which each plane corresponds to one bit. frame buffer 30
The display pixel information read out from the dot shifter 30
B is converted into pixel serial information. The output of the dot shifter 306 is a color palette 307, which outputs color gradation data as address information. This color
Palette 307 is a table memory having entries corresponding to the number of planes of frame buffer 304. The digital color gradation data output by the color palette 307 is converted into analog data by the D/A converter 308.
converted into a video signal. A display synchronization circuit 305 controls readout of the frame buffer 304 and also controls CR.
Generates a synchronization signal for T display. CRT display section 309
The deflection is controlled by a synchronization signal provided from a display synchronization circuit 305, and the analog video signal provided from a D/A converter 308 is displayed on a cathode ray tube.

[Problem to be solved by the invention]

The conventional graphic display device described above has a color per pixel.
When drawing data with different code bit numbers coexist on the screen, the processor must convert the drawing data to match the frame buffer configuration, which has the disadvantage of reducing drawing performance. .

[Means to solve the problem]

The graphic display device of the present invention includes a frame buffer configured with multiple frames for each color that stores display pixel information in the form of individual gradation codes for red, blue, and green, and a color frame buffer for each pixel that a processor provides as display pixel information. A color mode register that sets the effective number of bits of the code, a look-up table address control circuit that converts the color code into the address data of the look-up table according to the settings of the color mode register, and a look-up table. The look-up table converts the address data output by the address control circuit into red, blue, and green color gradation hoods and outputs them as write data to the frame buffer, and the digital data output by the frame buffer. D/converts color gradation code to analog video signal
The display control section includes an A converter and a display synchronization circuit that controls display readout of the frame Q buffer and generates a synchronization signal for CRT display.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a graphic display device which is an embodiment of the present invention.

In FIG. 1, one embodiment of the present invention includes a microprocessor 101 that is a microprogram execution unit, a memory 102 that is a storage unit for microprograms and data, and an interface control unit that is a unit that controls interfaces with other devices. section 103 and display control sections 104 to 108, 110, and 111 that control the CR1 display section 109. The microprocessor 101 operates to interpret graphic display commands by executing a microprogram, develop display information into a pixel pattern in the form of a color code, and store the pixel pattern in the frame buffer 104 of the display control section.

The color mode register 110 is stored in the microprocessor 10.
1 is a register for setting the effective number of bits of a color code per pixel of drawing input data given as display pixel information, and defines the operation mode of the LUT address control circuit 111.

The LUT address control circuit 111 transfers display pixel information in the color code format provided by the processor to the LUT 10 according to the operation mode specified in the color mode register 110.
7 address and data.

LUT (Le Tsuku 9a Tsubu Urn Table) 107ct
The display pixel information output by the LUT address control circuit 111 is used as address information to output individual gradation codes for red, blue, and green.It is a table memory in which data can be written by a processor, and has 224 entries, each color having 8 bits. This is the data structure.

The frame buffer 104 is a multi-plane memory that stores display pixel information in the form of individual gradation codes for each color, in which each plane from the LUT 107 corresponds to one bit of red, blue, and green, and has M pixels x N lines. In order to achieve display performance of 224 simultaneous expression colors with a display resolution of M x N
Bits/plane: 8 planes each for red, blue, and green, total 2
It has a 4-plane configuration.

Dot shifter 106 converts display pixel information read from frame buffer 104 into pixel serial information.

The D/A converter 108 converts the digital color gradation data output from the dot shifter 106 into an analog video signal, and the display synchronization circuit 105 converts the digital color gradation data output from the dot shifter 106 into an analog video signal.
It controls the display readout of No. 4 and generates a synchronization signal for display synchronization.

The CRT display unit 109 is deflection-controlled by a synchronization signal provided from a display synchronization circuit 105, and is controlled by a D/A converter 108.
Analog video signals provided by the computer are displayed on a cathode ray tube.

FIG. 2 shows the operation of the LUT address control circuit 111.

In FIG. 2, the 16M color mode is the case where the effective number of bits of the color code per pixel is set to 24 bits in the color mode register 110, and the 256 color mode is the same as the 8-pit, monochrome mode. is set to 1 bit.

That is, for 16M color mode, the processor gives 60
~624 24-bit drawing input data is used as LUT
It is provided to LUT 107 as addresses AO to A23. In addition, in the case of the 256 color mode, the 8-bit drawing input data b18 to b23 are given as LUT addresses A16 to A23, and "O" is given to AO to A15 to the LUT 107.

In monochrome mode, the 1-bit drawing input data of b23 is LUT address A23, and AO to A22 are “0”.
” is given to the LUT 107.

Through the above operations, display pixel information in color code format provided by the processor is stored in LUT1 according to the mode.
07, each of red, blue, and green is converted into a data format compatible with the 8-plane frame buffer 104 and stored.

〔Effect of the invention〕

As explained above, in accordance with the effective number of bits of the color code per pixel set in the color mode register, the color code given by the processor as display pixel information is configured into 8 planes each for red, blue, and green. The frame of
By configuring the data format to be converted into a data format that matches the buffer and then stored, code conversion by the processor is not required when drawing data with different bit numbers of color codes per pixel are mixed on the screen, and as a result, This has the effect of improving drawing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a graphic display device which is an embodiment of the present invention, and FIG. 2 is a LUT address control circuit 1 shown in FIG.
FIG. 3 is a block diagram showing a conventional graphic display device. 101: Microprocessor, 102: Memory, 103
: Interface control unit, 104: Frame buffer, 105: Display synchronization circuit, 106: Dot shifter, 1
07: LUT, 108: D/A converter, 109: C
RT display section, 110: Color mode register, 111:
LUT address control circuit, 301: microprocessor, 302: memory, 303: interface control unit, 3
04 Niframe buffer, 305: Display synchronization circuit, 3
06: Dot shifter, 307: Color palette, 3
08: D/A converter, 309: CRT display section.

Claims (1)

[Claims] A frame buffer with multiple planes for each color that stores display pixel information in the form of individual gradation codes for each color in which each plane corresponds to 1 bit of red, blue, and green, and a frame buffer that stores display pixel information in the form of a gradation code for each color, each plane corresponding to 1 bit of red, blue, and green, and a frame buffer that stores display pixel information in the form of a gradation code for each color. a color mode register that sets the effective number of bits of the color code; and a look-up table address control circuit that converts display pixel information provided by the processor into look-up table address data according to the settings of the color mode register. and a look-up table that converts the address data provided by the look-up table address control circuit into red, blue, and green tone codes and outputs them as write data to the frame buffer; A D/A converter that converts the digital color gradation code output from the frame buffer into an analog video signal, and a display synchronization circuit that controls the display readout of the frame buffer and generates a synchronization signal for CRT display. A graphic display device comprising a display control section including: