JPH049384B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device. More specifically, a plurality of active layers are stacked in which functional elements such as transistors and conductive wires (hereinafter referred to as wiring) that connect them are integrated, and the functional elements and circuits integrated in different active layers are stacked. The present invention relates to a method of manufacturing a multilayer semiconductor device that is organically connected to each other.

FIG. 1 shows an example of the structure of a multilayer semiconductor device. In the figure, 10 is a supporting substrate such as a semiconductor or an insulator, 11 is a first active layer formed on the supporting substrate 10, and 21, 31, 41, 51, 6
1 and 71 are the second layer, third layer, fourth layer,...
...the (n-2)th layer, the (n-1)th layer, the nth active layer, 12 the substrate of the package on which the multilayer semiconductor device 1 is mounted, 13 the bonding pad, 1
4 is a bonding wire. Next, the manufacturing sequence of a conventionally known multilayer semiconductor device will be briefly explained using the same figure.

First, a first active layer 11 consisting of functional elements such as transistors and wiring is formed on the surface of a supporting substrate 10 made of semiconductor or the like using a well-known integrated circuit forming process. At this time, a process for bonding with the second layer active layer 21 to be created next is also performed. Next, an insulating film, a semiconductor film, etc. are sequentially formed on the first active layer 11. The most typical example of the semiconductor film is a silicon single crystal film obtained by crystallizing polysilicon by laser annealing or electron beam annealing. Next, functional elements such as transistors are integrated using the semiconductor film, and then these are connected to form the second active layer 21. In this case, if necessary, the first active layer 11
In addition to coupling the functional elements and circuits formed in the active layer 21 of the second layer and the active layer 21 with each other, a process for coupling with the circuit elements in the active layer 31 of the third layer to be formed next is also performed. Hereinafter, using a process similar to the process for creating the second layer active layer 21, the third layer, fourth layer, ... (n-2)th layer, (n-th layer), etc.
-1) layer, n-th active layer 31, 41,...51,
61 and 71 are sequentially created to form a multilayer semiconductor device 1.

Semiconductor devices manufactured in this way have not only a two-dimensional expansion but also a three-dimensional expansion in the vertical direction, so compared to well-known integrated circuits that only have a two-dimensional expansion, the semiconductor devices have higher integration density, functionality, signal processing ability, etc. is excellent. However, since all the processes for creating each active layer are performed layer by layer and then stacked up, as the number of active layers increases, the time required to create the device (TAT) increases. This results in extremely serious problems such as increased yield and decreased yield.

The present invention provides a method for manufacturing a semiconductor device that solves these drawbacks.

According to the present invention, a plurality of active layers in which circuit elements such as transistors and conductive wires interconnecting these are integrated are laminated, and the circuit elements of each active layer are mechanically coupled to each other between the layers. A semiconductor device manufacturing method for forming a multi-layered semiconductor device, in which n supporting substrates (n is an integer of 2 or more) made of semiconductors, insulators, etc. are prepared, and at least one layer is formed on the surface of each supporting substrate. active layers (hereinafter referred to as first layer, second layer, ... nth active layer), and alignment patterns formed in the second layer, third layer, ... nth active layer. Remove the supporting substrate from the side opposite to the active layer in a portion corresponding to the position, then make the surface of the first active layer face the surface of the second active layer, and align both active layers as described above. After aligning the positions with each other using a pattern, the connecting portions provided on the surfaces of both active layers are brought into close contact with each other, and both are bonded. Subsequently, the support substrate under the second active layer is removed to form a second active layer. The back surfaces of the two active layers are exposed, and then the exposed back surfaces of the second active layer and the third layer are exposed.
After the surfaces of the active layers of the layers are opposed and both active layers are aligned with each other using an alignment pattern, a second
The connection portion provided on the back surface of the active layer of the layer and the connection portion provided on the surface of the third layer active layer are brought into close contact with each other, and both are bonded, and the support substrate of the third layer active layer is subsequently removed. After exposing the back surface of the third active layer, the fourth, fifth, ... n-th active layers are also subjected to the same process as the third active layer. A method for manufacturing a semiconductor device is obtained, which is characterized in that the process is repeated.

Further, according to the present invention, a plurality of active layers in which circuit elements such as transistors and conductive wires interconnecting these are integrated are laminated, and the circuit elements of each active layer are mechanically coupled to each other between the layers. A semiconductor device manufacturing method for forming a multi-layered semiconductor device, in which n supporting substrates (n is an integer of 2 or more) made of semiconductors, insulators, etc. are prepared, and at least one layer is formed on the surface of each supporting substrate. active layer (hereinafter referred to as the first layer, second layer, ... n-th active layer)
The second layer, the third layer...the supporting substrate in the portion corresponding to the position of the alignment pattern formed in the nth active layer is removed from the side opposite to the active layer. After the surface of the first active layer is opposed to the surface of the second active layer, and the positions of both active layers are aligned with each other using the alignment pattern, the connecting portions provided on the surfaces of both active layers are connected. While keeping them in close contact with each other,
After bonding the two, the supporting substrate of the second active layer is removed to expose the back surface of the second active layer, and then the exposed back surface of the second active layer and the third layer are bonded together.
After the surfaces of the active layers of the layers are opposed and both active layers are aligned with each other using an alignment pattern, a second
The connection portion provided on the back surface of the active layer of the layer and the connection portion provided on the surface of the third layer active layer are brought into close contact with each other, and both are bonded, and the support substrate of the third layer active layer is subsequently removed. After exposing the back surface of the third active layer, the fourth, fifth, ... n-th active layers are also subjected to the same process as the third active layer. A method for manufacturing a semiconductor device is obtained, which is characterized in that a plurality of n-layer laminates are formed in parallel by repeated steps, and then the plurality of laminates are laminated.

The present invention will be explained in detail below using the drawings. FIGS. 2, 3, and 4 respectively show first, second, and nth active layers formed on a supporting substrate such as a semiconductor or an insulator. Note that these active layers are formed by using a semiconductor such as silicon as a support substrate, on which an insulating film such as silicon dioxide and a polysilicon film are sequentially deposited, and then the polysilicon is subjected to laser annealing or electron beam annealing. This is an example created using a silicon single crystal film obtained by recrystallization, that is, SOI (Silicon on Intulator).

In Figure 2, 101 is vapor phase growth (CVD)
This is an insulating film made of silicon dioxide or the like deposited on a support substrate 10 of silicon or the like by a method or the like. 10
4, 105, 106 are the drain and source regions of field effect transistors (hereinafter referred to as FETs),
The channel region is formed using the above-mentioned silicon film formed on the insulating film 101 by a well-known process. 107 is the gate of the FET, and 102 is an insulating film of silicon dioxide or the like deposited by CVD or the like after the gate is formed. 108 is the insulating film 102 on the drain region 104 and source region 105.
This is a metal wiring made of aluminum or the like, which is deposited by a sputtering method or the like after opening a hole in the material, and then patterned by a photolithography method or the like. 109 is an alignment pattern for aligning the first and second active layers; here, as an example, the metal wiring 10
8 is made of the same material and formed at the same time. Reference numeral 103 is an insulating film made of silicon dioxide or the like that is deposited by CVD or the like after forming the metal wiring 108 and alignment pattern 109. Reference numeral 110 denotes a vertical wiring made of metal such as aluminum and inserted into a hole formed by opening the insulating film 103. 112
are metal bumps such as gold provided on the vertical wiring, and the circuit elements in the first active layer and the circuit elements in the other active layers are coupled to each other via the metal bumps. Reference numeral 113 is a transparent heat dissipating material such as artificial diamond that has both excellent insulation properties and thermal conductivity, and is formed as necessary when the amount of heat generated from the active layer is large. Note that the first active layer 11 has layers 101, 102, and 10, as is clear from FIG.
3,104,105,106,107,108,
It is composed of elements such as 109, 110, 112, and 113.

In FIG. 3, 20 is a support substrate made of silicon or the like;
21 is a second active layer. The second active layer 21 is an insulating film 201, 20 made of silicon dioxide or the like.
2, 203, FET drain region 204, source region 205, channel region 206, gate 20
7. Metal wiring 208 made of aluminum or the like, alignment pattern 209, vertical wiring 210 on the metal bump side made of metal such as aluminum and vertical wiring 211 on the support substrate side, metal bump 2 made of gold or the like
12, is composed of a heat dissipating material 213 such as artificial diamond. The manufacturing process for these components is almost the same as that for the first active layer. However, before laminating the second active layer 21 on the first active layer 11, the alignment pattern 209 is
A process is added in which a portion of the support substrate corresponding to the area is removed and an opening portion 214 is provided as shown in FIG. This opening process can be easily performed, for example, by performing anisotropic selective etching using a solution such as KOH. By removing a portion of the opaque supporting substrate such as silicon in this way, a transparent insulating film 20 such as silicon dioxide is formed.
It becomes possible to see through the alignment pattern 209 formed in 1, 202, 203 from the support substrate side. Therefore, even when the second layer active layer 21 is stacked on the first layer active layer 10 with the active layer side facing up, the alignment pattern 209 can be formed using transparent insulating films 101 and 102 such as silicon dioxide. , 103 can be matched to the alignment pattern 109 formed therein. Although the explanation is omitted, the third layer, the fourth layer,
..., (n-1)th active layer 31, 41, ..., 6
1 is also formed using exactly the same process as the second active layer.

In FIG. 4, 70 is a support substrate made of silicon or the like;
71 is an n-th active layer. The n-th active layer 71 is made of insulating films 701 and 70 made of silicon dioxide or the like.
2,703, FET drain region 704, source region 705, channel region 706, gate electrode 707, metal wiring 708 such as aluminum (can be partially used as a bonding pad), alignment pattern 709, aluminum It is composed of vertical wiring 710 made of metal such as, metal bumps 712 made of gold or the like, heat dissipation material 713 such as artificial diamond, and the like. The manufacturing process for these components is almost the same as that for the first and second active layers. Also, before laminating the active layer, similarly to the second active layer, the portion of the support substrate corresponding to the alignment pattern 709 is removed to form an opening 714. At the same time, a portion of the support substrate corresponding to the bonding pad is also removed to provide an opening 715.

The active layers laminated above have been explained. Next, a method for laminating these active layers will be explained in order of steps with reference to FIGS. 5 to 7. In this figure, elements that are the same as those shown in FIGS. 1 to 4 are designated by the same numbers as used in FIGS. 1 to 4.

First, as shown in FIG.
1 is formed on a stage 15.
to be installed. The stage 15 is equipped with a heating device 16 such as a heater, and also has a well-known suction function for fixing the support substrate 10 in a predetermined position.
On the other hand, the second active layer 21 formed on the support substrate 20 is fixed to the movable device 17 with the active layer side facing downward and facing the first active layer. The movable device 17 is equipped with a well-known adsorption function, a well-known alignment function, a function of applying pressure to the support substrate 20 and the second active layer 21, and the like. Next, while moving the movable device 17 back and forth, left and right, the second active layer 21 is inserted through the hole 214 opened in the support substrate.
The first and second active layers are aligned with each other by matching the alignment pattern 209 provided therein with the alignment pattern 109 provided in the first active layer 11 within a tolerance range. .

When the alignment is completed, the movable device 17 is translated downward as shown in FIG.
112) in the figure and the metal bump provided on the second active layer 21 (for example, 212 in FIG. 3) are brought into close contact with each other. At this time, these metal bumps are heated in advance by the heating device 16 to a temperature of, for example, 300 or more.
Heat to 400 degrees C. At the same time, by controlling the movable device 17 and applying a pressure of, for example, about 50 kg/mm ² in the direction of the arrow 18, these metal bumps are diffusion welded to each other, completing a two-layer semiconductor device. .

After the connection between the metal bumps is completed, the two-layer semiconductor device is taken out from the stage 15 and the movable device 17, and then the support substrate 21 is removed. An example of a method for removing this support substrate 20 will be explained using FIG. 3. First, by a method such as polishing using an alkaline or ammonia-based solution, up to the portion indicated by the broken line 215, that is, the portion 20a close to the surface of the support substrate is removed. Then, for example,
Using a mixture of HNO ₃ , HF and CH ₃ COOH,
The remaining support substrate 20b is removed. At this time, the insulating films 201 and 201a function as a stopper to stop this etching. Note that the supporting substrates 20a and 20b can also be removed at once using the mixed solution. Next, in order to expose the vertical wiring 211, the insulating film 201a is removed using a mixed solution of hydrofluoric acid and water. At this time, a portion of the exposed surface of the insulating film 201 is also etched.

After the removal of the support substrate 20 is completed, the third
Moving on to the step of laminating the active layer of the layer. This is shown in FIG. In this case as well, the process is similar to the process of laminating the second active layer and the process of removing the supporting substrate described using FIGS. 5 and 6.
The same applies to the third to nth active layers.

Finally, the insulating film of the n-th active layer (71 in Figure 4)
6) is removed using photolithography and an opening is opened to expose the bonding pad (a portion of the metal wiring 708), thereby forming an n-layer semiconductor device. FIG. 8 shows an example of the structure of a three-layer semiconductor device manufactured by the above manufacturing method. In this case the first
The active layers of the second layer and the third layer are respectively
3 and 4, respectively.

Above, we have explained in detail the method for manufacturing multilayer semiconductor devices, that is, the stacking method. According to the present invention, the creation of the first, second, ... n-th active layers and the removal of the supporting substrate from the second to n-th active layers are performed in parallel and at the same time. The time required to create a multilayer semiconductor device according to the present invention is extremely shortened compared to the time required to create a multilayer semiconductor device well known from the present invention. Furthermore, active layers made of semiconductors made of different materials such as silicon and gallium arsenide, or active layers formed using different manufacturing processes such as FETs and bipolar transistors can be laminated freely, allowing for multifunctionality and optimization of functions. , the degree of freedom in design increases. Furthermore, since active layers with no failures can be selected by testing circuits and the like in advance and then stacking them, it is possible to realize semiconductor devices with extremely high yields. Therefore, productivity is greatly improved. In addition, the alignment pattern provided in the transparent insulating film is
After removal of the opaque support substrate, it is freely visible and alignment alignment between the layers can be easily accomplished using conventional methods. For this reason, back alignment devices, etc.
It has advantages such as not requiring large-scale equipment.

Note that in the method for manufacturing a semiconductor device of the present invention,
When laminating an active layer or removing a supporting substrate, there are no restrictions on the sizes of the active layer, supporting substrate, transparent substrate, etc. Also, the types of materials used in the above explanation (semiconductor materials, insulating materials, metal materials, heat dissipation materials,
Adhesive materials, etching solutions, etc.), manufacturing conditions (temperature, pressure, film thickness, etc.), or individual manufacturing methods (etching, polishing, diffusion welding, etc.) are just examples, and the effects of the present invention may not be achieved. If so, it is not limited to the matters listed above. In the above explanation, the active layer formed using SOI was explained as an example, but the explanation is not limited to this, and there are cases where the active layer is formed on the surface of a semiconductor substrate, or when the active layer is formed on the surface of a semiconductor substrate. This also applies when it is formed on an epitaxial semiconductor film or on an SOS Si film. Furthermore, the simple circuit configuration described above is also an example, and the present invention is not limited thereto.

In addition, in the above embodiment, n sheets were initially prepared in which only one active layer was formed on the support substrate, but it is not necessary to be limited to this. Alternatively, a plurality of active layers may be formed in advance using a method.

Furthermore, although the above embodiments have shown the case where three or more active layers are laminated, the present invention can of course be applied to the case where there are two active layers.

Further, in the embodiment described above, the n-layer laminate obtained by laminating n active layers one by one was used as a completed semiconductor device, but there is no need to be limited by this understanding. That is, in the present invention, (n+1) layers, (n+2) layers, etc. may be further laminated on this n-layer laminate.

Alternatively, a plurality of n-layer laminates may be made in parallel, and finally they may be laminated in the same manner as in the previous embodiment. Conversely, when considering an n-layer laminate as a completed semiconductor device, for example, three n/3-layer laminates are manufactured in parallel, and finally these three are laminated to form an n-layer semiconductor device. may be completed.

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view of an n-layer semiconductor device;
3 and 4 are schematic cross-sectional views of the first, second, and nth active layers and support substrate using SOI as an example, and FIGS. 5 to 7 are schematic cross-sectional views of the active layer and support substrate of the present invention In order to explain the manufacturing method, a schematic cross-sectional view showing the structure of a multilayer semiconductor device, No. 8 is shown in the order of the steps.
The figure is a schematic cross-sectional view of a three-layer semiconductor device obtained by the manufacturing method according to the present invention. 1 to 8, 1 is a multilayer semiconductor device, 10, 2
0, 30, 70 are supporting substrates, 11, 21, 31,
41, 51, 61 are active layers of the first layer, second layer, third layer, fourth layer, (n-2) layer, and (n-1) layer, and 71 is the n-th layer or the third layer. active layer, 12
13 is a substrate of the package, 13 is a bonding pad, 14 is a bonding wire, 15 is a stage, 16 is a heating device, 17 is a movable device, and 18 is a direction of pressurization. In Figures 2 to 8, 1
01, 102, 103, 201, 202, 20
3,701,702,703 are insulating films, 104,
204, 704 is a drain region, 105, 20
5,705 is the source area, 106,206,70
6 is a channel region, 107, 207, 707 is a gate, 108, 208, 308 is a metal wiring, 10
9,209,309,709 are alignment patterns,
110, 210, 211, 710 are vertical wiring, 1
12,212,712 is a metal bump, 113,2
13, 713 is a heat dissipating material, 714 is a hole through which the alignment pattern can be seen, and 716 is a through hole in the pad.

Claims (1)

[Claims] 1. A plurality of active layers in which circuit elements such as transistors and conductive wires interconnecting these are integrated, and the circuit elements of each active layer are organically coupled to each other between the layers. A method for manufacturing a semiconductor device in which a multi-layered semiconductor device is formed by forming n supporting substrates made of semiconductors, insulators, etc. (n is 2).
(an integer greater than or equal to
layer,...referred to as the nth active layer), and the second layer is formed.
Layer, third layer...A portion of the support substrate corresponding to the position of the alignment pattern formed in the n-th active layer is removed from the side opposite to the active layer, and then the first active layer is removed. After the surface and the surface of the second active layer are made to face each other, and the positions of both active layers are aligned with each other using the alignment pattern, the connecting portions provided on the surfaces of both active layers are brought into close contact with each other, and both Combine,
Subsequently, the supporting substrate of the second active layer is removed to expose the back surface of the second active layer, and then the exposed back surface of the second active layer and the surface of the third active layer are placed opposite each other. After aligning the positions of both active layers with each other using an alignment pattern, connect the connecting portions provided on the back surface of the second active layer and the connecting portions provided on the surface of the third active layer with each other. After bringing them into close contact and bonding them together, the support substrate of the third active layer is removed to expose the back surface of the third active layer, and then the fourth layer, fifth layer, . . . A method for manufacturing a semiconductor device, characterized in that the steps described above for the third layer active layer are repeated for the active layer as well. 2. A multi-layer semiconductor in which a plurality of active layers are stacked in which circuit elements such as transistors and conductive wires that interconnect these are integrated, and the circuit elements in each active layer are organically bonded to each other between the layers. A method for manufacturing a semiconductor device forming a device, in which n supporting substrates made of semiconductors, insulators, etc.
(an integer greater than or equal to
layer,...referred to as the nth active layer), and the second layer is formed.
layers, third layer, ... The supporting substrate of the portion corresponding to the position of the alignment pattern formed in the active layer of the n-th layer is removed from the side opposite to the active layer, and then the supporting substrate of the part of the active layer of the first layer is removed. After the surface and the surface of the second active layer are made to face each other, and the positions of both active layers are aligned with each other using the alignment pattern, the connecting portions provided on the surfaces of both active layers are brought into close contact with each other, and both Combine,
Subsequently, the supporting substrate of the second active layer is removed to expose the back surface of the second active layer, and then the exposed back surface of the second active layer and the surface of the third active layer are placed opposite each other. After aligning the positions of both active layers with each other using an alignment pattern, connect the connecting portions provided on the back side of the second active layer and the connecting portions provided on the surface of the third active layer with each other. After bringing them into close contact and bonding them together, the support substrate of the third active layer is removed to expose the back surface of the third active layer, and then the fourth layer, fifth layer, . . . For the active layer, a plurality of n-layer laminates are formed in parallel by repeating the steps described above for the third active layer, and then the plurality of n-layer laminates are formed in parallel. A method of manufacturing a semiconductor device, comprising stacking a laminate of.