JPH049376B2 - - Google Patents
Info
- Publication number
- JPH049376B2 JPH049376B2 JP3777182A JP3777182A JPH049376B2 JP H049376 B2 JPH049376 B2 JP H049376B2 JP 3777182 A JP3777182 A JP 3777182A JP 3777182 A JP3777182 A JP 3777182A JP H049376 B2 JPH049376 B2 JP H049376B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor substrate
- etching
- mounting table
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 12
- 238000005260 corrosion Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 6
- 239000007788 liquid Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 238000003756 stirring Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】 本発明は半導体基体の腐食方法に関する。[Detailed description of the invention] The present invention relates to a method for corroding semiconductor substrates.
高耐圧、大容量の半導体装置では、半導体基体
をメサ構造に加工して、特性の向上をはかつてい
る。従来、この種のメサ型半導体装置を製造する
過程でのメサエツチングは、予め、残すべき領域
の表面を二酸化シリコン膜や耐酸性ワツクスで被
覆したのち、その半導体基板を弗酸、硝酸、醋酸
の混液に浸漬し、同液を撹拌しながら、前記半導
体基板の露出面を食刻する方法によつて行われて
いた。しかしながら、この方法によつても、食刻
の深さは、前記混液の組成、温度、処理時間ある
いは撹拌の仕方などにより、かなりのばらつきが
見られる。とりわけ、大口径の半導体基板に多数
の単位素子を造り込み、これを碁盤割りに配した
細溝で区切つてメサエツチングを行う場合には、
その細溝の形状、寸法も加味すると、同細溝の深
さを一律に制御するのは甚だむつかしく、そのば
らつぎが半導体素子の特性のばらつきとなつて現
われ、耐圧、リーク電流特性の低下にもつながつ
てくる。 In high-voltage, large-capacity semiconductor devices, semiconductor substrates are processed into mesa structures to improve their characteristics. Conventionally, in mesa etching in the process of manufacturing this type of mesa-type semiconductor device, the surface of the area to be left is coated in advance with a silicon dioxide film or acid-resistant wax, and then the semiconductor substrate is coated with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid. The exposed surface of the semiconductor substrate is etched while the semiconductor substrate is immersed in the liquid and the liquid is stirred. However, even with this method, the depth of etching varies considerably depending on the composition, temperature, processing time, stirring method, etc. of the mixed solution. In particular, when performing mesa etching by building a large number of unit elements on a large-diameter semiconductor substrate and separating them with narrow grooves arranged in a grid pattern,
Taking into account the shape and dimensions of the narrow groove, it is extremely difficult to uniformly control the depth of the same narrow groove, and variations in the depth appear as variations in the characteristics of semiconductor elements, resulting in a decrease in withstand voltage and leakage current characteristics. It also connects.
本発明は、上述のような半導体のエツチングに
おける問題点を解消する方法を提供するものであ
る。すなわち、本発明は、半導体載置台を偏中心
軸で左および右に交互に回動させるとともに、同
載置台を上下動させながら、この載置台上に支持
した上記半導体を腐食処理することを特徴とする
半導体の腐食方法であり、この方法によれば、従
来のように腐食液を撹拌機で撹拌しながらエツチ
ング処理するより、はるかに均一処理ができ、高
効率であることが確認された。 The present invention provides a method for solving the above-mentioned problems in semiconductor etching. That is, the present invention is characterized in that the semiconductor mounting table is rotated alternately to the left and right about an eccentric axis, and the semiconductor supported on the mounting table is subjected to corrosion treatment while the mounting table is moved up and down. It has been confirmed that this method provides a much more uniform etching process and is highly efficient than the conventional etching process in which the etching solution is stirred with a stirrer.
以下、本発明を実施例により詳しくのべる。 Hereinafter, the present invention will be described in detail with reference to Examples.
第１図は実施例方法に用いた半導体エツチング
治具の概略図であり、半導体基板１をその腐食処
理面２が下向きになるように載置台３で支持して
置き、半導体基板１を同エツチング治具４内に多
段に配置したものである。この治具４はその中央
部、すなわち、円盤形半導体基板１の円中心部よ
り外れた位置に軸心をもつ回転軸体５を有してお
り、この軸体５を回動させることによつて、これ
に載置された前記半導体基板１もそお軸のまわり
を左右自在に回転する。したがつて、前記半導体
基板１は偏心して回動する。経験によると、この
偏心の程度は前記半導体基板１の直径を1/3〜1/4
等分した位置に回転軸が置かれるようにすると好
適であつた。 FIG. 1 is a schematic diagram of a semiconductor etching jig used in the example method, in which a semiconductor substrate 1 is supported on a mounting table 3 with its corrosion-treated surface 2 facing downward, and the semiconductor substrate 1 is etched using the same etching method. They are arranged in multiple stages within the jig 4. This jig 4 has a rotating shaft 5 whose axis is located away from the center of the disk-shaped semiconductor substrate 1, and by rotating the shaft 5. Accordingly, the semiconductor substrate 1 placed thereon also rotates freely left and right around the vertical axis. Therefore, the semiconductor substrate 1 rotates eccentrically. According to experience, the degree of eccentricity is approximately 1/3 to 1/4 of the diameter of the semiconductor substrate 1.
It was preferable to place the rotating shafts at equally divided positions.
さらに、この治具４は前記回転軸体５を摺動さ
せることによつて、上下動も自在になるように形
成する。これによつて、前記回転軸体５を、外部
のモータ、カムなどの駆動機構と組合わせるか、
あるいは手動で、前記半導体基板１を左および右
に交互に回動させながら、併せて、上下動させる
ことができる。 Furthermore, this jig 4 is formed so that it can be moved vertically by sliding the rotating shaft body 5. With this, the rotating shaft body 5 can be combined with an external drive mechanism such as a motor or a cam, or
Alternatively, the semiconductor substrate 1 can be manually rotated alternately left and right while simultaneously being moved up and down.
第２図は、前記エツチング治具を用いて半導体
のメサエツチを行つた際の管理分布図であり、メ
サエツチの深さ100μmを目標値としたときのばら
つきは、この実施例特性Ａが従来例特性Ｂにより
改善されていることが確認された。 FIG. 2 is a management distribution diagram when performing mesa etching of a semiconductor using the etching jig. It was confirmed that B was improved.
以上に詳述したように、この発明の方法によれ
ば次のような作用効果が期待される。第１に、半
導体基板の被エツチ面を下面にして、同半導体基
板に左右交互の回転運動を上下運動とを同時に与
えることで、エツチング時の反応と同時に発生す
る気泡を確実に取り除き、その撹拌の効果が顕著
であり、これにより、メサエツチの深さのばらつ
きが減少する。第２に、半導体載置台を半導体基
板の中心より若干偏心させた位置を回転中心とし
て回転させることにより、腐食液の撹拌による液
流が複雑性を増して、離泡の効果が上がり、均一
エツチング作用の増進がはかられる。これらの作
用効果により、本発明によれば、メサ型半導体装
置の特性向上、たとえば、耐圧向上、リーク電流
の減少となり、製造歩留りの向上など、大きな利
点を有し、工業的利用価値大である。 As detailed above, the method of the present invention is expected to have the following effects. First, by placing the surface to be etched of the semiconductor substrate on the lower side and giving the semiconductor substrate alternating left and right rotational motion and vertical motion at the same time, it is possible to reliably remove bubbles that are generated at the same time as the reaction during etching, and to agitate the semiconductor substrate. The effect of this is significant, and this reduces the variation in the depth of the mesa etch. Second, by rotating the semiconductor mounting table at a position slightly eccentric from the center of the semiconductor substrate, the liquid flow due to stirring of the corrosive liquid increases in complexity, improving the bubble separation effect and achieving uniform etching. The effect will be enhanced. As a result of these effects, the present invention has great advantages such as improved characteristics of the mesa semiconductor device, such as improved breakdown voltage and reduced leakage current, and improved manufacturing yield, and has great industrial utility value. .
第１図は本発明の実施に用いる半導体エツチン
グ治具の要部概略図、第２図は本発明の実施効果
を示す特性図である。
１……半導体基板、２……半導体の腐食処理
面、３……載置台、４……エツチング治具、５…
…回転軸体。
FIG. 1 is a schematic view of the main parts of a semiconductor etching jig used for implementing the present invention, and FIG. 2 is a characteristic diagram showing the effects of implementing the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Corrosion-treated surface of semiconductor, 3... Mounting table, 4... Etching jig, 5...
...Rotating shaft body.
Claims (1)
に回動させることにより、前記載置台を回転及び
上下動させながら、前記載置台上に支持した前記
半導体を腐食処理することを特徴とする半導体基
体の腐食方法。1. Corrosion treatment is performed on the semiconductor supported on the semiconductor mounting table while rotating and vertically moving the semiconductor mounting table by alternately rotating the semiconductor mounting table to the left and right about an eccentric axis. Corrosion method for semiconductor substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3777182A JPS58154234A (en) | 1982-03-09 | 1982-03-09 | Etching method for semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3777182A JPS58154234A (en) | 1982-03-09 | 1982-03-09 | Etching method for semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58154234A JPS58154234A (en) | 1983-09-13 |
| JPH049376B2 true JPH049376B2 (en) | 1992-02-20 |
Family
ID=12506727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3777182A Granted JPS58154234A (en) | 1982-03-09 | 1982-03-09 | Etching method for semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58154234A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5172901A (en) * | 1990-07-31 | 1992-12-22 | Sharp Kabushiki Kaisha | Paper feeding device |
| JP2721059B2 (en) * | 1991-11-06 | 1998-03-04 | 富士通テン株式会社 | Tape reproducing apparatus and method |
| JP4818133B2 (en) | 2007-01-17 | 2011-11-16 | ニスカ株式会社 | Printing device |
-
1982
- 1982-03-09 JP JP3777182A patent/JPS58154234A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58154234A (en) | 1983-09-13 |
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