JPH0493096A - Multilayer ceramic board - Google Patents
Multilayer ceramic boardInfo
- Publication number
- JPH0493096A JPH0493096A JP21082590A JP21082590A JPH0493096A JP H0493096 A JPH0493096 A JP H0493096A JP 21082590 A JP21082590 A JP 21082590A JP 21082590 A JP21082590 A JP 21082590A JP H0493096 A JPH0493096 A JP H0493096A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- vias
- diameter
- multilayer ceramic
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 57
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 239000002344 surface layer Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 abstract description 3
- 230000008094 contradictory effect Effects 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 101100313164 Caenorhabditis elegans sea-1 gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用骨！Ｉ！ｆ） 本発明は多層セラミック基板に関する。[Detailed description of the invention] (Industrial use bone!I!f) The present invention relates to a multilayer ceramic substrate.
（従来の技術）
半導体装置用パッケージとして用いられる多層セラミッ
ク基板は、内部および外表面に導体回路を形成した複数
枚のグリーンシートを積層し焼成してなるものである。(Prior Art) A multilayer ceramic substrate used as a package for a semiconductor device is made by laminating and firing a plurality of green sheets each having conductor circuits formed on the inside and outside surfaces.
この多層セラミック基板では層間の電気的接続をとるた
めにビアが設けられる。ビアはグリーンシー１〜にビア
ポールを穿設し、ピアホール内に導体材料を充填し、積
層したグリーンシートと同時焼成によって形成される。In this multilayer ceramic substrate, vias are provided for electrical connection between layers. The via is formed by drilling a via pole in the green sea 1~, filling the peer hole with a conductive material, and co-firing with the laminated green sheets.
（発明が解決しようとする課題）
第２図は半導体装置用パッケージで用いる多層セラミッ
ク基板の平面図の例を示すが、半導体素子の高集積化と
ともに図のようにセラミック基板に設けるビア配置がき
わめて高密度となっている。(Problems to be Solved by the Invention) Figure 2 shows an example of a plan view of a multilayer ceramic substrate used in a semiconductor device package. It has a high density.
このように高密度にビアを設けるためには、ビアの位置
を高精度で配置させる技術が必要となる。In order to provide vias at such a high density, a technique for arranging the vias with high precision is required.
ビアは表面層−にに形成する導体回路と電気的に接続さ
れるから、導体回路と接続することからみるとビア径は
小さいほど位置合わせは容易である。Since the via is electrically connected to a conductor circuit formed on the surface layer, the smaller the diameter of the via, the easier the alignment is from the viewpoint of connection to the conductor circuit.
第３図はビア」−〇と導体回路１２との接続状態を示す
が、導体回路１２とビア１０との位置誤差はほぼ一定で
あるから、大径のビアを位置合わせするほうが小径のビ
アを位置合わせするよりも困難゛である。Figure 3 shows the connection state between the via "-" and the conductor circuit 12. Since the positional error between the conductor circuit 12 and the via 10 is almost constant, it is better to align the large diameter via than to align the small diameter via. It is more difficult than alignment.
セラミック基板はグリーンシー１−の焼成時に収縮する
のでビア位置を精度よく製造することは困難であり、位
置ずれしたりすることがらビア径はできるだけ小径であ
ることが望ましい。Since the ceramic substrate contracts during firing of Green Sea 1-, it is difficult to manufacture the via position with high precision, and it is desirable that the diameter of the via be as small as possible to avoid misalignment.
第２図に示すように一定面積内にビアを高密度で配置す
るにはビア径を小さくせざるを得ないが、一方、このよ
うにビアを小径にするとビア部分での電気抵抗値が大き
くなるから、これによって多層セラミック基板の電気的
特性が低下するという１Ｍ題点が生じる。ビアにはタン
グステン粉末等の導体材料を混ぜたペース１へが用いら
れるが、これらは本来、さほど電導性が良好とはいえな
い材料である。したがって、ビアを小径にするとさらに
電気抵抗値が大きくなり、電気的特性に悪影響を及ぼす
ようになる。As shown in Figure 2, in order to arrange vias at a high density within a certain area, the diameter of the vias must be made small, but on the other hand, when the diameter of the vias is made small in this way, the electrical resistance value in the via portion becomes large. Therefore, this causes the 1M problem of deteriorating the electrical characteristics of the multilayer ceramic substrate. Pase 1, which is a mixture of conductive materials such as tungsten powder, is used for the vias, but these materials are inherently not very conductive. Therefore, if the diameter of the via is made smaller, the electrical resistance value will further increase, which will adversely affect the electrical characteristics.
そこで、本発明は」二記問題点を解消すべくなされたも
のであり、その［］１的とするところは、半導体装置用
パッケージ等で用いる多層セラミック基板において、表
面層上に形成する導体回路との位置合わせが容易にでき
ると共に、ビアの電気抵抗値を効果的に小さくすること
のできる多層セラミック基板を提供しようとするもので
ある。Therefore, the present invention has been made to solve the above two problems, and its first purpose is to provide a conductor circuit formed on a surface layer of a multilayer ceramic substrate used in a semiconductor device package, etc. It is an object of the present invention to provide a multilayer ceramic substrate that can be easily aligned with the substrate and that can effectively reduce the electrical resistance value of the via.
（課題を解決するための手段） 本発明は上記目的を達成するため次の構成をそなえる。(Means for solving problems) The present invention has the following configuration to achieve the above object.
すなわち、ビアを有する多層セラミック基板において、
前記ビアを複数層を貫通して設けると共に、導体回路に
接続する表面層のビア径よりも内層のビア径を大径に形
成したことを特徴とする。That is, in a multilayer ceramic substrate having vias,
The vias are provided to penetrate through a plurality of layers, and the diameter of the vias in the inner layer is larger than the diameter of the vias in the surface layer connected to the conductor circuit.
（作用）
多層セラミック基板の表面層のビアが小径であるから導
体回路等の接続部との位置合わせが容易である。多層セ
ラミック基板の内層のビアを大径に形成したことで断面
積が大きくとれ、ビアの電気抵抗値を小さくできる。(Function) Since the vias in the surface layer of the multilayer ceramic substrate have a small diameter, alignment with connection parts such as conductor circuits is easy. By forming the vias in the inner layer of the multilayer ceramic substrate with a large diameter, the cross-sectional area can be increased, and the electrical resistance value of the vias can be reduced.
（実施例）
以下、本発明の好適な実施例を図面とともに詳細に説明
する。(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明に係る多層セラミック基板の要部を示す
。FIG. 1 shows the main parts of a multilayer ceramic substrate according to the present invention.
本発明に係る多層セラミック基板はその表面層」二に形
成する導体回路に接続するビアの構成を特徴とするもの
である。The multilayer ceramic substrate according to the present invention is characterized by the structure of vias connected to conductor circuits formed on its surface layer.
第１−図にその構成例を示す。図のように１本実施例の
多層セラミック基板は、最下層の基板１４ａと中間層の
基板１４ｂと最上層の基板１４ｃの３層からなり、各層
を貫通してビア１０を形成している。Figure 1 shows an example of its configuration. As shown in the figure, the multilayer ceramic substrate of this embodiment consists of three layers: a bottom layer substrate 14a, an intermediate layer substrate 14b, and a top layer substrate 14c, with vias 10 penetrating through each layer.
各層の基板厚は適宜設定してよいが、最下層の基板１４
ａと最」二層の基板１４ｃは尊く、中間層の基板１４ｂ
は厚く設定するのがよい。実施例の多層セラミック基板
では最下層の基板１４ａと最上層の基板１４ｃの厚さが
０．１５ｍｍで、中間層の基板１４ｂの厚さが０．４ｍ
ｍである。The substrate thickness of each layer may be set as appropriate, but the bottom layer substrate 14
The two layer substrates 14c and 14c are important, and the intermediate layer substrate 14b
It is better to set it thickly. In the multilayer ceramic substrate of the example, the thickness of the bottom layer substrate 14a and the top layer substrate 14c is 0.15 mm, and the thickness of the intermediate layer substrate 14b is 0.4 m.
It is m.
また、最下層の基板１４ａと最」二層の基板１４Ｃに設
けるビア１０のビア径にくらべて、中間層１４ｂに設け
るビア径を大径にする。Further, the diameter of the via provided in the intermediate layer 14b is made larger than the via diameter of the via 10 provided in the bottom layer substrate 14a and the two-most layer substrate 14C.
実施例では最下層の基板］、 ４ ａと最上層の基板１
４ｃに設けるビア径を０．１ｍｍφ、中間層の基板１４
ｂに設けるビア径を０．３ｍｍφに設定した。In the embodiment, the bottom layer substrate] 4a and the top layer substrate 1
The via diameter provided in 4c is 0.1 mmφ, and the intermediate layer substrate 14
The diameter of the via provided in b was set to 0.3 mmφ.
最下層の基板１４ａと最上層の基板１４ｃの表面には積
層、焼成後に導体回路が形成され、最下層の基板１４ａ
と最上層の基板１４ｃに設けたビア１０はそれぞれ導体
回路に接続されるものである。Conductor circuits are formed on the surfaces of the bottom layer substrate 14a and the top layer substrate 14c after lamination and firing, and the bottom layer substrate 14a
The vias 10 provided in the uppermost substrate 14c are connected to conductor circuits, respectively.
上記多層セラミック基板の製造にあたっては、まず、最
下層の基板］４ａと、中間層の基板１４ｂと、最上層の
基板１４ ｃのグリーンシーＩ〜をそれぞれ所定厚で別
々に形成し、それぞれピアホールを所定の同じ位置に穿
設する。中間層の基板１４ｂ用のグリーンシートに設け
るピアホールは他にくらべて大径に穿設する。In manufacturing the above-mentioned multilayer ceramic substrate, first, the bottom layer substrate 4a, the middle layer substrate 14b, and the top layer substrate 14c (Green Sea I~) are separately formed to a predetermined thickness, and a peer hole is formed in each. Drill at the same predetermined location. The pier hole provided in the green sheet for the intermediate layer substrate 14b has a larger diameter than other pier holes.
次に、それぞれのグリーンシー１〜のピアホールに導体
ペース１へを充填し、充填後のグリーンシー１〜を最下
層、中間層、最上層の３層で位置決めして積層する。Next, the conductor paste 1 is filled into the pier holes of each of the Green Seas 1~, and the filled Green Seas 1~ are positioned and stacked in three layers: the bottom layer, the middle layer, and the top layer.
次に、この積層したグリーンシーＩ−を所定プロセスに
よって焼成して多層セラミック基板を得る。Next, this laminated Green Sea I- is fired by a predetermined process to obtain a multilayer ceramic substrate.
こうして得られた多層セラミック基板は第１図に示すよ
うな断面形状を有するビアによって、その後、外表面に
形成される導体回路と接続することができるセラミック
基板となる。The thus obtained multilayer ceramic substrate becomes a ceramic substrate that can be connected to a conductor circuit formed on the outer surface thereof through vias having a cross-sectional shape as shown in FIG.
導体回路は、焼成後の多層セラミック基板の表面を平滑
にした後、蒸着、スパッタリングなどにより金属導体層
を形成し、この金属導体層をエツチングなどにより所定
の回路パターンに形成してビアと電気的に接続する。な
お、多層セラミック基板の表面層上に導体ペース１−を
用いて回路パターンを形成後、基板とともに焼成して導
体回路を形成するようにしてもよい。Conductive circuits are made by smoothing the surface of the multilayer ceramic substrate after firing, forming a metal conductor layer by vapor deposition, sputtering, etc., and forming the metal conductor layer into a predetermined circuit pattern by etching, etc. to connect vias and electrical connections. Connect to. Note that a circuit pattern may be formed on the surface layer of a multilayer ceramic substrate using conductive paste 1-, and then fired together with the substrate to form a conductive circuit.
本実施例の多層セラミック基板によれば、導体回路を形
成する表面層ではビア径が小径に形成されているから、
ビアと導体回路の接続部との位置合わぜが容易にできる
。また一方、ビア基板の中間層ではビアを大径にしてい
るからビアの断面積が大きくなり、これによってビアの
電気抵抗値を効果的に低くすることができる。According to the multilayer ceramic substrate of this example, the via diameter is formed to be small in the surface layer forming the conductor circuit.
The vias and the connecting portions of the conductor circuits can be easily aligned. On the other hand, since the vias in the intermediate layer of the via substrate have a large diameter, the cross-sectional area of the vias becomes large, thereby effectively reducing the electrical resistance value of the vias.
実際に電気抵抗値を測定したところ、以下の結果が得ら
れた。比較例は」二記実施例の多層セラミック基板と同
厚で０．１ｍｍφの貫通したビアによるものである。When the electrical resistance values were actually measured, the following results were obtained. The comparative example has a via having the same thickness as the multilayer ceramic substrate of Example 2 and having a diameter of 0.1 mm.
実施例（３層構造）４０ｍΩ
比較例 ８０ｍΩ
このように上記実施例のビアは比較例の１７２の電気抵
抗値となっている。複数層からなる多層セラミック基板
の各層のＪ％さは適宜設定できるから、各層の厚さの比
を変えることによって電気抵抗値を変えることが可能で
ある。Example (three-layer structure): 40 mΩ Comparative example: 80 mΩ As described above, the via of the above example has an electrical resistance value of 172 of the comparative example. Since the J% of each layer of a multilayer ceramic substrate consisting of a plurality of layers can be set as appropriate, it is possible to change the electrical resistance value by changing the thickness ratio of each layer.
また、本実施例の多層セラミック基板のように表面層に
露出するビアの径を第４図に示すように細くすると、従
来の第３図に示す場合と比べて隣接するビア間にスペー
スを確保することができるため、ビア間にも導体回路を
形成して導体回路を高密度に形成できるという利点があ
る。Furthermore, if the diameter of the vias exposed on the surface layer is made thinner as shown in Figure 4, as in the multilayer ceramic substrate of this example, more space can be secured between adjacent vias than in the conventional case shown in Figure 3. Therefore, there is an advantage that conductor circuits can be formed between the vias and the conductor circuits can be formed with high density.
なお、」二記実施例の多層セラミック基板はアルミナ、
窒化アルミニウム、ガラスセラミック等の種々のセラミ
ック基板に対して利用することができるものである。Note that the multilayer ceramic substrate of Example 2 is made of alumina,
It can be used for various ceramic substrates such as aluminum nitride and glass ceramic.
また、上記実施例では多層セラミック基板を３層構造で
形成したが、」二層が小径のビア部、下層が大径のビア
部のように２層で形成したものや４層以」；の構造で形
成したものでも有効である。すなわち、多層セラミック
基板の表面層」二に形成される導体回路等の接続部に接
続される表面層のビア部を小径に形成し、内層のビア部
を大径に形成することで導体回路等の接続部との位置合
わせの容易化と、ビアの電気抵抗値の低下を達成するこ
とができる。In addition, although the multilayer ceramic substrate was formed with a three-layer structure in the above embodiment, it may be formed with two layers, such as two layers having a small-diameter via portion and a lower layer with a large-diameter via portion, or four or more layers. It is also effective if the structure is formed. In other words, the via portions of the surface layer connected to the connection portions of the conductor circuits formed on the surface layer 2 of the multilayer ceramic substrate are formed with a small diameter, and the via portions of the inner layer are formed with a large diameter. It is possible to facilitate alignment with the connecting portion of the via and to reduce the electrical resistance value of the via.
以上、本発明について好適な実施例を挙げて種々説明し
たが、本発明はこの実施例に限定されるものではなく、
発明の精神を逸脱しない範囲内で多くの改変を施し得る
のはもちろんのことである。The present invention has been variously explained above using preferred embodiments, but the present invention is not limited to these embodiments.
Of course, many modifications can be made without departing from the spirit of the invention.
（発明の効果）
本発明に係る多層セラミック基板によれば、ビアと多層
セラミック基板上に形成される導体回路等の接続部との
位置合わせを容易にすることと、ビア部の電気抵抗値を
下げるという相反する要求を容易に達成することができ
、導体回路やビアを高密度で配置することが容易に可能
になると共に、半導体装置用パッケージの電気的特性を
向」ニさせることかできる等の著効を奏する。(Effects of the Invention) According to the multilayer ceramic substrate according to the present invention, it is possible to easily align the vias with the connecting portions such as conductor circuits formed on the multilayer ceramic substrate, and to reduce the electrical resistance value of the via portions. It is possible to easily achieve the conflicting demands of lowering the temperature, easily arrange conductor circuits and vias at high density, and improve the electrical characteristics of semiconductor device packages. It is very effective.
第１図は本発明に係る多層セラミック基板の要部を示す
断面図、第２図はビア配置を示す説明図、第３図および
第４図はビアと導体回路との接続状態を示す説明図であ
る。
１０・・・ビア、 １２・・・導体回路、１−４ａ、
１４ｂ、１４Ｃ・・・基板。FIG. 1 is a sectional view showing the main parts of a multilayer ceramic substrate according to the present invention, FIG. 2 is an explanatory view showing the via arrangement, and FIGS. 3 and 4 are explanatory views showing the connection state between the via and the conductor circuit. It is. 10... Via, 12... Conductor circuit, 1-4a,
14b, 14C...Substrate.
Claims (1)
アを複数層を貫通して設けると共に、導体回路に接続す
る表面層のビア径よりも内層のビア径を大径に形成した
ことを特徴とする多層セラミック基板。1. A multilayer ceramic substrate having vias, characterized in that the vias are provided to penetrate through a plurality of layers, and the diameter of the vias in the inner layer is larger than the diameter of the vias in the surface layer connected to the conductor circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21082590A JPH0493096A (en) | 1990-08-08 | 1990-08-08 | Multilayer ceramic board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21082590A JPH0493096A (en) | 1990-08-08 | 1990-08-08 | Multilayer ceramic board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0493096A true JPH0493096A (en) | 1992-03-25 |
Family
ID=16595744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21082590A Pending JPH0493096A (en) | 1990-08-08 | 1990-08-08 | Multilayer ceramic board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0493096A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0779079A (en) * | 1993-09-09 | 1995-03-20 | Nec Corp | Ceramic multilayer wiring board |
| EP0851724A3 (en) * | 1996-12-26 | 2000-09-27 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electric components |
| JP2006041242A (en) * | 2004-07-28 | 2006-02-09 | Kyocera Corp | Ceramic wiring board |
| JP2007184314A (en) * | 2005-12-30 | 2007-07-19 | Murata Mfg Co Ltd | Method for manufacturing ceramic multilayer substrate and ceramic multilayer substrate |
| JP2015076481A (en) * | 2013-10-08 | 2015-04-20 | 株式会社村田製作所 | Ceramic multilayer substrate |
| WO2016021397A1 (en) * | 2014-08-06 | 2016-02-11 | 大日本印刷株式会社 | Through-electrode substrate, method for manufacturing same, and semiconductor device in which through-electrode substrate is used |
-
1990
- 1990-08-08 JP JP21082590A patent/JPH0493096A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0779079A (en) * | 1993-09-09 | 1995-03-20 | Nec Corp | Ceramic multilayer wiring board |
| US6192581B1 (en) | 1996-04-30 | 2001-02-27 | Matsushita Electric Industrial Co., Ltd. | Method of making printed circuit board |
| EP0851724A3 (en) * | 1996-12-26 | 2000-09-27 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electric components |
| US6281448B1 (en) * | 1996-12-26 | 2001-08-28 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electronic components |
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| EP1250033A3 (en) * | 1996-12-26 | 2003-01-02 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electronic component |
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| JP2015076481A (en) * | 2013-10-08 | 2015-04-20 | 株式会社村田製作所 | Ceramic multilayer substrate |
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| WO2016021397A1 (en) * | 2014-08-06 | 2016-02-11 | 大日本印刷株式会社 | Through-electrode substrate, method for manufacturing same, and semiconductor device in which through-electrode substrate is used |
| US10008442B2 (en) | 2014-08-06 | 2018-06-26 | Dai Nippon Printing Co., Ltd. | Through-electrode substrate, method for manufacturing same, and semiconductor device in which through-electrode substrate is used |
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