JPH0492296A - Fuse circuit - Google Patents
Fuse circuitInfo
- Publication number
- JPH0492296A JPH0492296A JP2207742A JP20774290A JPH0492296A JP H0492296 A JPH0492296 A JP H0492296A JP 2207742 A JP2207742 A JP 2207742A JP 20774290 A JP20774290 A JP 20774290A JP H0492296 A JPH0492296 A JP H0492296A
- Authority
- JP
- Japan
- Prior art keywords
- signal wiring
- resistance element
- resistance
- level
- disconnectable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 239000012535 impurity Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Read Only Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、不揮発性メモリーとしてヒユーズ回路を用い
た場合の半導体集情回路（以下ＩＣと称〔従来の技術〕
できあがった工ａの外部より、何らかの操作を行つ事に
よってＩＣの特性や機能を変更できる事は、機能の多様
化や特性の高精度化が可能となり工Ｃの付加価値を高め
る事となる。従来より、工Ｃの外部より何らかの操作を
行って機能・特性を変更する手段としては、工Ｃの製造
コスト上鏝も安価なヒユーズ回路が多く用いられている
。従来のヒユーズ回路の一例を第２図に示す。１は外部
との電気的接続をする為のパッド、２はヒユーズ素子、
４はＮ型ＭＯ８−ＦＦＪＴ、５はインバータ、６はパッ
ド１に接続した信号配線、７は正極電源、８は負極電源
、９はＮ型ＭＯ３−ＦＩＴ。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit (hereinafter referred to as IC [prior art]) when a fuse circuit is used as a nonvolatile memory. , being able to change the characteristics and functions of an IC by performing some operations makes it possible to diversify functions and improve the precision of characteristics, increasing the added value of Engineering C. As a means of changing functions and characteristics by performing some kind of operation, fuse circuits are often used because they are inexpensive in terms of manufacturing cost.An example of a conventional fuse circuit is shown in Fig. 2.1 is Pad for electrical connection with the outside, 2 is a fuse element,
4 is an N-type MO8-FFJT, 5 is an inverter, 6 is a signal wiring connected to the pad 1, 7 is a positive power supply, 8 is a negative power supply, and 9 is an N-type MO3-FIT.
１０はＮ型ＭＯ８−ＰＥＴを制御する制御信号である。10 is a control signal for controlling the N-type MO8-PET.
信号配線６への情報書き込みは、ヒユーズ素子２を切断
が非切断で切り替える。ヒユーズ素子２は多結晶シリコ
ン等で形成されており、その切断は正極電源７とパッド
１０間に、例えば２０〜２５Ｖ程度の電圧を数ミ＋７秒
間印加し、電流により溶断させる事によって行う。When information is written to the signal wiring 6, the fuse element 2 is switched without being cut. The fuse element 2 is made of polycrystalline silicon or the like, and is cut by applying a voltage of, for example, about 20 to 25 V between the positive electrode power source 7 and the pad 10 for several milliseconds and blowing it out with a current.
次に書き込み動作について説明する。ヒユーズ素子２が
非切断の場合、信号配線６には、ヒユーズ素子２を介し
て正極電源７の電圧レベルが出力され、“Ｈ”レベルと
なる。インバータ５は“Ｌ”を出力し、Ｎ型ＭＯＳ−Ｆ
ＥＴ４はオフする。Next, the write operation will be explained. When the fuse element 2 is not cut, the voltage level of the positive power supply 7 is outputted to the signal wiring 6 via the fuse element 2, and becomes "H" level. Inverter 5 outputs "L", and N type MOS-F
ET4 is turned off.
Ｎ型Ｍτ５−ＦＥＴ９がオンした時のインピーダンスに
対し、ヒユーズ素子２のインピーダンスを充分小さくし
ておけば、たとえＮ型ＭＯＳ−ＦＥＴ９がオンしても、
信号配線６は＠Ｈ＃レベルを保持する。If the impedance of the fuse element 2 is made sufficiently small compared to the impedance when the N-type Mτ5-FET9 is turned on, even if the N-type MOS-FET9 is turned on,
Signal wiring 6 holds @H# level.
一方、ヒユーズ素子２が切断されていると、信号配線６
は初期時にフローティングとなるが、制御信号１０が一
度“Ｈ”となると、Ｎ型ＭＯＳ−ＦＥＴ９がオンし、負
極電源已に接続するので”Ｌ”レベルとなる。するとイ
ンバータ５は″”Ｈ”を出力し、Ｎ型ＭＯＳ−’ＩＰＥ
Ｔ４をオンさせるので、制御信号１０が“Ｌ＃に切シ替
わってＮ型ＭＯＳ−ＦＥＴ９をオフさせても、信号配線
６は６Ｌ”レベルを保持する。On the other hand, if the fuse element 2 is disconnected, the signal wiring 6
is floating at the initial stage, but once the control signal 10 becomes "H", the N-type MOS-FET 9 is turned on and connected to the negative power supply terminal, so that it becomes "L" level. Then, the inverter 5 outputs "H", and the N-type MOS-'IPE
Since T4 is turned on, even if the control signal 10 switches to "L#" and turns off the N-type MOS-FET 9, the signal wiring 6 maintains the 6L level.
第２図の従来例では、ヒユーズ素子２が非切断の場合、
Ｎ型ＭＯＳ−ＦＥＴ９がオンする毎に電流を消費してし
まう。電池を電源とするハンディ機器や電子腕時計のよ
うに低消費電流で動作する事が重要な特性の製品では、
上述の電流を極力制限する必要がある。その為にはＮ型
ＭＯＳ−ＦＥＴ９を制御する制御信号１０がＨ″となる
タイミング（＝Ｎ型Ｍ ＯＳ −Ｆ Ｅ Ｔ カオンす
るタイミング）が極力少ないデー−ティの信号を形成す
る必要がある。しかしながら、Ｍ御信号１０が“Ｈ”と
なるタイミングの極力少ない信号として、例えば１秒に
１回、１０ミリ秒だけ“Ｈ”となる信号としたとすると
、電源投入時、制御信号１０が′Ｈ”レベルとなるまで
の時間、つまり約１秒間は入力配線６はフローティング
となり、工Ｃを誤動作させてしまうという課題があった
。In the conventional example shown in FIG. 2, when the fuse element 2 is not cut,
Current is consumed every time the N-type MOS-FET 9 is turned on. For products that require low current consumption, such as handheld devices and electronic watches that are powered by batteries,
It is necessary to limit the above-mentioned current as much as possible. For this purpose, it is necessary to form a data signal with as few timings as possible at which the control signal 10 controlling the N-type MOS-FET 9 becomes H'' (=timing at which the N-type MOS-FET turns on). However, if the M control signal 10 is set to "H" as little as possible, for example, once every second for 10 milliseconds, then when the power is turned on, the control signal 10 becomes "H". There was a problem in that the input wiring 6 was floating for the time until it reached the H'' level, that is, about 1 second, causing the circuit C to malfunction.
本発明は、上述の課題を解決するもので有り、目的とす
る所は入力配線６の電圧レベルを“Ｌ″に保持するため
のＮ型ＭＯＳ−ＦＥＴ９の必要のない、低消費電流のヒ
ユーズ回路を提供する事にある。The present invention is intended to solve the above-mentioned problems, and its purpose is to create a low current consumption fuse circuit that does not require an N-type MOS-FET 9 to maintain the voltage level of the input wiring 6 at "L". The goal is to provide the following.
上述した課題を解決する為に４本発明のヒユーズ回路は
、抵抗素子と、切断可能な抵抗素子と、ラッチ回路と、
信号配線とで構成され、前記信号配線は前記抵抗素子を
介して一方の電源へ接続され、更に前記信号配線は、前
記切断可能な抵抗素子を介して他の一方の電源へ接続さ
れ、前記信号配線に前記抵抗素子が接続した側の電源電
圧レベルが与えられた場合は、前記信号配線の電圧レベ
ルを前記ラッチ回路がラッチする事を特徴とする〔実施
例〕
本発明の一実烏例を第１図の回路図に示す。基本的回路
は第２図と同様であって、かつ同じ素子は同一の記号を
使用している。新しい構成要素として６の抵抗素子が信
号６と負極電源８の間に配置されている。更に、第２図
に於けるＮ型ＭＯＳ−ＦＥＴ９は削除した構成となって
いる。In order to solve the above-mentioned problems, the fuse circuit of the present invention includes a resistive element, a cuttable resistive element, a latch circuit,
The signal wiring is connected to one power supply via the resistance element, and the signal wiring is connected to the other power supply via the cuttable resistance element. [Embodiment] An example of the present invention is characterized in that when a power supply voltage level on the side to which the resistance element is connected to the wiring is applied, the latch circuit latches the voltage level of the signal wiring. This is shown in the circuit diagram of FIG. The basic circuit is similar to that in FIG. 2, and the same elements are designated by the same symbols. Six resistance elements are placed between the signal 6 and the negative power source 8 as new components. Furthermore, the N-type MOS-FET 9 in FIG. 2 has been omitted.
２は切断可能な抵抗素子（ヒユーズ回路）で、信号配線
６と正極電源７の間に配置されている。Reference numeral 2 denotes a cuttable resistance element (fuse circuit), which is arranged between the signal wiring 6 and the positive power supply 7.
３は抵抗素子で信号配線６と負極電源８の間に配置され
ている。Ｎ型ＭＯＳ−ＦＥＴ４とインバータ５はラッチ
回路を構成していて、切断可能な抵抗素子２が切断され
ていると、信号配線６は抵抗素子５を介して負極電源８
の電圧レベル（“Ｌ”レベル）トナリ、インバータ５
カ″Ｈ″レベルを出力し、Ｎ型ＭＯＳ−ＦＥＴ４がオン
する事により、信号配線６を１Ｌ″レベルにラッチする
。切断可能な抵抗素子２は、ボロン（Ｂ）や！／７（Ｐ
）などの不純物をドーピングした多結晶シリコンで、数
十Ω〜数百０の比抵抗を有する。抵抗素子６は不純物を
ドーピングしていない真性多結晶シリコンで、数十ギガ
Ωの比抵抗を有する。従って切断可能な抵抗素子２の抵
抗値Ｒ２とＲ３の関係は以下のように構成されている。Reference numeral 3 denotes a resistive element arranged between the signal wiring 6 and the negative electrode power supply 8. The N-type MOS-FET 4 and the inverter 5 constitute a latch circuit, and when the disconnectable resistance element 2 is disconnected, the signal wiring 6 is connected to the negative power supply 8 via the resistance element 5.
voltage level (“L” level), inverter 5
The signal wiring 6 is latched to the 1L" level by outputting the "H" level and turning on the N-type MOS-FET 4. The cuttable resistive element 2 is made of boron (B) or !/7 (P).
) is doped with impurities such as polycrystalline silicon, and has a specific resistance of several tens of ohms to several hundred ohms. The resistance element 6 is made of intrinsic polycrystalline silicon that is not doped with impurities, and has a specific resistance of several tens of giga-ohms. Therefore, the relationship between the resistance values R2 and R3 of the cuttable resistance element 2 is configured as follows.
Ｒ２＜＜Ｒ５・・・・・・０
次に書き込み動作について説明する。切断可能な抵抗素
子２が非切断の場合、信号配線６の電圧レベルは、切断
可能な抵抗素子２の抵抗値Ｒ２と抵抗素子６の抵抗値Ｒ
３との比で決まるが、抵抗Ｒ２とＲ５の関係は上述０式
であるので、信号配線６はほぼ″′Ｈ＃レベルとなる。R2<<R5...0 Next, the write operation will be explained. When the cuttable resistance element 2 is not cut, the voltage level of the signal wiring 6 is equal to the resistance value R2 of the cuttable resistance element 2 and the resistance value R of the resistance element 6.
3, and the relationship between the resistors R2 and R5 is the above-mentioned equation 0, so the signal wiring 6 is approximately at the ``H# level.
一方、切断可能な素子２が切断されている場合は、信号
配線６は抵抗素子５により′Ｌ”レベルとなる。更に、
ラッチ回路のインバータ５とＮ型ＭＯＳ−ＦＥＴ４とに
より信号配線６の′Ｌ”レベルはラッチされる。On the other hand, when the cuttable element 2 is cut, the signal wiring 6 becomes 'L' level due to the resistance element 5.Furthermore,
The 'L' level of the signal line 6 is latched by the inverter 5 and the N-type MOS-FET 4 of the latch circuit.
上述の説明では、切断可能な抵抗素子２を正極電源側で
、抵抗素子３を負極電源側に接続したが切断可能な抵抗
素子を負極側電源側、抵抗素子を正極電源側に接続して
も、インノ（−夕５の出力を受けるＭＯＳ−ＩＰＥＴを
Ｐ型ＭＯ８−ＸＰｇＴとして正極電源７と信号配線６の
間に配置すれば、同様のヒユーズ回路を実現できる。ま
た、上述の説明では、ラッチ回路として、インバータ１
ケとＭＯＳ−ＦＥＴＩケの構成で説明したが、信号配線
６の電圧レベルをラッチできれば、どのようなラッチ回
路でもよい。In the above explanation, the cuttable resistance element 2 was connected to the positive power supply side and the resistance element 3 was connected to the negative power supply side, but it is also possible to connect the cuttable resistance element 2 to the negative power supply side and the resistance element to the positive power supply side. A similar fuse circuit can be realized by placing a P-type MO8-XPgT MOS-IPET that receives the output of the inno(-5) between the positive power supply 7 and the signal wiring 6.In addition, in the above explanation, the latch As a circuit, inverter 1
Although the explanation has been made using the configurations of 1 and MOS-FETI, any type of latch circuit may be used as long as it can latch the voltage level of the signal wiring 6.
次に切断可能な抵抗素子２と、抵抗素子３について工Ｃ
上のレイアウトについて説明する。第６図は切断可能な
抵抗素子のレイアウトの一例を示すレイアウト図である
。１１は多結晶シリフンであり、全体にボロン（Ｂ）や
リン（Ｐ）の不純物がドーピングされており、比抵抗は
数十Ω〜数百Ω程度である。１２と１６は金属配線層で
一方を電源、他の一方を信号配線に接続する。１４と１
５は多結晶シリコン１１と金属配線１２と１５を電気的
接続する為のコンタクト、１６は工０を雰囲気の湿度℃
不純物などからの特性変化を防ぐために、工Ｃの表面を
覆っているシリコン酸化膜などのパシベーション膜の開
口部である。非切断として使用する場合は、外部から何
らの操作を加えず、上述の構成で使用する。切断状態で
使用する場合は、配線ｚ２と配線１３０間に、例えば２
０■以上の高電圧を印加し、多結晶シリコン１１に電流
を流す。すると、前記電流による発熱で、多結晶シリコ
ン１１が溶解し、パシベーション開口１６を介して雰囲
気中に蒸発し切断状態に切り換える。Next, cut the resistor element 2 and the resistor element 3.
Let's explain the layout above. FIG. 6 is a layout diagram showing an example of the layout of a cuttable resistance element. 11 is polycrystalline silicon, the entire structure is doped with impurities such as boron (B) and phosphorus (P), and the specific resistance is about several tens of ohms to several hundred ohms. 12 and 16 are metal wiring layers, one of which is connected to a power supply and the other to a signal wiring. 14 and 1
5 is a contact for electrically connecting the polycrystalline silicon 11 and metal wirings 12 and 15; 16 is the temperature of the atmosphere (°C);
This is an opening in a passivation film such as a silicon oxide film that covers the surface of the substrate C to prevent changes in characteristics due to impurities. When used as a non-cutting device, the above-mentioned configuration is used without any external operation. When used in a disconnected state, for example, connect 2 wires between the wire z2 and the wire 130.
A high voltage of 0■ or more is applied to cause a current to flow through the polycrystalline silicon 11. Then, the polycrystalline silicon 11 is melted by the heat generated by the current and evaporated into the atmosphere through the passivation opening 16, thereby switching to the cutting state.
第１図における抵抗素子６についてのレイアウトの一例
を第４図のレイアウト図で説明する。１７は多結晶シリ
コン、１８と１９は金属配線で一方を電源、他の一方を
信号配線に接続する。２０と２１は多結晶シリコン１１
と金属配線１８と１９を電気的接続するコンタクト、２
２は工Ｃの製造工程中で多結晶シリコン１７への不純物
ドーピングの際に、不純物がドーピングされない領域を
示す。−船釣に、領域２２には、工Ｃ製造時フォトエツ
チング手法の素子選択に用いるレジスト（感光性樹脂）
を付けておき、その上方より不純物をドーピングする。An example of the layout of the resistor element 6 in FIG. 1 will be explained with reference to the layout diagram in FIG. 4. 17 is polycrystalline silicon, and 18 and 19 are metal wirings, one of which is connected to a power supply and the other to a signal wiring. 20 and 21 are polycrystalline silicon 11
and a contact for electrically connecting the metal wirings 18 and 19, 2
Reference numeral 2 indicates a region where impurities are not doped when polycrystalline silicon 17 is doped with impurities during the manufacturing process of process C. - For boat fishing, area 22 contains a resist (photosensitive resin) used for element selection in the photoetching method during the manufacturing of process C.
is attached and then doped with impurities from above.
すると、領域２２以外は不純物がドーピングされるが、
領域２２に囲まれた多結晶シリコン１７の部分は、不純
物がドーピングされない真性多結晶シリコンが得られる
。この真性多結晶シリコンにより比抵抗数十ギガΩの抵
抗素子を形成する。Then, regions other than the region 22 are doped with impurities, but
In the portion of polycrystalline silicon 17 surrounded by region 22, intrinsic polycrystalline silicon that is not doped with impurities is obtained. This intrinsic polycrystalline silicon forms a resistance element with a specific resistance of several tens of giga-ohms.
以上述べたように、本発明によれば、切断可能な抵抗素
子２（ヒユーズ素子）が切断されている場合に電源投入
しても、入力配線６は抵抗を介して電圧レベルが固定さ
れるので、工Ｃが誤動作する事がない。また、第２図従
来例におけるＮ型ＭＯＳ−ＦＥＴ９が必要ないので、前
記Ｎ型ＭＯ３−ＦＫＴ９が消費する電流が無（なり、低
消費電流化が達成できる。抵抗素子３に流れる電流は、
抵抗素子６の抵抗が数十ギガΩであるので、１．５Ｖ銀
電池を電源とする場合は１ナノ・アンペア以下となり、
通常無視できる値である。また、前記Ｎ型ＭＯＳ−ＦＥ
Ｔ９を制御する信号も不必要となるので、工０内の回路
が簡略化され、チップ・サイズの縮少から工Ｃコストの
低減が達成できるまた、切断可能な抵抗素子３が切断さ
れている場所は、信号配線６の電圧レベルは高抵抗の抵
抗素子３・により与えられ、ノイズに影響され易い状態
となるが、前記信号配線６の電圧レベルはラッチ回路に
より、瞬時にラッチされるので、ノイズの影響も受けづ
らいという効果を有する。As described above, according to the present invention, even if the power is turned on when the disconnectable resistance element 2 (fuse element) is disconnected, the voltage level of the input wiring 6 is fixed through the resistor. , Engineering C will not malfunction. Furthermore, since the N-type MOS-FET 9 in the conventional example shown in FIG.
Since the resistance of the resistive element 6 is several tens of giga ohms, when using a 1.5V silver battery as a power source, the resistance will be less than 1 nanoampere,
This is usually a negligible value. Moreover, the N-type MOS-FE
Since the signal to control T9 is also unnecessary, the circuit in the process 0 is simplified, and the cost of the process C can be reduced by reducing the chip size.Also, the resistive element 3, which can be cut, is cut. The voltage level of the signal wiring 6 is given by the high-resistance resistor 3 and is susceptible to noise, but the voltage level of the signal wiring 6 is instantaneously latched by the latch circuit. It also has the effect of being less susceptible to noise.
１１．１７・・・・・・・・・多結晶シリコン１２．１
５，１８．１９・・・・・・金属配線11.17・・・・・・Polycrystalline silicon 12.1
5,18.19・・・Metal wiring
第１図は本発明の一実施例を示す回路図。
第２図は従来例の回路図。
第３図は切断可能な抵抗素子のレイアウト図。
第４図は抵抗素子のレイアウト図。
１−・・・・・・・パッド
２・・・・・・・・・ヒユーズ素子
５・・・・・・・・・抵抗素子
４・・・・・・・・・Ｎ型ＭＯＳ−ＦＥＴ５・・・・・
・・・・インバータ
６・・・・・・・・・信号配線
７・・・・・・・・・正極電源
８・・・・・・・・・負極電源
９・・・・・・・・・Ｎ型ＭＯＳ−ＦＩＴｌｏ・・・・
・・・・・制御信号FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram of a conventional example. FIG. 3 is a layout diagram of a cuttable resistance element. FIG. 4 is a layout diagram of a resistance element. 1-...Pad 2...Fuse element 5...Resistance element 4...N-type MOS-FET5.・・・・・・
...Inverter 6... Signal wiring 7... Positive power supply 8... Negative power supply 9...・N-type MOS-FITlo・・・・
·····Control signal
Claims (1)
信号配線とで構成され、前記信号配線は前記抵抗素子を
介して一方の電源へ接続され、更に前記信号配線は、前
記切断可能な抵抗素子を介して他の一方の電源へ接続さ
れ、前記信号配線に前記抵抗素子が接続した側の電源電
圧レベルが与えられた場合は、前記信号配線の電圧レベ
ルを前記ラッチ回路がラッチすることを特徴とするヒュ
ーズ回路。A resistance element, a cuttable resistance element, a latch circuit,
The signal wiring is connected to one power supply via the resistance element, and the signal wiring is connected to the other power supply via the cuttable resistance element. A fuse circuit characterized in that the latch circuit latches the voltage level of the signal wiring when a power supply voltage level on the side to which the resistance element is connected to the wiring is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2207742A JPH0492296A (en) | 1990-08-06 | 1990-08-06 | Fuse circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2207742A JPH0492296A (en) | 1990-08-06 | 1990-08-06 | Fuse circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0492296A true JPH0492296A (en) | 1992-03-25 |
Family
ID=16544784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2207742A Pending JPH0492296A (en) | 1990-08-06 | 1990-08-06 | Fuse circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0492296A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7215176B2 (en) | 2003-09-29 | 2007-05-08 | Seiko Epson Corporation | Analog value adjustment circuit, display driver circuit, and method of adjusting analog value |
-
1990
- 1990-08-06 JP JP2207742A patent/JPH0492296A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7215176B2 (en) | 2003-09-29 | 2007-05-08 | Seiko Epson Corporation | Analog value adjustment circuit, display driver circuit, and method of adjusting analog value |
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