JPH0492288A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To minimize the loss of reading voltage even when an integrated degree is improved by executing the precharging operation of a reference bit line by a precharging means also at the time of memory cell connecting operation. CONSTITUTION:When storage data from a memory cell are read in a selecting bit line SBL, the electric potential of the selecting bit line SBL ascends/descends for DELTAV1 than 1/2 Vcc corresponding to the storage contents of the memory cell. On the other hand, since a reference bit line RBL in precharging, even when some electric potential change is generated by capacity coupling between the selecting bit line SBL and the reference bit line RBL to the reference bit line RBL, the electric potential is recovered quickly. Accordingly, an electric potential difference between the selecting bit line SBL and the reference bit line RBL becomes DELTAV1 substantially and reading voltage is not lost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor memory device, and particularly to stabilizing the read operation of a DRAM or the like.

[Conventional technology]

FIG. 7 is a circuit configuration diagram showing the periphery of a set of bit lines in a conventional DRAM. As shown in the figure, bit lines BLI,
A bit line pair is formed by BL2, and a memory capacitor M
CI is connected to the bit line BLI via the NMO3 selection transistor Q1, and the word line WL1 is connected to the gate of the selection transistor Q1. Similarly, memory capacitor MC2 is connected to bit line BL2 via NMO3 selection transistor Q2, and word line WL2 is connected to the gate of selection transistor Q2. Bit lines BLI and BL2 are commonly connected to a precharge power supply VBL whose potential is at the 1/2 Vcc level via NMOS transistors Q3 and Q4, respectively. Also, NM
A precharge signal PR is applied to the gates of OS transistors Q3 and Q4.

On the other hand, a sense amplifier 1 is provided between the bit lines BLI and BL2. Sense amplifier 1 becomes active upon receiving sense amplifier activation signal SO at H level, and in the active state, bit line BLI is activated.

The potential difference between BL2 is detected, and the high potential bit line is brought to H level, and the low potential bit line is brought to L (ground) level.

FIG. 8 is a waveform diagram showing the refresh operation of the DRAM shown in FIG. The refresh operation will be explained below with reference to the same figure.

First, before the time t1 when the potential of the word line WLI rises to the H level, the precharge signal PR is set to the H level, and after precharging the potential of the bit line pair BLI and BL2 to 1/2 Vcc, the precharge signal PR is set to the H level. lower to L level.

Then, at time t1, when the potential of the word line WLI is raised to H level, the selection transistor Q1 is turned on.
The charge stored in the memory capacitor MCI is transmitted to the selected bit line BL1, and the potential of the bit line BLI rises or falls arbitrarily based on the contents stored in the memory capacitor MCI. On the other hand, the potential of the word line WL2 is fixed at L level, and the selection transistor Q
Since bit line BL2 is turned off, the potential of bit line BL2, which is the reference bit line, maintains 1/2Voo.

That is, a potential difference occurs between bit lines BLI and BL2 based on the storage content of memory capacitor MCI.

Then, at time t2, the sense amplifier activation signal SO is set to H.
Raise the level and activate the sense amplifier. Then, of the bit lines BLI and BL2, the high potential bit line is amplified to H level, and the low potential bit line is amplified to L level.

As a result, the potential of the bit line BLI amplified to H and L levels is written into the memory capacitor MCI again.

Thereafter, the word line WLI falls to the L level, the sense amplifier activation signal SO is set to the L level, and the precharge signal SO rises to the H level again to perform rewriting to other memory capacitors.

A refresh operation is performed by performing such rewriting on all memory capacitors.

[Problem to be solved by the invention]

In recent years, DRAMs have become highly integrated, and the width between bit line pairs tends to become narrower, so that parasitic capacitance is likely to be formed between bit line pairs.

FIG. 9 is an explanatory diagram showing the electron potential of signal lines, etc. during refreshing. In the figure, SN is the storage node of the memory capacitor, SBL is the selected bit line, and R
BL indicates a reference bit line.

As shown in the figure, when the stored data from the memory cell is read to the selected bit line SBL, the selected bit line SBL
The potential of is 1/2Voo depending on the memory contents of the memory cell.
Increase/decrease by ΔV1.

At this time, due to the capacitive coupling between the selected bit line SBL and the reference bit line RBL, the potential of the reference bit line RBL also increases/decreases by ΔV2 from 1/2 Vcc.

Therefore, the potential difference between the selected bit line SBL and the reference bit line RBL, which is the sensing target of the sense amplifier 1, becomes substantially (ΔV1-Δv2), which is smaller than ΔV1, resulting in a loss of read voltage.

As described above, the conventional highly integrated dynamic RAM has the problem of loss of read voltage due to capacitive coupling between bit line pairs.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor memory device that can minimize read voltage loss even when the degree of integration is improved.

[Means to solve the problem]

In the semiconductor memory device according to the present invention, the first
A memory cell consisting of a capacitive component is connected to a selected bit line, which is one of the bit lines, and the second bit line, and data stored in the selected memory cell is read based on the potential difference with the reference bit line, which is the other bit line. a precharging unit that performs a precharging operation to set the selected bit line and the reference bit line to a predetermined potential; and a precharging unit that connects the memory cell to the selected bit line after performing the precharging operation of the selected bit line. and a sense amplifier that performs a read operation to detect and amplify a potential difference between the selected bit line and the reference bit line after the memory cell connection operation, The precharging means continues the precharging operation of the reference bit line during the memory cell connection operation, and completes the precharging operation by the time of the read operation.

[Effect]

Since the precharging means in this invention performs the precharging operation of the reference bit line even during the memory cell connection operation, the capacitive coupling that occurs between the selected bit line and the reference bit line causes memory cell connection n'.

It is possible to suppress potential changes occurring in the reference bit line based on potential changes in the reference bit line.

〔Example〕

FIG. 1 is a circuit configuration diagram showing the periphery of one set of bit lines of a DRAM according to an embodiment of the present invention. As shown in the figure, the bit lines BLI and BL2 have a common potential of 1/2cc through NMOS transistors Q5 and Q6, respectively.
It is connected to the level precharge power supply VBL. Then, a precharge signal PR2 is applied to the gate of NMO3) transistor Q5, and a precharge signal PRI is applied to the gate of NMO5) transistor Q6. Note that the other configurations are the same as the conventional example shown in FIG. 7, so explanations will be omitted.

FIG. 2 is a waveform diagram showing the refresh operation of the DRAM shown in FIG. 1. The refresh operation will be explained below with reference to the same figure.

First, before time t01 when the potential of word line WLI rises to H level, precharge signals PR1 and PH1 are set to H level, and after precharging the potential of bit line pair BLl and BL2 to 1/2 Vcc, the precharge signal Lower PR2 to L level. At this time, the precharge signal PRI is maintained at H level.

Then, at time t01, when the potential of the word line WLI is raised to H level, the selection transistor Q1 is turned on, so that the charge accumulated in the memory capacitor MCI is transmitted to the bit line BL1, which is the selected bit line, and the memory capacitor Based on the memory contents of MCI, the potential of bit line BLI slightly increases or decreases. On the other hand, word line WL2
The potential of is fixed at L level, and the selection transistor Q2 is turned off. At this time, bit line pair BLI and BL
Although the potential of the bit line BL2 changes due to the capacitive coupling formed between the bit line BL2 and the bit line BL2, the precharge signal PR1 maintains the H level and precharging of the bit line BL2 continues. Line BL2
The potential quickly recovers to ]/2Vcc.

Thereafter, at time t02, the precharge signal PR1 falls to L, and at time t03, the sense amplifier activation signal S
0 to the H level, and the sense amplifier 1 is activated. Then, of the bit lines BL1 and BL2, the bit line with a high potential is amplified to H level, and the bit line with low potential is amplified to L level.

As a result, the potential of the bit line BLI amplified to H and L levels is written into the memory capacitor MCI again.

After that, the word line WLI falls to the L level, the sense amplifier activation signal SO is set to the L level, and the precharge signal s is activated again.

is raised to H level, and rewriting to other memory capacitors is performed.

A refresh operation is performed by performing such rewriting on all memory capacitors.

FIG. 3 is an explanatory diagram showing the electron potential of each signal line during refresh of the DRAM in the embodiment shown in FIG. In the figure, SN indicates a storage node of a memory capacitor, SBL indicates a selected bit line, and RBL indicates a reference bit line.

As shown in the figure, when the stored data from the memory cell is read to the selected bit line SEL, the selected bit line SBL
The potential of ]/2■oo depends on the memory contents of the memory cell.
Increase/decrease by ΔV1.

On the other hand, since the reference bit line RBL is being precharged, even if a slight potential change occurs on the reference bit line RBL due to capacitive coupling between the selected bit line SBL and the reference bit line RBL, the potential is quickly reduced to 1.
/2VCC is restored.

Therefore, the selected bit line SBL and the reference bit line R
The potential difference with BL is substantially Δ■1, and there is no loss of read voltage.

FIG. 4 is a circuit diagram showing a precharge signal generating circuit 10 that generates a precharge signal PRI in the DRAM of this embodiment.

As shown in the figure, the synchronous inversion signal RAS of the external row address strobe signal RAS is taken in as one input of both the NAND gate 11 and the NAND gate 12, and
A row address signal RAO instructing the selection of the word line WL2 is taken in as the other input of the AND gate 11, and a row address signal RAO instructing the selection of the word line WL1 is taken in as the other input of the NAND gate 2.

The output of the NAND gate 12 is connected to the NAND gate via the inverter 13.
A word line completion signal RX is applied to one input of the AND gate 14, and the other input of the NAND gate 14 is input manually.
It becomes D. The outputs of the NAND gates 11 and ]4 are input to one side of the NAND gate 15, and the other side is input manually, and the output of the NAND gate 15 and the signal RAS are input to the NAND gate 15.
AND gate] 6 is given as one input and the other input.

The output of this NAND gate 16 is the precharge signal PR.
Becomes I.

FIG. 5 is a circuit diagram showing a precharge signal generating circuit 20 that generates a precharge signal PR2 in the DRAM of this embodiment.

As shown in the figure, the synchronous inversion signal RAS of the external row address strobe signal RAS is taken in as one input of both the NAND gate 11 and the NAND gate 12, and
A row address signal RAO instructing selection of word line WLI is taken in as the other input of AND gate 11, and a row address signal RAO instructing selection of word line WL2 is taken in as the other input of NAND gate 12.

The configurations and input/output connections of the inverter 23 and NAND gates 24 to 26 are the same as those of the inverter 13 and NAND gates 24 to 26 shown in FIG.
The output of D gate 26 becomes precharge signal PR2.

FIG. 6 is a waveform diagram showing the operation of precharge signal generating circuits 10 and 20 shown in FIGS. 4 and 5, respectively. Hereinafter, the precharge operation will be explained with reference to the same figure, and the portion divided into the solid line part and the broken line part will be referred to the broken line part.

First, before time T1 when the synchronous inversion signal RAS becomes H level, the row address signal RAO5RAO and the word line completion signal RXD are both at the L level, so the outputs of the NAND gates 11 and 14 of the precharge signal generation circuit 10 are at the H level. , the output of the NAND gate 15 is high, and the precharge signal PRI, which is the output of the NAND gate 16, is high.

On the other hand, the outputs of the NAND gates 21 and 24 of the precharge signal generation circuit 20 are the output of the HSNAND gate 25, and the precharge signal PR2, which is the output of the NAND gate 26, is also high.

Then, after the signal RAS rises to H level at time T1, address signal RAO rises to H level at time T2, and row address signal RAO maintains L level. Then, the NAND gate 21 of the precharge signal generation circuit 20
The output of the NAND gate 25 is inverted to L, and the output of the NAND gate 25 is accordingly inverted to H, so the precharge signal PR2, which is the output of the NAND gate 26, falls to L. on the other hand,
In the precharge signal generation circuit 10, the outputs of NAND gates 1 and 14 maintain H, and the output of NAND gate 15 maintains L, so the precharge signal PRI, which is the output of NAND gate 16, maintains H.

Then, at time T3, when the selected word line WLI is raised to the H level by a row decoder (not shown), this is used as a trigger to cause the word line rise completion signal RXD to rise to the H level at time T4. Then, the output of the NAND gate 4 of the precharge signal generation circuit 10 is inverted to L, and the output of the NAND gate 15 is accordingly inverted to H, so that the precharge signal PRI, which is the output of the NAND gate 16, also reaches the time T5. and fall to L.

Then, at the end of the cycle, the signal RAS becomes L level and the other input of each of the NAND gates 16 and 26 becomes L, so that the precharge signals PR] and PH1 rise to H, and the pitch hm vs. BL1. ．． Precharging of BL2 is performed.

In this way, by raising the selected word line WL to H, the memory capacitor MCI to the selected bit line BLI is
At time T3 when the connection of the reference bit line B
Precharge potential of L2 (1/2 v cc)
Is it possible to keep it?

On the other hand, in FIG. 6, if we refer to the solid line part at the point where it is divided into the solid line part and the broken line part, we can see that the selected bit line is BL2.
, a refresh operation is performed using the reference bit line as BLI. Therefore, at time T3 when the memory capacitor MC2 is connected to the selected bit line BL2 by raising the selected word line WL2 to H, the precharge signal PR2 applied to the gate of the NMOS transistor Q5 on the reference bit line BLl side is set to H. By maintaining the level and continuing precharging, the potential of the reference bit line BLI can be maintained at the precharge potential.

In this embodiment, a read operation during refresh is taken as an example, but the present invention can of course be applied to a normal read operation as well.

Further, in this embodiment, a 1/2 Voc bit line precharge type DRAM is shown, but the present invention can be applied to other bit line precharge type DRAMs.

〔Effect of the invention〕

As described above, according to the present invention, the precharging means performs the precharging operation of the reference bit line even during the memory cell connection operation, thereby reducing the potential change when the memory cell is connected to the selected bit line. Based on this, it is possible to suppress potential changes that occur on the reference bit line due to capacitive coupling that occurs between the selected bit line and the reference bit line, so parasitic capacitance is formed between the selected bit line and the reference bit line due to increased integration. However, it has the effect of minimizing read voltage loss.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a part of a DRAM which is an embodiment of the present invention, Fig. 2 is a waveform diagram showing the refresh operation of the DRAM shown in Fig. 1, and Fig. 3 is a waveform diagram showing the refresh operation of the DRAM shown in Fig. 1. DRA
4 and 5 are circuit diagrams showing the DRAM precharge signal generation circuit shown in FIG. 1, and FIG. 6 is a waveform diagram showing its operation.
FIG. 7 is a circuit diagram showing a part of a conventional DRAM, FIG. 8 is a waveform diagram showing the refresh operation of the DRAM shown in FIG. 7, and FIG. 9 is a circuit diagram showing the DRAM signal lines shown in FIG. 7. It is an explanatory diagram showing potential. In the figure, 1 is a sense amplifier, MCI, MC2 is a memory capacitor, BLI, BL2 is a bit line, WLI, W
L2 is a word line, PRI, PH1 is a precharge signal,
Ql,,Q2. Q5. Q6 is an NMO3) transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure N L1 BL BL Figure Figure

Claims (1)

[Claims] (1) At the time of reading, a memory cell consisting of a capacitive component is connected to the selected bit line, which is one of the first and second bit lines, and selected based on the potential difference with the reference bit line, which is the other bit line. A semiconductor memory device of a type that reads data stored in a memory cell, the device comprising: a precharging unit that performs a precharging operation to set the selected bit line and the reference bit line to a predetermined potential; and a precharging operation of the selected bit line. After execution, a memory cell connection means for performing a memory cell connection operation of connecting the memory cell to the selected bit line; and after the memory cell connection operation, detecting a potential difference between the selected bit line and the reference bit line; and a sense amplifier that performs an amplifying read operation, and the precharging means continues the precharging operation of the reference bit line during the memory cell connection operation, and completes the precharging operation by the time of the read operation. A semiconductor memory device characterized by: