JPH0490626A - Interference compensating device - Google Patents

Interference compensating device

Info

Publication number
JPH0490626A
JPH0490626A JP20658890A JP20658890A JPH0490626A JP H0490626 A JPH0490626 A JP H0490626A JP 20658890 A JP20658890 A JP 20658890A JP 20658890 A JP20658890 A JP 20658890A JP H0490626 A JPH0490626 A JP H0490626A
Authority
JP
Japan
Prior art keywords
signal
input
circuit
output
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20658890A
Other languages
Japanese (ja)
Other versions
JP2951704B2 (en
Inventor
Toshiyuki Kaizuka
貝塚 俊之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP20658890A priority Critical patent/JP2951704B2/en
Publication of JPH0490626A publication Critical patent/JPH0490626A/en
Application granted granted Critical
Publication of JP2951704B2 publication Critical patent/JP2951704B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)

Abstract

PURPOSE:To simplify construction without necessitating a dual signal reception circuit by suppressing an interference wave in radio communication and receiving the only signal to be desired. CONSTITUTION:A modulator 12 modulating the output signal of a first signal synthesis circuit 4 by a low frequency signal with low frequency compared with the interference wave, a second signal synthesis circuit 6 synthesizing the modulation output of the modulator 12 and the second input signal, a signal reception circuit 5 taking the output signal of this circuit 6 as input to be converted to an intermediate frequency signal, a first phase detector 14 detecting the intermediate frequency signal by the synchronizing signal of a second input signal to be inputted, a second phase detector 15 detecting the intermediate frequency signal with a phase-transferred signal, two product detectors 7 and 8 taking the detection output of the two phase detectors 14 and 15 as input respectively and outputting them as control voltage after product-detection by a low frequency signal, are provided. Thus, the construction is simplified without necessitating the dual signal reception circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、無線通信の干渉補償装置に利用する。[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the interference compensation apparatus of wireless communication.

特に、干渉波を抑圧して希望する信号を受信する装置に
関するものである。
In particular, the present invention relates to a device that suppresses interference waves and receives a desired signal.

〔従来の技術〕[Conventional technology]

第2図は従来例の干渉補償装置のブロック構成図である
FIG. 2 is a block diagram of a conventional interference compensation device.

従来、干渉補償装置は、第2図に示すような構成であっ
た。第2図において、1.2は入力端子、3は振幅位相
制御回路、4は信号合成回路、5A。
Conventionally, an interference compensator has had a configuration as shown in FIG. In FIG. 2, 1.2 is an input terminal, 3 is an amplitude phase control circuit, 4 is a signal synthesis circuit, and 5A.

5Bは増幅器、周波数変換器および帯域濾波器などから
構成される信号受信回路、7.8は乗積検波器、10は
干渉波補償出力端子ならびに17は90゜移相器を示す
Reference numeral 5B indicates a signal receiving circuit composed of an amplifier, a frequency converter, a bandpass filter, etc., 7.8 a product detector, 10 an interference wave compensation output terminal, and 17 a 90° phase shifter.

入力端子1には通常の通信のための信号が入力するが、
干渉波も混入する。入力端子2には主に干渉波が入力す
る。入力端子2に入力した干渉波は2系統に分岐され、
一方の信号は振幅位相制御回路3でその振幅および位相
が制御され、入力端子1からの信号と信号合成回路4で
合成される。
Signals for normal communication are input to input terminal 1, but
Interference waves are also mixed in. Interference waves are mainly input to the input terminal 2. The interference wave input to input terminal 2 is branched into two systems,
One signal has its amplitude and phase controlled by an amplitude and phase control circuit 3, and is combined with the signal from the input terminal 1 by a signal synthesis circuit 4.

この合成信号と入力端子2の他方の信号とはそれぞれ信
号受信回路5A、5Bで周波数変換および増幅された後
、さらに2分岐され乗積検波器7.8で検波される。こ
のとき乗積検波器7.8に入力する四つの信号の内の一
つは90°移相器17で90”位相推移される。この乗
積検波器7.8の出力信号は入力端子1から入力される
干渉波と入力端子2から入力される干渉波との振幅が同
じで位相が反転するように振幅位相制御回路3を制御す
る。
This composite signal and the other signal at input terminal 2 are frequency-converted and amplified by signal receiving circuits 5A and 5B, respectively, and then branched into two and detected by product detector 7.8. At this time, one of the four signals input to the product detector 7.8 is shifted in phase by 90" by the 90° phase shifter 17. The output signal of the product detector 7.8 is input to the input terminal 1. The amplitude and phase control circuit 3 is controlled so that the interference wave input from the input terminal 2 and the interference wave input from the input terminal 2 have the same amplitude and reverse phase.

以上により干渉波補償出力端子10の出力に干渉波の含
まれない信号が得られる。
As described above, a signal containing no interference waves can be obtained in the output of the interference wave compensation output terminal 10.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、このような従来例の干渉補償装置では、信号受
信回路が2系統必要であり、また精度良く干渉波を抑圧
するためには両信号受信回路の位相および振幅の変動特
性を合わせる必要があり、そのために構成部品が多くそ
の振幅位相特性変動の調整などが難しい欠点があった。
However, such conventional interference compensation devices require two systems of signal receiving circuits, and in order to accurately suppress interference waves, it is necessary to match the phase and amplitude fluctuation characteristics of both signal receiving circuits. Therefore, it has the disadvantage that it has a large number of components, making it difficult to adjust the fluctuations in its amplitude and phase characteristics.

本発明は上記の欠点を解決するもので、信号受信回路が
2系統必要なく、かつ構成が簡易で調整の容易な干渉補
償装置を提供することを目的とする。
The present invention solves the above-mentioned drawbacks, and aims to provide an interference compensating device that does not require two signal receiving circuits, has a simple configuration, and is easy to adjust.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、希望受信波の他に干渉波が混入した第一の入
力信号を入力する第一の入力端子(1)と、上記干渉波
を主成分とする第二の入力信号を入力する第二の入力端
子(2〉と、入力する制御電圧に基づき上記第二の入力
信号を制御して上記第一の入力信号の干渉波と振幅がほ
ぼ等しく位相がほぼ反転した信号を出力する振幅位相制
御回路(3)と、この振幅位相制御回路の出力信号と上
記第一の入力信号とを合成して干渉波補償信号を出力す
る第一の信号合成回路(4)とを備えた干渉補償装置に
おいて、上記信号合成回路の出力信号を上記干渉波に比
して周波数の低い低周波信号により変調する変調器(1
2)と、この変調器の変調出力と上記第二の入力信号と
を合成する第二の信号合成回路(6)と、この第二の信
号合成回路の出力信号を入力とし中間周波信号に変換す
る信号受信回路(5)と、入力する上記第二の入力信号
の同期信号により上記中間周波信号を検波する第一の位
相検波器(14)および上記同期信号を90゜位相推移
させた信号により上記中間周波信号を検波する第二の位
相検波器(15)と、上記二つの位相検波器(14,1
5)の検波出力をそれぞれ入力とし上記低周波信号によ
りそれぞれ乗積検波して上記制御電圧として出力する二
つの乗積検波器(7,8)とを備えたことを特徴とする
The present invention comprises a first input terminal (1) to which a first input signal mixed with interference waves in addition to the desired received wave is input, and a second input terminal (1) to which a second input signal having the interference wave as a main component is input. a second input terminal (2>) and an amplitude phase that controls the second input signal based on the input control voltage and outputs a signal whose amplitude is almost equal to that of the interference wave of the first input signal and whose phase is almost reversed. An interference compensation device comprising a control circuit (3) and a first signal synthesis circuit (4) that synthesizes the output signal of the amplitude phase control circuit and the first input signal to output an interference wave compensation signal. a modulator (1) that modulates the output signal of the signal synthesis circuit with a low frequency signal having a lower frequency than the interference wave;
2), a second signal synthesis circuit (6) that synthesizes the modulated output of this modulator and the second input signal, and the output signal of this second signal synthesis circuit is input and converted into an intermediate frequency signal. a first phase detector (14) that detects the intermediate frequency signal using a synchronization signal of the second input signal, and a signal obtained by shifting the phase of the synchronization signal by 90 degrees. a second phase detector (15) that detects the intermediate frequency signal; and a second phase detector (15) that detects the intermediate frequency signal;
The present invention is characterized in that it includes two product detectors (7, 8) each receiving the detection output of 5), performing product detection using the low frequency signal, and outputting the product as the control voltage.

また、本発明は、上記変調器(12)は振幅変調器であ
ることができる。
Further, in the present invention, the modulator (12) may be an amplitude modulator.

さらに、本発明は、上記信号受信回路(5)には自動利
得制御手段を含むことができる。
Further, in the present invention, the signal receiving circuit (5) may include automatic gain control means.

また、本発明は、上記第二の入力信号が所定レベル以下
であるとき上記振幅位相制御回路の出力を無効とする手
段を備えることができる。
Further, the present invention may include means for invalidating the output of the amplitude and phase control circuit when the second input signal is below a predetermined level.

〔作用〕[Effect]

変調器(12)は信号合成回路(4)の出力信号に混入
する干渉波をこの干渉波に比して周波数の低い低周波信
号により変調する。信号合成回路(6)はこの変調器の
変調出力と第二の入力信号とを合成する。信号受信回路
(5)は第二の信号合成回路の出力信号を入力とし中間
周波信号に変換する。第一の位相検波器(14)は入力
する第二の入力信号に同期した同期信号により上記中間
周波信号を検波し、第二の位相検波器(15)は上記同
期信号を90°位相推移させた信号により上記中間周波
信号を検波する。さらに、二つの乗積検波器(7,8)
は上記二つの位相検波器の検波出力の直流分をそれぞれ
カットして上記低周波信号により乗積検波し、低域濾波
器でこの乗積検波出力の直流成分を取出し制御電圧とし
て振幅位相制御回路に与える。
The modulator (12) modulates the interference wave mixed in the output signal of the signal synthesis circuit (4) with a low frequency signal whose frequency is lower than that of the interference wave. A signal combining circuit (6) combines the modulated output of this modulator and the second input signal. The signal receiving circuit (5) receives the output signal of the second signal synthesis circuit and converts it into an intermediate frequency signal. The first phase detector (14) detects the intermediate frequency signal using a synchronization signal synchronized with the input second input signal, and the second phase detector (15) shifts the phase of the synchronization signal by 90°. The intermediate frequency signal is detected by the detected signal. Furthermore, two product detectors (7, 8)
Cuts the DC components of the detection outputs of the two phase detectors, performs product detection using the low frequency signal, extracts the DC component of the product detection output using a low-pass filter, and uses it as a control voltage in the amplitude phase control circuit. give to

また、信号受信回路(5)の自動利得制御手段は位相検
波器の直流分出力が一定になるように自動利得制御をか
けて第二の入力信号のレベル変動に対して安定な補償動
作が得られるようにすることができる。
Further, the automatic gain control means of the signal receiving circuit (5) performs automatic gain control so that the DC component output of the phase detector is constant, so that a stable compensation operation can be achieved with respect to level fluctuations of the second input signal. You can make it possible to

さらに、第二の入力信号が所定レベル以下であるときに
は、干渉波がなくなったものとして振幅位相制御回路の
出力を無効とし熱雑音などによる希望受信波に対する有
害な影響を防止する。
Furthermore, when the second input signal is below a predetermined level, it is assumed that there is no interference wave and the output of the amplitude phase control circuit is invalidated to prevent harmful effects such as thermal noise on the desired received wave.

以上により信号受信回路が2系統必要なくなり、かつ構
成が簡易で調整が容易にできる。
As a result of the above, two systems of signal receiving circuits are not required, and the configuration is simple and adjustment can be made easily.

〔実施例〕〔Example〕

本発明の実施例について図面を参照して説明する。第1
図は本発明一実施例干渉補償装置のブロック構成図であ
る。第3図は本発明の干渉補償装置の振幅位相制御回路
のブロック構成図である。
Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of an interference compensation device according to an embodiment of the present invention. FIG. 3 is a block diagram of the amplitude and phase control circuit of the interference compensator of the present invention.

第1図において、干渉補償装置は、希望受信波の他に干
渉波が混入した第一の入力信号を入力する第一の入力端
子として入力端子1と、上記干渉波を主成分とする第二
の入力信号を入力する第二の入力端子として入力端子2
と、入力する制御電圧に基づき上記第二の入力信号を制
御して上記第一の入力信号の干渉波と振幅がほぼ同じで
位相がほぼ反転した信号を出力する振幅位相制御回路3
と、振幅位相制御回路3の出力信号と上記第一の入力信
号とを合成して干渉波補償信号を出力する第一の信号合
成回路として信号合成回路4と、この干渉波補償信号を
出力する干渉波補償出力端子10とを備える。
In FIG. 1, the interference compensator has an input terminal 1 as a first input terminal to which a first input signal mixed with interference waves in addition to the desired received wave is input, and a second input terminal whose main component is the interference wave. Input terminal 2 serves as the second input terminal for inputting the input signal of
and an amplitude phase control circuit 3 which controls the second input signal based on the input control voltage and outputs a signal having substantially the same amplitude and substantially inverted phase as the interference wave of the first input signal.
and a signal synthesis circuit 4 as a first signal synthesis circuit which synthesizes the output signal of the amplitude phase control circuit 3 and the first input signal and outputs an interference wave compensation signal, and outputs this interference wave compensation signal. and an interference wave compensation output terminal 10.

ここで本発明の特徴とするところは、信号合成回路4の
出力信号を上記干渉波に比して周波数の低い低周波信号
により変調する変調器として変調器12および低周波発
振器11と、変調器12の変調出力と上記第二の入力信
号とを合成する第二の信号合成回路として信号合成回路
6と、信号合成回路6の出力信号を入力とし中間周波信
号に変換する信号受信回路5と、入力する上記第二の入
力信号に同期した同期信号により上記中間周波信号に同
期した同期信号により上記中間周波信号を検波する第一
の位相検波器として位相検波器14および上記同期信号
を90°位相推移させた信号により上記中間周波信号を
検波する第二の位相検波器として位相検波器15と、位
相検波器15の検波出力を低域濾波器27を介して入力
し上記同期信号を出力する電圧制御発振器13と、二つ
の位相検波器14.15の検波出力をそれぞれ高域濾波
器21.22を介して入力し上記低周波信号によりそれ
ぞれ乗積検波し低域濾波器23.24および直流積分回
路25.26を介して上記制御電圧として出力する二つ
の乗積検波器7.8とを備えたことにある。
Here, the present invention is characterized in that a modulator 12 and a low frequency oscillator 11 are used as a modulator for modulating the output signal of the signal synthesis circuit 4 with a low frequency signal whose frequency is lower than that of the interference wave. a signal synthesizing circuit 6 as a second signal synthesizing circuit that synthesizes the modulated output of 12 and the second input signal; a signal receiving circuit 5 that receives the output signal of the signal synthesizing circuit 6 and converts it into an intermediate frequency signal; A phase detector 14 as a first phase detector detects the intermediate frequency signal using a synchronizing signal synchronized with the second input signal to be input, and a synchronizing signal synchronized with the intermediate frequency signal. A phase detector 15 serves as a second phase detector that detects the intermediate frequency signal using the shifted signal, and a voltage that inputs the detection output of the phase detector 15 via a low-pass filter 27 and outputs the synchronization signal. The detected outputs of the controlled oscillator 13 and the two phase detectors 14 and 15 are inputted through high-pass filters 21 and 22, respectively, and subjected to product detection using the above-mentioned low frequency signals. Two product detectors 7.8 are provided which output the control voltages via circuits 25 and 26.

また、変調器12は振幅変調器である。Moreover, the modulator 12 is an amplitude modulator.

さらに、信号受信回路5には自動利得制御手段を含む。Further, the signal receiving circuit 5 includes automatic gain control means.

また、上記第二の入力信号が所定レベル以下であるとき
振幅位相制御回路3の出力を無効とする手段として位相
検波器14の出力に接続されたスイッチ16を備える。
Further, a switch 16 connected to the output of the phase detector 14 is provided as means for invalidating the output of the amplitude and phase control circuit 3 when the second input signal is below a predetermined level.

第3図は干渉補償装置の振幅位相制御回路のブロック構
成図である。第3図において、31は入力端子、32は
信号分岐回路、33a〜33dは固定移相器、34a 
〜34dはPINダイオード減衰器、35は信号合成器
、36a 、 36bは制御信号入力端子および37は
出力端子である。第3図の構成および動作については特
公昭62−16580号公報に詳細な説明がある。
FIG. 3 is a block diagram of the amplitude and phase control circuit of the interference compensator. In FIG. 3, 31 is an input terminal, 32 is a signal branch circuit, 33a to 33d are fixed phase shifters, and 34a is a signal branch circuit.
34d is a PIN diode attenuator, 35 is a signal combiner, 36a and 36b are control signal input terminals, and 37 is an output terminal. The structure and operation of FIG. 3 are explained in detail in Japanese Patent Publication No. 16580/1983.

このような構成の干渉補償装置の動作について説明する
。第1図において、入力端子2に入力した干渉波は、2
分岐されて振幅位相制御回路3および信号受信回路5に
入力される。この2分岐された信号は複素表示により次
のように表せる。
The operation of the interference compensation device having such a configuration will be explained. In Fig. 1, the interference wave input to input terminal 2 is 2
The signal is branched and input to the amplitude phase control circuit 3 and the signal receiving circuit 5. This two-branched signal can be expressed in complex form as follows.

IA=i、 ejか lA二入力端子2に入力する干渉波する振幅Ω :干渉
波角周波数 振幅位相制御回路3では制御電圧v1、v2に対して、
出力信号を次のように制御し出力する。
IA=i, ej or lA Amplitude Ω of the interference wave input to the two input terminals 2: In the interference wave angular frequency amplitude phase control circuit 3, for the control voltages v1 and v2,
The output signal is controlled and output as follows.

Iv =  Kv  (V+ + J V2 )  I
A−KvViA ej(ΩL+〆) Kv:振幅位相制御回路の制御感度 V ejf’= V、 + j V3 この振幅位相制御回路3の出力信号は、信号合成回路4
で入力端子1からの信号と合成される。
Iv = Kv (V+ + J V2) I
A-KvViA ej(ΩL+〆) Kv: Control sensitivity of the amplitude phase control circuit V ejf'= V, + j V3 The output signal of this amplitude phase control circuit 3 is transmitted to the signal synthesis circuit 4
It is combined with the signal from input terminal 1.

このときに入力端子1からの干渉波信号は次式で表され
、 ■つ=1we io 二入力端子1に入力する干渉波の振幅α:入力端
子1に入力する干渉波と入力端子2に入力する干渉波と
の位相差 合成信号は次式となる。
At this time, the interference wave signal from input terminal 1 is expressed by the following formula, ■ = 1we io Amplitude α of interference wave input to two input terminals 1: Interference wave input to input terminal 1 and input to input terminal 2 The phase difference composite signal with the interference wave is given by the following equation.

1、 = i、 ej(fLt+メン −K V V 
I A eJ (Q(+メ1:=: r e J (O
L本θ〕 ただし、re”=iXe”−に、ViAe’1この合成
信号に低周波信号発振器11の出力で変調器12におい
て、「オン」−「オフ」の振幅変調を行うと実数表示で
次式のように表わせる。
1, = i, ej(fLt+men -K V V
I A eJ (Q(+Me1:=: r e J (O
L lines θ] However, if re"=iXe"-, ViAe'1 This composite signal is subjected to "on"-"off" amplitude modulation in the modulator 12 using the output of the low frequency signal oscillator 11, and then it is expressed as a real number. It can be expressed as the following formula.

I+’=rsin(Ωt+θ) (1/2+ (2/π) cos  (2n−1)  ωt) ω:変調信号角周波数 これを入力端子2の入力信号と信号合成回路6において
合成すると次式になる。
I+'=rsin(Ωt+θ) (1/2+ (2/π) cos (2n-1) ωt) ω: Modulation signal angular frequency When this is combined with the input signal of input terminal 2 in signal synthesis circuit 6, the following equation is obtained. .

5=iA sinΩt+rsin(Ωt+θ)(1/2
+ (2/π) cos  (2n−1)  ωt) 次に電圧制御発振器13の出力As1nΩtで位相検波
器14において検波すると、 Sn+= (IA A/2)(1cos2Ωt)+(r
A/4)(cosθ −cos (2Ωを十θ)) ÷(rA/π)(cosθ −cos (2Ωt+θ)) cos  (2n−1)  ωt) この5ellの直流分を低域濾波器で取出し、この直流
分出力が一定となるように自動利得制御(AGC)かけ
る。すなわち低域濾波器で取出した直流電圧は、 IAA/ま ただし、iA>r となり、これに基づきAGCによる増幅利得をK / 
(IA A / 2 ) Kニ一定 とすると、SDIは次式となる。
5=iA sinΩt+rsin(Ωt+θ)(1/2
+ (2/π) cos (2n-1) ωt) Next, when the output As1nΩt of the voltage controlled oscillator 13 is detected by the phase detector 14, Sn+= (IA A/2)(1cos2Ωt)+(r
A/4) (cosθ - cos (2Ω to 10θ)) ÷ (rA/π) (cosθ - cos (2Ωt+θ)) cos (2n-1) ωt) The DC component of this 5ell is extracted with a low-pass filter, Automatic gain control (AGC) is applied so that this DC output is constant. In other words, the DC voltage taken out by the low-pass filter is IAA/, where iA>r, and based on this, the amplification gain by AGC is K/
(IA A/2) If K is constant, SDI is expressed as follows.

Sa+  =K(I  CO52Ωt)+  (Kr/
iA)  (cosθ cos(2Ωt+θ)) ((1−2)+  (2/π) cos  (2n−1)act) 本式の直流成分をコンデンサなどの高域濾波器21によ
りカットし、変調信号、すなわち低周波信号発振器11
の出力信号でさらに乗積検波すると、次式を得る。ただ
し、高調波成分(2Ωを含む成分)は省略する。
Sa+ =K(I CO52Ωt)+ (Kr/
iA) (cosθ cos(2Ωt+θ)) ((1-2)+ (2/π) cos (2n-1)act) The DC component of this formula is cut by a high-pass filter 21 such as a capacitor, and the modulated signal, That is, the low frequency signal oscillator 11
Further product detection is performed on the output signal of , and the following equation is obtained. However, harmonic components (components including 2Ω) are omitted.

e+ = (2Kr/πi、)cosθcos  (2
n−1)(lJt) (1/2+  (2/π) cos  (2n−1)act) この検波出力の直流成分を低域濾波器23および直流積
分回路25により得る。すなわち、乗積検波器7の出力
制御電圧E1は、 E、= (2/π2)(r/1A)cosθまた、Sを
電圧制御発振器13の出力を90°位相推移させた信号
で検波すると次式になり、SD2’ =Ks i n 
2Ωを十(Kr/1A)(sinθ+5in(2Ωt+
θ)) (1/2+ (2/π) 1 、 =t Ae J In t ” m ]   
KvV I AeJ [” t”〆)−Kv (2KG
/π2)roj[Ωt+σ)= (1−2Kv  KG
/rr2)r eJC”θ)制御ループ利得2KvKG
/π2を適切に設定すればIi+は最終的に「0」とな
り、干渉波が抑圧され、干渉波補償出力端子10から希
望波のみの信号が得られる。
e+ = (2Kr/πi,)cosθcos (2
n-1) (lJt) (1/2+ (2/π) cos (2n-1) act) A DC component of this detection output is obtained by a low-pass filter 23 and a DC integration circuit 25. That is, the output control voltage E1 of the multiplicative product detector 7 is E, = (2/π2) (r/1A) cosθ.If S is detected by a signal obtained by shifting the output of the voltage controlled oscillator 13 by 90°, then the following equation can be obtained. The formula becomes, SD2' = Ks i n
2Ω to 10 (Kr/1A) (sinθ+5in(2Ωt+
θ)) (1/2+ (2/π) 1, =t Ae J In t ” m ]
KvV I AeJ [”t”〆)-Kv (2KG
/π2)roj[Ωt+σ)=(1-2Kv KG
/rr2) r eJC”θ) Control loop gain 2KvKG
If /π2 is appropriately set, Ii+ will eventually become "0", the interference wave will be suppressed, and a signal containing only the desired wave will be obtained from the interference wave compensation output terminal 10.

また、rQJ   rπ」の位相変調を行うとすると、
変調信号は、 cos  (2n−1)  ωt) さらに、変調信号で乗積検波した直流成分として次式を
得る。すなわち、乗積検波器8の出力制御電圧は、 E2 = (2/π2)(r/1A)s inθこの二
つの制御電圧1、E2を適切な利得Gで増幅し、上述の
制御電圧v1、v2に加算して制御すると、信号合成回
路4の出力信号は次式となり、cos  (2n−1)
  cc+t となり、同様の過程をもって干渉補償が可能である。「
オン」−「オフ」またはrQJ   rπ」変調のよう
に高調波を含む変調波ではなく正弦波によっても干渉波
補償が可能である。
Also, if we perform phase modulation of ``rQJ rπ'',
The modulated signal is cos (2n-1) ωt) Furthermore, the following equation is obtained as a DC component obtained by product detection using the modulated signal. That is, the output control voltage of the multiplicative detector 8 is E2 = (2/π2) (r/1A) sin θ These two control voltages 1 and E2 are amplified with an appropriate gain G, and the above control voltage v1, When controlled by adding it to v2, the output signal of the signal synthesis circuit 4 becomes the following formula, cos (2n-1)
cc+t, and interference compensation is possible through a similar process. "
Interference wave compensation is also possible using a sine wave rather than a modulated wave including harmonics such as "on"-"off" or rQJ rπ" modulation.

また、電圧制御発振器13を入力信号に同期させる方法
はS [12’の直流成分を「O」になるように制御す
る位相同期ループや他の搬送波再生回路によって実現可
能である。ただし、位相同期ループにおいて「オン」−
「オフ」変調の場合は干渉補償誤差が大きいときには同
期誤差が発生するが補償動作がある程度進行すると同期
誤差は無視することができる。
Further, the method of synchronizing the voltage controlled oscillator 13 with the input signal can be realized by a phase-locked loop or other carrier wave recovery circuit that controls the DC component of S[12' to become "O". However, in a phase-locked loop, “on” −
In the case of "off" modulation, a synchronization error occurs when the interference compensation error is large, but once the compensation operation has progressed to a certain extent, the synchronization error can be ignored.

以上の説明はAGCを行う場合についてであるが、AG
Cを行わなくても干渉波の補償は可能である。しかし、
入力干渉波のレベル変動に対してループ利得が変動する
ため補償動作が不安定となる。このためにAGCをかけ
たほうが安定な補償動作が得られる。
The above explanation is about the case where AGC is performed.
It is possible to compensate for interference waves without performing C. but,
Since the loop gain fluctuates in response to level fluctuations of the input interference wave, the compensation operation becomes unstable. For this reason, a more stable compensation operation can be obtained by applying AGC.

また、干渉となる信号の送信が停止されるなどの場合に
は干渉補償装置は熱雑音などに対して動作するた約希望
波に有害な影響を与える可能性がある。このたtに、干
渉波が存在するときだけ干渉補償を行うようにしたほう
がよい。すなわち、入力端子2の入力信号の干渉波レベ
ルを検出し、干渉波が検出されないときには入力端子1
の入力信号に入力端子2の入力信号が合成されないよう
にする必要がある。具体的にはAGCの制御電圧を監視
し、雑音レベル以上の規定レベルに相当する電圧が検出
されたときに振幅位相制御回路3の出力信号に設けたス
イッチ16を「オン」にするように制御する方法などが
考えられる。
Furthermore, if the transmission of an interfering signal is stopped, the interference compensator operates against thermal noise, etc., and may have a detrimental effect on the desired wave. In addition, it is better to perform interference compensation only when interference waves exist. In other words, the interference wave level of the input signal of input terminal 2 is detected, and when no interference wave is detected, the level of the interference wave of the input signal of input terminal 2 is detected.
It is necessary to prevent the input signal of input terminal 2 from being combined with the input signal of input terminal 2. Specifically, the control voltage of the AGC is monitored, and when a voltage corresponding to a specified level higher than the noise level is detected, the switch 16 provided for the output signal of the amplitude phase control circuit 3 is controlled to be turned on. There are ways to do this.

〔発明の効果〕 以上説明したように、本発明は、信号受信回路が2系統
必要なく、かつ構成が簡易で調整が容易な優れた効果が
ある。
[Effects of the Invention] As described above, the present invention has excellent effects in that two signal receiving circuits are not required, and the configuration is simple and adjustment is easy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明一実施例干渉補償装置のブロック構成図
。 第2図は従来例の干渉補償装置のブロック構成図。 第3図は干渉補償装置の振幅位相制御回路のブロック構
成図。 1.2・・・入力端子、3・・・振幅位相制御回路、4
.6・・・信号合成回路、5.5A、5B・・・信号受
信回路、7.8・・・乗積検波器、9.17・・・90
°移相器、10・・・干渉補償出力端子、11・・・低
周波信号発振器、12・・・変調器、13・・・電圧制
御発振器、14.15・・・位相検波器、16・・・ス
イッチ、21.22・・・高域濾波器(HPF)、23
.24.27・・・低濾波器(LPF)、25.26・
・・直流積分回路、31・・・入力端子、32・・・信
号分岐回路、33a〜33d・・・固定移相器、34a
〜34d・・・PINダイオード減衰器、35・・・信
号合成器、36a、36b・・・制御信号入力端子、3
7・・・出力端子。 特許出願人 日本電信電話株式会社 代理人  弁理士  井 出 直 孝
FIG. 1 is a block diagram of an interference compensation device according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional interference compensation device. FIG. 3 is a block diagram of the amplitude and phase control circuit of the interference compensator. 1.2... Input terminal, 3... Amplitude phase control circuit, 4
.. 6... Signal synthesis circuit, 5.5A, 5B... Signal receiving circuit, 7.8... Product detector, 9.17...90
° Phase shifter, 10... Interference compensation output terminal, 11... Low frequency signal oscillator, 12... Modulator, 13... Voltage controlled oscillator, 14.15... Phase detector, 16... ...Switch, 21.22...High-pass filter (HPF), 23
.. 24.27...Low filter (LPF), 25.26.
...DC integration circuit, 31...Input terminal, 32...Signal branch circuit, 33a to 33d...Fixed phase shifter, 34a
~34d...PIN diode attenuator, 35...signal combiner, 36a, 36b...control signal input terminal, 3
7...Output terminal. Patent applicant: Nippon Telegraph and Telephone Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

【特許請求の範囲】 1、希望受信波の他に干渉波が混入した第一の入力信号
を入力する第一の入力端子(1)と、上記干渉波を主成
分とする第二の入力信号を入力する第二の入力端子(2
)と、入力する制御電圧に基づき上記第二の入力信号を
制御して上記第一の入力信号の干渉波と振幅がほぼ同じ
で位相がほぼ反転した信号を出力する振幅位相制御回路
(3)と、この振幅位相制御回路の出力信号と上記第一
の入力信号とを合成して干渉波補償信号を出力する第一
の信号合成回路(4)とを備えた 干渉補償装置において、 上記信号合成回路の出力信号を上記干渉波に比して周波
数の低い低周波信号により変調する変調器(12)と、
この変調器の変調出力と上記第二の入力信号とを合成す
る第二の信号合成回路(6)と、この第二の信号合成回
路の出力信号を入力とし中間周波信号に変換する信号受
信回路(5)と、入力する上記第二の入力信号の同期信
号により上記中間周波信号を検波する第一の位相検波器
(14)および上記同期信号を90゜位相推移させた信
号により上記中間周波信号を検波する第二の位相検波器
(15)と、上記二つの位相検波器(14、15)の検
波出力をそれぞれ入力とし上記低周波信号によりそれぞ
れ乗積検波して上記制御電圧として出力する二つの乗積
検波器(7、8)とを備えたことを特徴とする干渉補償
装置。 2、上記変調器(12)は振幅変調器である請求項1記
載の干渉補償装置。 3、上記信号受信回路(5)には自動利得制御手段を含
む請求項1記載の干渉補償装置。4、上記第二の入力信
号が所定レベル以下であるとき上記振幅位相制御回路の
出力を無効とする手段を備えた請求項1記載の干渉補償
装置。
[Claims] 1. A first input terminal (1) into which a first input signal mixed with an interference wave in addition to the desired received wave is input, and a second input signal whose main component is the interference wave. The second input terminal (2
), and an amplitude phase control circuit (3) that controls the second input signal based on the input control voltage and outputs a signal having substantially the same amplitude and substantially inverted phase as the interference wave of the first input signal. and a first signal combining circuit (4) that combines the output signal of the amplitude phase control circuit and the first input signal to output an interference wave compensation signal, the signal combining circuit comprising: a modulator (12) that modulates the output signal of the circuit with a low frequency signal having a lower frequency than the interference wave;
a second signal synthesis circuit (6) that synthesizes the modulated output of this modulator and the second input signal; and a signal reception circuit that receives the output signal of this second signal synthesis circuit and converts it into an intermediate frequency signal. (5), a first phase detector (14) that detects the intermediate frequency signal using the synchronization signal of the second input signal; a second phase detector (15) that detects the voltage, and a second phase detector (15) that receives the detection outputs of the two phase detectors (14, 15) as inputs, performs product detection using the low frequency signal, and outputs the control voltage as the control voltage. An interference compensation device characterized by comprising two multiplicative detectors (7, 8). 2. The interference compensation device according to claim 1, wherein the modulator (12) is an amplitude modulator. 3. The interference compensation device according to claim 1, wherein the signal receiving circuit (5) includes automatic gain control means. 4. The interference compensation device according to claim 1, further comprising means for invalidating the output of the amplitude and phase control circuit when the second input signal is below a predetermined level.
JP20658890A 1990-08-03 1990-08-03 Interference compensator Expired - Fee Related JP2951704B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20658890A JP2951704B2 (en) 1990-08-03 1990-08-03 Interference compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20658890A JP2951704B2 (en) 1990-08-03 1990-08-03 Interference compensator

Publications (2)

Publication Number Publication Date
JPH0490626A true JPH0490626A (en) 1992-03-24
JP2951704B2 JP2951704B2 (en) 1999-09-20

Family

ID=16525891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20658890A Expired - Fee Related JP2951704B2 (en) 1990-08-03 1990-08-03 Interference compensator

Country Status (1)

Country Link
JP (1) JP2951704B2 (en)

Also Published As

Publication number Publication date
JP2951704B2 (en) 1999-09-20

Similar Documents

Publication Publication Date Title
US6317589B1 (en) Radio receiver and method of operation
US6255912B1 (en) Phase lock loop used as up converter and for reducing phase noise of an output signal
US4420723A (en) Phase locked loop amplifier for variable amplitude radio waves
US5771442A (en) Dual mode transmitter
US5359412A (en) Optical frequency discriminator using two mach-zehnder interferometer arrangement
US5446421A (en) Local oscillator phase noise cancelling modulation technique
US6671337B1 (en) Carrier modulator for use in a transmitter or transceiver
KR20010102100A (en) Transmitter image suppression in tdd transceivers
TW517480B (en) Wireless transceiver with subtractive filter compensating both transmit and receive artifacts
JP3709032B2 (en) Radar system
EP0883237A1 (en) Radio receiver and method of operation
US6614837B1 (en) Device system and method for low noise radio frequency transmission
US6617932B2 (en) System and method for wide dynamic range clock recovery
JPH0490626A (en) Interference compensating device
JPS60172842A (en) Controller of optical reception circuit
JPH0490625A (en) Interference compensating device
US1885009A (en) Method and means for electrical signaling and control
JP2679445B2 (en) Transmission power control method
JPH0774684A (en) Radio communication system and equipment
JPS6126253B2 (en)
US4114111A (en) Constant phase delay network having a coherent reference
JPS6022830A (en) Heterodyne type transmitter
US4139823A (en) Electrical energy transmission network
KR100650589B1 (en) Mobile communication terminal having a frequency transferring device and controlling method therefore
JPS63155932A (en) Interference wave extracting circuit

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees