JPH0490625A - Interference compensating device - Google Patents

Interference compensating device

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Publication number
JPH0490625A
JPH0490625A JP20658790A JP20658790A JPH0490625A JP H0490625 A JPH0490625 A JP H0490625A JP 20658790 A JP20658790 A JP 20658790A JP 20658790 A JP20658790 A JP 20658790A JP H0490625 A JPH0490625 A JP H0490625A
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JP
Japan
Prior art keywords
signal
input
output
circuit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20658790A
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Japanese (ja)
Other versions
JP2951703B2 (en
Inventor
Toshiyuki Kaizuka
貝塚 俊之
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Nippon Telegraph and Telephone Corp
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Nippon Telegraph and Telephone Corp
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Priority to JP20658790A priority Critical patent/JP2951703B2/en
Publication of JPH0490625A publication Critical patent/JPH0490625A/en
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Abstract

PURPOSE:To simplify construction without necessitating a dual signal reception circuit by suppressing the interference wave in radio communication and receiving only the signal to be desired. CONSTITUTION:A first modulator 12 modulating the output signal of a first signal synthesis circuit 4 by a low frequency signal with low frequency compared with the interference wave, a second modulator 13 modulating this low frequency signal 90 deg. phase-transferring the output signal by the signal phase-transferred by 90 deg., a second signal synthesis circuit 16 synthesizing the modulation output of modulators 12,13, a signal reception circuit 5 taking the output of this circuit 16 as input to be converted to an intermediate frequency signal, an envelope detector 9 envelope-detecting this intermediate frequency signal, and two product detectors 7,8 respectively taking the output of the envelope detector 9 as input, product-detecting the low frequency signal and the phase of the low frequency signal after phase-transferred by 90 deg. to be outputted as control voltage, are provided. Thus, the dual signal reception circuit is not unnecessitated and the construction is simplified.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、無線通信の干渉補償装置に利用する。[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the interference compensation apparatus of wireless communication.

特に、干渉波を抑圧して希望する信号を受信する装置に
関するものである。
In particular, the present invention relates to a device that suppresses interference waves and receives a desired signal.

〔従来の技術〕[Conventional technology]

第2図は従来例の干渉補償装置のブロック構成図である
FIG. 2 is a block diagram of a conventional interference compensation device.

従来、干渉補償装置は、第2図に示すような構成であっ
た。第2図において、1.2は入力端子、3は振幅位相
制御回路、4は信号合成回路、5A、5Bは増幅器、周
波数変換器および帯域濾波器などから構成される信号受
信回路、7.8は乗積検波器、10は干渉波補償出力端
子ならびに17は90゜移相器を示す。
Conventionally, an interference compensator has had a configuration as shown in FIG. In FIG. 2, 1.2 is an input terminal, 3 is an amplitude phase control circuit, 4 is a signal synthesis circuit, 5A, 5B is a signal receiving circuit composed of an amplifier, a frequency converter, a bandpass filter, etc., 7.8 10 indicates a multiplicative detector, 10 indicates an interference wave compensation output terminal, and 17 indicates a 90° phase shifter.

入力端子1には通常の通信のための信号が入力するが、
干渉波も混入する。入力端子2には主に干渉波が入力す
る。入力端子2に入力した干渉波は2系統に分岐され、
一方の信号は振幅位相制御回路3でその振幅および位相
が制御され、入力端子1からの信号と信号合成回路4で
合成される。
Signals for normal communication are input to input terminal 1, but
Interference waves are also mixed in. Interference waves are mainly input to the input terminal 2. The interference wave input to input terminal 2 is branched into two systems,
One signal has its amplitude and phase controlled by an amplitude and phase control circuit 3, and is combined with the signal from the input terminal 1 by a signal synthesis circuit 4.

この合成信号と入力端子2の他方の信号とはそれぞれ信
号受信回路5A、5Bで周波数変換および増幅された後
、さらに2分岐され乗積検波器7.8で検波される。こ
のとき乗積検波器7.8に入力する四つの信号の内の一
つは90°移相器17で90゜位相推移される。この乗
積検波器7.8の出力信号は入力端子1から入力される
干渉波と入力端子2から入力される干渉波との振幅が同
じで位相が反転するように振幅位相制御回路3を制御す
る。
This composite signal and the other signal at input terminal 2 are frequency-converted and amplified by signal receiving circuits 5A and 5B, respectively, and then branched into two and detected by product detector 7.8. At this time, one of the four signals input to the product detector 7.8 is phase shifted by 90° by the 90° phase shifter 17. The output signal of the product detector 7.8 controls the amplitude and phase control circuit 3 so that the interference wave input from input terminal 1 and the interference wave input from input terminal 2 have the same amplitude and reverse phase. do.

以上により干渉波補償出力端子10の出力に干渉波の含
まれない信号が得られる。
As described above, a signal containing no interference waves can be obtained in the output of the interference wave compensation output terminal 10.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、このような従来例の干渉補償装置では、信号受
信回路が2系統必要であり、また精度良く干渉波を抑圧
するためには両信号受信回路の位相および振幅の変動特
性を合わせる必要があり、そのために構成部品が多くそ
の振幅位相特性変動の調整などが難しい欠点があった。
However, such conventional interference compensation devices require two systems of signal receiving circuits, and in order to accurately suppress interference waves, it is necessary to match the phase and amplitude fluctuation characteristics of both signal receiving circuits. Therefore, it has the disadvantage that it has a large number of components, making it difficult to adjust the fluctuations in its amplitude and phase characteristics.

本発明は上記の欠点を解決するもので、信号受信回路が
2系統必要な(、かつ構成が簡易で調整の容易な干渉補
償装置を提供することを目的とする。
The present invention solves the above-mentioned drawbacks, and aims to provide an interference compensating device that requires two signal receiving circuits (and has a simple configuration and easy adjustment).

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、希望受信波の他に干渉波が混入した第一の入
力信号を入力する第一の入力端子(1)と、上記干渉波
を主成分とする第二の入力信号を入力する第二の入力端
子(2)と、入力する制御電圧に基づき上記第二の入力
信号を制御して上記第一の入力信号の干渉波と振幅がほ
ぼ同じで位相がほぼ反転した信号を出力する振幅位相制
御回路(3)と、この振幅位相制御回路の出力信号と上
記第一の入力信号とを合成して干渉波補償信号を出力す
る第一の信号合成回路(4)とを備えた干渉補償装置に
おいて、上記信号合成回路の出力信号を上記干渉波に比
して周波数の低い低周波信号により変調する第一の変調
器(12)および上記出力信号を90°位相推移させた
信号をこの低周波信号を90°位相推移させた信号によ
り変調する第二の変調器(13)と、この二つの変調器
(12,13)の変調出力を合成する第二の信号合成回
路(16)と、この第二の信号合成回路の出力を入力と
し中間周波信号に変換する信号受信回路(5)と、この
中間周波信号を包絡線検波する包絡線検波器(9)と、
この包絡線検波器の出力をそれぞれ入力とし上記低周波
信号および上記低周波信号の位相を90’位相推移させ
た信号でそれぞれ乗積検波して上記制御電圧として出力
する二つの乗積検波器(7,8)とを備えたことを特徴
とする。
The present invention comprises a first input terminal (1) to which a first input signal mixed with interference waves in addition to the desired received wave is input, and a second input terminal (1) to which a second input signal having the interference wave as a main component is input. a second input terminal (2), and an amplitude that controls the second input signal based on the input control voltage and outputs a signal having approximately the same amplitude and almost inverted phase as the interference wave of the first input signal. Interference compensation comprising a phase control circuit (3) and a first signal synthesis circuit (4) that synthesizes the output signal of this amplitude phase control circuit and the first input signal and outputs an interference wave compensation signal. In the apparatus, a first modulator (12) modulates the output signal of the signal synthesis circuit with a low frequency signal having a lower frequency than the interference wave, and a signal obtained by shifting the phase of the output signal by 90 degrees. a second modulator (13) that modulates a frequency signal with a signal with a 90° phase shift; a second signal synthesis circuit (16) that synthesizes the modulation outputs of these two modulators (12, 13); a signal receiving circuit (5) which inputs the output of this second signal synthesis circuit and converts it into an intermediate frequency signal; an envelope detector (9) which performs envelope detection of this intermediate frequency signal;
Two product detectors each input the output of the envelope detector and perform product detection using the low frequency signal and a signal obtained by shifting the phase of the low frequency signal by 90', respectively, and output the control voltage as the control voltage. 7, 8).

また、本発明は、上記第一および第二の変調器(12,
13)  は共に振幅変調器であることができる。
The present invention also provides the first and second modulators (12,
13) can both be amplitude modulators.

さらに、本発明は、上記信号受信回路(5)の入力に上
記第二の信号合成回路(16)の出力と上記第二の入力
信号とを合成する第三の信号合成回路(6)が設けられ
ることができる。
Furthermore, in the present invention, a third signal synthesis circuit (6) for synthesizing the output of the second signal synthesis circuit (16) and the second input signal is provided at the input of the signal receiving circuit (5). can be

また、本発明は、上記信号受信回路には自動利得制御手
段を含むことができる。
Further, in the present invention, the signal receiving circuit may include automatic gain control means.

さらに、本発明は、上記第二の入力信号が所定レベル以
下であるとき、上記振幅位相制御回路の出力を無効とす
る手段を備えることができる。
Furthermore, the present invention can include means for invalidating the output of the amplitude and phase control circuit when the second input signal is below a predetermined level.

〔作用〕[Effect]

第一の変調器(12)は第一の信号合成回路(4)の出
力信号を干渉波に比して周波数の低い低周波信号により
変調し、上記第二の変調器(13)は上記出力信号を9
0°位相推移させた信号を上記低周波信号を90°位相
推移させた信号により変調する。
The first modulator (12) modulates the output signal of the first signal synthesis circuit (4) with a low frequency signal whose frequency is lower than that of the interference wave, and the second modulator (13) modulates the output signal of the first signal synthesis circuit (4). Signal 9
A signal whose phase is shifted by 0° is modulated by a signal whose phase is shifted by 90° from the above-mentioned low frequency signal.

第二の信号合成回路(16)は第一および第二の変調器
の変調出力を合成する。その合成出力には低周波信号で
変調された干渉波が出力される。いま、スイッチ(20
)が「オフ」の状態とする。信号受信回路(5)は第二
の合成回路の出力を入力し中間周波信号に変換する。包
絡線検波器(9)はこの中間周波信号を包絡検波する。
A second signal combining circuit (16) combines the modulated outputs of the first and second modulators. The combined output is an interference wave modulated with a low frequency signal. Now, switch (20
) is in the "off" state. The signal receiving circuit (5) receives the output of the second combining circuit and converts it into an intermediate frequency signal. The envelope detector (9) performs envelope detection on this intermediate frequency signal.

乗積検波器(7,8)は包絡線検波器の検波出力の直流
分をそれぞれカットして上記低周波信号および上記低周
波信号を90°位相推移させた信号でそれぞれ乗積検波
し、低域濾波器でこの乗積検波出力の直流成分を取出し
制御電圧として振幅位相制御回路に与える。
The product detectors (7, 8) each cut the DC component of the detection output of the envelope detector and perform product detection using the low frequency signal and a signal obtained by shifting the phase of the low frequency signal by 90°, respectively, and detect the low frequency signal. The DC component of this multiplicative detection output is taken out by the filter and applied to the amplitude and phase control circuit as a control voltage.

また、スイッチ(20)が「オン」の場合を考えると第
三の信号合成回路(6)で第二の信号合成回路(16)
の出力と第二の入力信号とを合成して信号受信回路に与
える。信号受信回路に自動利得制御手段を設けて第二の
入力信号のレベル変動に対して安定な補償動作が得られ
るようにすることができる。
Also, considering the case where the switch (20) is "on", the third signal synthesis circuit (6) is connected to the second signal synthesis circuit (16).
and the second input signal are combined and applied to the signal receiving circuit. Automatic gain control means can be provided in the signal receiving circuit to ensure stable compensation operation against level fluctuations of the second input signal.

さらに、第二の入力信号が所定レベル以下であるときは
、干渉波がなくなっているものとして振幅位相制御回路
の出力信号を無効とする。
Furthermore, when the second input signal is below a predetermined level, it is assumed that there is no interference wave and the output signal of the amplitude phase control circuit is invalidated.

以上により信号受信回路が2系統必要なくなり、かつ構
成が簡易で調整が容易にできる。
As a result of the above, two systems of signal receiving circuits are not required, and the configuration is simple and adjustment can be made easily.

〔実施例〕〔Example〕

本発明の実施例について図面を参照して説明する。第1
図は本発明一実施例干渉補償装置のブロック構成図であ
る。第3図は本発明の干渉補償装置の振幅位相制御回路
のブロック構成図である。
Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of an interference compensation device according to an embodiment of the present invention. FIG. 3 is a block diagram of the amplitude and phase control circuit of the interference compensator of the present invention.

第1図において、干渉補償装置は、希望受信波の他に干
渉波が混入した第一の入力信号を入力する第一の入力端
子として入力端子1と、上記干渉波を主成分とする第二
の入力信号を入力する第二の入力端子として入力端子2
と、入力する制御電圧に基づき上記第二の入力信号を制
御して上記第一の入力信号の干渉波と振幅がほぼ同じで
位相がほぼ反転した信号を出力する振幅位相制御回路3
と、振幅位相制御回路3の出力信号と上記第一の入力信
号とを合成して干渉波補償信号を出力する第一の信号合
成回路として信号合成回路4と、この干渉波補償信号を
出力する干渉波補償出力端子10とを備える。
In FIG. 1, the interference compensator has an input terminal 1 as a first input terminal to which a first input signal mixed with interference waves in addition to the desired received wave is input, and a second input terminal whose main component is the interference wave. Input terminal 2 serves as the second input terminal for inputting the input signal of
and an amplitude phase control circuit 3 which controls the second input signal based on the input control voltage and outputs a signal having substantially the same amplitude and substantially inverted phase as the interference wave of the first input signal.
and a signal synthesis circuit 4 as a first signal synthesis circuit which synthesizes the output signal of the amplitude phase control circuit 3 and the first input signal and outputs an interference wave compensation signal, and outputs this interference wave compensation signal. and an interference wave compensation output terminal 10.

ここで本発明の特徴とするところは、信号合成回路4の
出力信号を上記干渉波に比して周波数の低い低周波信号
により変調する第一の変調器および上記出力信号を90
°位相推移させた信号をこの低周波信号を90°位相推
移させた信号により変調する第二の変調器として変調器
12.13.90°移相器11.15および低周波信号
発振器14と、変調器12.13の変調出力を合成する
第二の信号合成回路として信号合成回路16と、信号合
成回路16の出力を入力とし中間周波信号に変換する信
号受信回路5と、この中間周波信号を包絡線検波する包
絡線検波器9と、包絡線検波器9の出力をそれぞれ高域
濾波器21.22を介して入力し上記低周波信号および
上記低周波信号の位相を90°位相推移させた信号でそ
れぞれ乗積検波し低域濾波器23.24および直流積分
回路25.26を介して上記制御電圧として出力する二
つの乗積検波器7.8とを備えたことにある。また、変
調器12.13はここでは共に振幅変調器である。
Here, the features of the present invention include a first modulator that modulates the output signal of the signal synthesis circuit 4 with a low frequency signal whose frequency is lower than that of the interference wave;
A modulator 12, 13, a 90° phase shifter 11, 15, and a low frequency signal oscillator 14 as a second modulator that modulates a signal whose phase is shifted by 90 degrees with a signal whose phase is shifted by 90 degrees, A signal synthesizing circuit 16 serves as a second signal synthesizing circuit for synthesizing the modulated outputs of the modulators 12 and 13, a signal receiving circuit 5 receives the output of the signal synthesizing circuit 16 as an input and converts it into an intermediate frequency signal, and a signal receiving circuit 5 serves as a second signal synthesizing circuit for synthesizing the modulated outputs of the modulators 12 and 13. An envelope detector 9 detects an envelope, and the outputs of the envelope detector 9 are inputted through high-pass filters 21 and 22, respectively, and the phases of the low-frequency signal and the low-frequency signal are shifted by 90°. Two product detectors 7.8 are provided, each of which performs product detection on the signal and outputs it as the control voltage via a low-pass filter 23, 24 and a DC integration circuit 25, 26. Also, modulators 12, 13 are both amplitude modulators here.

さらに、信号受信回路5の入力に信号合成回路16の出
力と上記第二の入力信号とを合成する第三の信号合成回
路として信号合成回路6が設けられる。
Further, a signal synthesizing circuit 6 is provided at the input of the signal receiving circuit 5 as a third signal synthesizing circuit that synthesizes the output of the signal synthesizing circuit 16 and the second input signal.

また、信号受信回路5には自動利得制御手段を含む。Further, the signal receiving circuit 5 includes automatic gain control means.

さらに、上記第二の入力信号が所定レベル以下であると
き、振幅位相制御回路3の出力を無効とする手段として
包絡線検波器9の出力に接続されたスイッチ18を備え
る。
Further, a switch 18 connected to the output of the envelope detector 9 is provided as means for invalidating the output of the amplitude phase control circuit 3 when the second input signal is below a predetermined level.

第3図は干渉補償装置の振幅位相制御回路のブロック構
成図である。第3図において、31は入力端子、32は
信号分岐回路、33a〜33dは固定移相器、34a 
〜34dはPINダイオード減衰器、35は信号合成器
、36a 、 36bは制御信号入力端子および37は
出力端子である。第3図の構成および動作については特
公昭62−16580号公報に詳細な説明がある。
FIG. 3 is a block diagram of the amplitude and phase control circuit of the interference compensator. In FIG. 3, 31 is an input terminal, 32 is a signal branch circuit, 33a to 33d are fixed phase shifters, and 34a is a signal branch circuit.
34d is a PIN diode attenuator, 35 is a signal combiner, 36a and 36b are control signal input terminals, and 37 is an output terminal. The structure and operation of FIG. 3 are explained in detail in Japanese Patent Publication No. 16580/1983.

このような構成の干渉補償装置の動作について説明する
。第1図において、入力端子2に入力した干渉波は、2
分岐されて振幅位相制御回路3および信号受信回路5に
入力される。この2分岐された信号は複素表示により次
のように表せる。
The operation of the interference compensation device having such a configuration will be explained. In Fig. 1, the interference wave input to input terminal 2 is 2
The signal is branched and input to the amplitude phase control circuit 3 and the signal receiving circuit 5. This two-branched signal can be expressed in complex form as follows.

■A−IA eJ4t iA 二人刃端子2に入力する干渉波する振幅Ω :干
渉波角周波数 振幅位相制御回路3では制御電圧v1、v2に対して、
出力信号を次のように制御し出力する。
■A-IA eJ4t iA Amplitude Ω of the interference wave input to the double-blade terminal 2: In the interference wave angular frequency amplitude phase control circuit 3, for the control voltages v1 and v2,
The output signal is controlled and output as follows.

Iv  =  Kv  (V+  +j V2  ) 
 IA’   Kv  V  I  A   eJ”’
中グ)−に、:振幅位相制御回路の制御感度 Ve’f=v、  +  j  V2 この振幅位相制御回路3の出力信号は、信号合成回路4
で入力端子1からの信号と合成される。
Iv = Kv (V+ +j V2)
IA' Kv V I A eJ"'
-: Control sensitivity of the amplitude phase control circuit Ve'f=v, + j V2 The output signal of this amplitude phase control circuit 3 is sent to the signal synthesis circuit 4.
It is combined with the signal from input terminal 1.

このときに入力端子1からの干渉波信号は次式で表され
、 1、= i、e”′lt″′) 1M二入力端子lに入力する干渉波の振幅α:入力端子
1に入力する干渉波と入力端子2に入力する干渉波との
位相差 合成信号は次式となる。
At this time, the interference wave signal from input terminal 1 is expressed by the following formula, 1, = i, e"'lt"') Amplitude α of interference wave input to 1M2 input terminal l: Input to input terminal 1 The phase difference composite signal of the interference wave and the interference wave input to the input terminal 2 is expressed by the following equation.

It =ix e”””’  −Kv V iA e”
Qt−φ)=: r 6 J (Ωt+θ) ただし、rejθ= iX e”−KvV iA e’
この合成信号を2系統に分岐し、この2分岐された一方
の信号の位相を90°位相推移させると各信号は次のよ
うに表わせる。
It =ix e"""'-Kv V iA e"
Qt-φ)=: r 6 J (Ωt+θ) However, rejθ= iX e”-KvV iA e'
When this composite signal is branched into two systems and the phase of one of the two branched signals is shifted by 90 degrees, each signal can be expressed as follows.

IIl、’ = (1/vT)  r s i n (
Ωt+θ)IR2−(1/J7)  r c o s 
 (Ωt+θ)この各信号に、位相の90°異なる低周
波信号発振器14の出力信号およびこの出力信号を90
”位相器15により位相推移した信号でそれぞれ変調器
12.13で「オン」−「オフ」の振幅変調を行うと次
式のように表わせる。
IIl,' = (1/vT) r sin (
Ωt+θ)IR2-(1/J7) r cos
(Ωt+θ) The output signal of the low frequency signal oscillator 14 with a phase difference of 90° and this output signal are added to each signal by 90°.
``If the signal whose phase has been shifted by the phase shifter 15 is subjected to amplitude modulation from ``on'' to ``off'' by the modulators 12 and 13, it can be expressed as the following equation.

IR+’ = (1/VT)  r S i n (Ω
t+θ)/ (2n−1))cos  (2n−1)ω
t〕 L、  = (1/’−’T)rcos  (Ωt+θ
)/ (2n−1))  s in  (2n−1) 
 Qt)ω:変調信号角周波数 この振幅変調された二つの信号を信号合成回路16で合
成し、さらにこの合成された信号と入力端子2の入力信
号とを信号合成回路6で合成すると次式となる。
IR+' = (1/VT) rS i n (Ω
t+θ)/(2n-1))cos(2n-1)ω
t] L, = (1/'-'T) rcos (Ωt+θ
) / (2n-1)) s in (2n-1)
Qt) ω: Modulation signal angular frequency When these two amplitude-modulated signals are synthesized by the signal synthesis circuit 16, and this synthesized signal and the input signal of the input terminal 2 are synthesized by the signal synthesis circuit 6, the following equation is obtained. Become.

S−(iA/V’T)s i nΩt+ (r/4’−
’2)(sin(Ωt+θ)十cos(Ωt+θ)si
n(Ωt+(2n−1)’CLlt十〇)〕この合合成
器を包絡線検波器9で、たとえば自乗検波すると次式を
得る。
S-(iA/V'T)s i nΩt+ (r/4'-
'2) (sin (Ωt+θ) ten cos(Ωt+θ)si
n(Ωt+(2n-1)'CLlt10)] When this combiner is subjected to, for example, square law detection by the envelope detector 9, the following equation is obtained.

S2= (iA ” /2) s in2Ωを十(iA
r/4)sinΩt[5in(Ωt+θ)+cos (
Ωt+θ)+ (4/π)sin(Ωt+  (2n−
1)  ωt+θ) 〕(r” /32)  [s i
 n (Ωを十θ)+cos  (Ωt+θ)+(4/
π)sin(Ωt+(2n−1)(let+θ)〕2こ
のS2の直流分を低域濾波器で取出し、この直流分出力
が一定となるように自動利得制御(AGC)をかける。
S2= (iA ”/2) s in2Ω as 10(iA
r/4) sinΩt[5in(Ωt+θ)+cos (
Ωt+θ)+ (4/π) sin(Ωt+ (2n-
1) ωt+θ) ](r”/32) [s i
n (Ω to 10θ) + cos (Ωt+θ) + (4/
π) sin(Ωt+(2n-1)(let+θ)]2 The DC component of S2 is extracted by a low-pass filter, and automatic gain control (AGC) is applied so that the output of this DC component is constant.

すなわち低域濾波器で取出した直流電圧は、 1^2/ま ただしiA>r これに基づきAGCによる増幅利得を K / 0フ7 ただし、K=一定 とすると、S2は次式となる。In other words, the DC voltage extracted by the low-pass filter is 1^2/ma However, iA>r Based on this, the amplification gain by AGC is K / 0f7 However, K = constant Then, S2 becomes the following equation.

S2=に2s i nΩt+ (K2r/21A)si
nΩt(sin(Ωを十〇) +cos  (Ωt+θ)+(4/π)sin(Ωt+
  (2n−1)act+θ)〕+  (K2r 2/
16 i A’)〔5in(Ωt+θ) +cos (Ωt+θ)十(4/π) sin(Ωt+ (2n−1)act+θ)〕22本の
直流成分をコンデンサなどの高域濾波器21.22によ
りカットし、変調信号、すなわち低周波信号発振器14
の出力信号およびこの出力信号を90゜移相器15で位
相推移した信号で乗積検波器7.8において乗積検波し
、この検波出力の直流成分を低域濾波器23.24およ
び直流積分回路25.26により得る。すなわち乗積検
波器7.8の出力する制御電圧E1、E2はそれぞれ次
式となる。
S2=2s i nΩt+ (K2r/21A)si
nΩt(sin(Ω=10) +cos (Ωt+θ)+(4/π)sin(Ωt+
(2n-1)act+θ)]+ (K2r 2/
16 i A') [5in (Ωt + θ) + cos (Ωt + θ) 10 (4/π) sin (Ωt + (2n-1) act + θ)] 22 DC components are cut by a high-pass filter 21.22 such as a capacitor. , a modulation signal, i.e. a low frequency signal oscillator 14
A product detector 7.8 performs product detection using the output signal and a signal whose phase is shifted by a 90° phase shifter 15, and the DC component of this detection output is passed through a low-pass filter 23, 24 and a DC integral. Obtained by circuits 25 and 26. That is, the control voltages E1 and E2 output from the product detector 7.8 are expressed by the following equations.

E+ = (K2 r/rr21A)cosθE2 =
 (K2 r/yr2 i、)s i nθただし、i
A>r この二つの出力信号E、、E2を適切な利得Gで増幅し
、上述の制御電圧v1、v2に加算して制御すると、信
号合成回路4の出力信号は次式となり、 i、 = 1)LeJ(flL+g)   KVviA
eJ(Qt、))−Kv  (K2 G/rr2)r 
ej(”θ)”” 1  (kr K2G/ π2) 
) 1 eJIQt−e)制御ループ利得に、に2G/
π2を適切に設定すれば■、は「0」となり、最終的に
干渉波が抑圧され、干渉波補償出力端子10から希望波
のみの信号が得られる。
E+ = (K2 r/rr21A) cosθE2 =
(K2 r/yr2 i,)s i nθ However, i
A>r When these two output signals E, , E2 are amplified with an appropriate gain G and controlled by adding them to the above-mentioned control voltages v1 and v2, the output signal of the signal synthesis circuit 4 becomes the following formula, i, = 1) LeJ(flL+g) KVviA
eJ(Qt, ))−Kv(K2 G/rr2)r
ej("θ)"" 1 (kr K2G/ π2)
) 1 eJIQt-e) control loop gain, 2G/
If π2 is set appropriately, (2) becomes "0", the interference wave is finally suppressed, and a signal containing only the desired wave is obtained from the interference wave compensation output terminal 10.

また、rQJ −rπ」の位相変調を行うとすると、変
調信号は、 得られる。すなわち、As1nQtでSを検波すると、 S’ = iA/2J”;E+ (r/8 J7)[(
cosθ+sinθ)+ (4/π)CO8(2n−1
)Qt および sin  (2n−1)  Qt となり、同様の過程をもって干渉波補償が可能である。
Further, if phase modulation of "rQJ -rπ" is performed, the modulated signal is obtained. That is, when detecting S with As1nQt, S' = iA/2J"; E+ (r/8 J7) [(
cosθ+sinθ)+(4/π)CO8(2n-1
) Qt and sin (2n-1) Qt, and interference wave compensation is possible through a similar process.

「オン」−「オフ」またはr OJ −rπ」変調のよ
うに高調波を含む変調波ではなく正弦波による変調によ
っても干渉波補償が可能である。
Interference wave compensation is also possible by modulation using a sine wave rather than a modulated wave including harmonics such as "on"-"off" or r OJ -rπ" modulation.

また、上述の説明では、包絡線検波器9で自乗検波の場
合について説明したが包絡線を得る方法として、位相同
期回路などにより、入力端子2に入力した干渉波に同期
した信号As1nΩt (A:定数)を得て、これで検
波しても同様の結果がcos  ((2n−1)  ω
t+θ) 〕ただし、高周波成分、すなわち2Ωの周波
数成分を含む項は省略している。この直流分i A/ 
2J”:i(ただし、iA>r)でAGCをかけると、
S’ =に−4−(K、/41A)C(4/π)cos
  ((2n−1)  ωt+θ) 〕この直流分を除
き、変調信号、すなわち低周波信号発振器14の出力信
号およびこの出力信号を90゜移相器15で位相推移し
た信号で乗積検波器7.8において乗積検波し、その直
流分を得る。
Furthermore, in the above explanation, the case of square law detection using the envelope detector 9 was explained, but as a method for obtaining the envelope, a signal As1nΩt (A: Even if we obtain the constant) and detect it using this, the same result will be obtained as cos ((2n-1) ω
t+θ)] However, terms including high frequency components, that is, 2Ω frequency components are omitted. This DC component i A/
2J”: When applying AGC with i (however, iA>r),
S' = to -4-(K,/41A)C(4/π)cos
((2n-1) ωt+θ)] Except for this DC component, the modulation signal, that is, the output signal of the low frequency signal oscillator 14 and a signal obtained by shifting the phase of this output signal by a 90° phase shifter 15, are used in the product detector 7. 8, product detection is performed to obtain the DC component.

(以下本頁余白) El = (K、 /π2iAXl+1/9+1/25
+ l /49+)s i nθ ’=0’、125  (K r/ iA)  s i 
nθE2 = (Kr/π21A)(1+1/9+1/
25+1/49+ )CO5θ #0.125  (K r/ iA)  c o sθ
このように上述の説明と同様に(r/1A)c○Sθお
よび(r/IA)Sinθに比例した電圧が得られ、干
渉波を抑圧できる。
(Hereinafter, this page margin) El = (K, /π2iAXl+1/9+1/25
+ l /49+) s i nθ '=0', 125 (K r/ iA) s i
nθE2 = (Kr/π21A) (1+1/9+1/
25+1/49+) CO5θ #0.125 (K r/ iA) co sθ
In this way, similarly to the above explanation, voltages proportional to (r/1A)c○Sθ and (r/IA)Sinθ can be obtained, and interference waves can be suppressed.

また、AGCは、高周波数帯、中間周波数帯で行う場合
について説明したが、低周波帯または直流信号において
も可能である。たとえば、高周波数帯、中間周波数帯で
AGCをかけてない場合の直流電圧E1は自乗検波のと
き次式となる。
Moreover, although the case where AGC is performed in a high frequency band and an intermediate frequency band has been described, it is also possible in a low frequency band or a DC signal. For example, the DC voltage E1 when AGC is not applied in the high frequency band and the intermediate frequency band is expressed by the following equation when using square law detection.

El −(iA  r/2rr2)cosθこれを自乗
検波出力の直流分iA”/2に基づき2 K/ l A
 ”  (Kは一定)の利得で増幅する。この結果、直
流電圧E1は次のようになり、同様の結果が得られる。
El - (iA r/2rr2) cos θ Based on the DC component iA”/2 of the square law detection output, 2 K/l A
" (K is constant). As a result, the DC voltage E1 becomes as follows, and the same result is obtained.

El = (Kr/π21A)cosθ以上の説明はA
GCを行う場合についてであるが、AGCを行わなくて
も干渉波の補償は可能である。しかし、入力干渉波のレ
ベル変動に対してループ利得が変動するため補償動作が
不安定となる。このためにAGCをかけたほうが安定な
補償動作が得られる。
El = (Kr/π21A)cosθ The above explanation is A
Regarding the case where GC is performed, it is possible to compensate for interference waves without performing AGC. However, since the loop gain fluctuates in response to level fluctuations of the input interference wave, the compensation operation becomes unstable. For this reason, a more stable compensation operation can be obtained by applying AGC.

また、干渉となる信号の送信が停止されるなどの場合に
は干渉補償装置は熱雑音などに対して動作するため希望
波に有害な影響を与える可能性がある。このために、干
渉波が存在するときだけ干渉補償を行うようにしたほう
がよい。すなわち、入力端子2の入力信号の干渉波レベ
ルを検出し、干渉波が検出されないときには入力端子1
の入力信号に入力端子20入力信号が合成されないよう
にする必要がある。具体的にはAGCの制御電圧を監視
し、雑音レベル以上の所定レベルに相当する電圧が検出
されたときに振幅位相制御回路3の出力信号に設けたス
イッチ18を「オン」にするように制御する方法などが
考えられる。
Further, in the case where the transmission of an interfering signal is stopped, the interference compensator operates against thermal noise and the like, which may have a harmful effect on the desired wave. For this reason, it is better to perform interference compensation only when interference waves exist. In other words, the interference wave level of the input signal of input terminal 2 is detected, and when no interference wave is detected, the level of the interference wave of the input signal of input terminal 2 is detected.
It is necessary to prevent the input signal from the input terminal 20 from being combined with the input signal from the input terminal 20. Specifically, the control voltage of the AGC is monitored, and when a voltage corresponding to a predetermined level higher than the noise level is detected, the switch 18 provided for the output signal of the amplitude phase control circuit 3 is controlled to be turned on. There are ways to do this.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、信号受信回路が2系統
必要なく、かつ構成が簡易で調整が容易な優れた効果が
ある。
As explained above, the present invention has excellent effects in that two signal receiving circuits are not required, and the configuration is simple and adjustment is easy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明一実施例干渉補償装置のブロック構成図
。 第2図は従来例の干渉補償装置のブロック構成図。 第3図は干渉補償装置の振幅位相制御回路のブロック構
成図。 1.2・・・入力端子、3・・・振幅位相制御回路、4
.6.16・・・信号合成回路、5.5A、5B・・・
信号受信回路、7.8・・・乗積検波器、9・・・包絡
線検波器、10・・・干渉波補償出力端子、11.15
.17・・・90°移相器、12.13・・・変調器、
14・・・低周波信号発振器、18.20・・・スイッ
チ、21.22・・・高域濾波器(HPF)、23.2
4・・・低域濾波器(LPF)、25.26・・・直流
積分回路、31・・・入力端子、32・・・信号分岐回
路、33a〜33d・・・固定移相器、34a〜34d
・・・PINダイオード減衰器、35・・・信号合成器
、36a 、 36b 用制御信号入力端子、37・・
・出力端子。 特許出願人 日本電信電話株式会社 代理人  弁理士  井 出 直 孝
FIG. 1 is a block diagram of an interference compensation device according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional interference compensation device. FIG. 3 is a block diagram of the amplitude and phase control circuit of the interference compensator. 1.2... Input terminal, 3... Amplitude phase control circuit, 4
.. 6.16...Signal synthesis circuit, 5.5A, 5B...
Signal receiving circuit, 7.8... Multiplier detector, 9... Envelope detector, 10... Interference wave compensation output terminal, 11.15
.. 17... 90° phase shifter, 12.13... Modulator,
14...Low frequency signal oscillator, 18.20...Switch, 21.22...High pass filter (HPF), 23.2
4...Low pass filter (LPF), 25.26...DC integration circuit, 31...Input terminal, 32...Signal branch circuit, 33a-33d...Fixed phase shifter, 34a- 34d
...PIN diode attenuator, 35... Signal combiner, control signal input terminal for 36a, 36b, 37...
・Output terminal. Patent applicant: Nippon Telegraph and Telephone Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

【特許請求の範囲】 1、希望受信波の他に干渉波が混入した第一の入力信号
を入力する第一の入力端子(1)と、上記干渉波を主成
分とする第二の入力信号を入力する第二の入力端子(2
)と、入力する制御電圧に基づき上記第二の入力信号を
制御して上記第一の入力信号の干渉波と振幅がほぼ同じ
で位相がほぼ反転した信号を出力する振幅位相制御回路
(3)と、この振幅位相制御回路の出力信号と上記第一
の入力信号とを合成して干渉波補償信号を出力する第一
の信号合成回路(4)とを備えた 干渉補償装置において、 上記信号合成回路の出力信号を上記干渉波に比して周波
数の低い低周波信号により変調する第一の変調器(12
)および上記出力信号を90゜位相推移させた信号をこ
の低周波信号を90゜位相推移させた信号により変調す
る第二の変調器(13)と、この二つの変調器(12、
13)の変調出力を合成する第二の信号合成回路(16
)と、この第二の信号合成回路の出力を入力とし中間周
波信号に変換する信号受信回路(5)と、この中間周波
信号を包絡線検波する包絡線検波器(9)と、この包絡
線検波器の出力をそれぞれ入力とし上記低周波信号およ
び上記低周波信号の位相を90゜位相推移させた信号で
それぞれ乗積検波して上記制御電圧として出力する二つ
の乗積検波器(7、8)とを備えた ことを特徴とする干渉補償装置。 2、上記第一および第二の変調器(12、13)は共に
振幅変調器である請求項1記載の干渉補償装置。 3、上記信号受信回路(5)の入力に上記第二の信号合
成回路(16)の出力と上記第二の入力信号とを合成す
る第三の信号合成回路(6)が設けられた請求項1記載
の干渉補償装置。 4、上記信号受信回路には自動利得制御手段を含む請求
項3記載の干渉補償装置。 5、上記第二の入力信号が所定レベル以下であるとき、
上記振幅位相制御回路の出力を無効とする手段を備えた
請求項3記載の干渉補償装置。
[Claims] 1. A first input terminal (1) into which a first input signal mixed with an interference wave in addition to the desired received wave is input, and a second input signal whose main component is the interference wave. The second input terminal (2
), and an amplitude phase control circuit (3) that controls the second input signal based on the input control voltage and outputs a signal having substantially the same amplitude and substantially inverted phase as the interference wave of the first input signal. and a first signal combining circuit (4) that combines the output signal of the amplitude phase control circuit and the first input signal to output an interference wave compensation signal, the signal combining circuit comprising: A first modulator (12
) and a second modulator (13) that modulates a signal obtained by shifting the phase of the output signal by 90 degrees with a signal obtained by shifting the phase of this low frequency signal by 90 degrees;
A second signal synthesis circuit (16) synthesizes the modulated outputs of (13)
), a signal receiving circuit (5) which receives the output of this second signal synthesis circuit and converts it into an intermediate frequency signal, an envelope detector (9) which detects the envelope of this intermediate frequency signal, and this envelope detector (9) which detects the envelope of this intermediate frequency signal. Two product detectors (7, 8) each receive the output of the detector and perform product detection using the low frequency signal and a signal obtained by shifting the phase of the low frequency signal by 90 degrees, and output the control voltage as the control voltage. ). 2. The interference compensation device according to claim 1, wherein the first and second modulators (12, 13) are both amplitude modulators. 3. Claim in which a third signal synthesis circuit (6) for synthesizing the output of the second signal synthesis circuit (16) and the second input signal is provided at the input of the signal reception circuit (5). 1. The interference compensation device according to 1. 4. The interference compensation device according to claim 3, wherein the signal receiving circuit includes automatic gain control means. 5. When the second input signal is below a predetermined level,
4. The interference compensator according to claim 3, further comprising means for invalidating the output of said amplitude and phase control circuit.
JP20658790A 1990-08-03 1990-08-03 Interference compensator Expired - Fee Related JP2951703B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20658790A JP2951703B2 (en) 1990-08-03 1990-08-03 Interference compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20658790A JP2951703B2 (en) 1990-08-03 1990-08-03 Interference compensator

Publications (2)

Publication Number Publication Date
JPH0490625A true JPH0490625A (en) 1992-03-24
JP2951703B2 JP2951703B2 (en) 1999-09-20

Family

ID=16525874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20658790A Expired - Fee Related JP2951703B2 (en) 1990-08-03 1990-08-03 Interference compensator

Country Status (1)

Country Link
JP (1) JP2951703B2 (en)

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JP2951703B2 (en) 1999-09-20

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