JPH0490177A - Synchronizing system for digital tape recorder - Google Patents

Abstract

PURPOSE:To attain synchronous operation using a pitch controller even in the case of a digital tape recorder using a voltage control crystal oscillator by simultaneously changing the frequency dividing values(FDVs) of respective variable frequency dividing means of plural digital tape recorders. CONSTITUTION:A FDV control means 6 receiving a signal from a speed setting means 5 in the 1st digital tape recorder 1 sends a signal for setting up a FDV to the 1st variable FD means 3 and the 2nd digital tape recorder 9. The 1st variable FD means whose FDV is set up divides the frequency of a signal outputted from a crystal oscillator and outputs the 1st clock signal. In the 2nd digital tape recorder 9, the 2nd variable FD means 11 whose FDV has been set up divides the frequency of a signal outputted from a voltage control crystal oscillator 10 and outputs the 2nd clock signal. A phase comparing means 13 compares the phases of the 1st and 2nd clock signals and outputs their error to the oscillator 10 as a voltage. Consequently, plural digital tape recorders can always be synchronized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Field of Industrial Application) The present invention relates to a synchronization system for digital tape recorders, and more specifically, to a synchronization system for a plurality of digital tape recorders and a standard for tape running and digital signal processing of a plurality of digital tape recorders. It is possible to synchronize the time axes of the clock signals, that is, to synchronize the clock signals. For example, one device can be a master device and one or more other devices can be slave devices, and the slave devices can synchronize the clock signals of the master device. It concerns a system for synchronizing the

(Prior Art) Conventionally, the method of synchronizing multiple digital tape recorders with each other is to compare the phase of the tarokk signal of the digital tape recorder itself sent from the master machine with the tarokk signal inside the slave machine, and to calculate the error. A known method is to generate a slave machine tarock signal synchronized with the master machine's clock signal through a voltage controlled oscillator and nine frequency divider based on the voltage.

Here, a voltage-controlled crystal oscillator is sometimes used in place of a voltage-controlled oscillator in digital tape recorders due to the large amount of jitter.

Compared to voltage controlled oscillators, this voltage controlled crystal oscillator has
Frequency variable range is narrow. On the other hand, since the pitch controller has a wide variable range, if the tape speed of the master machine is varied by the pitch controller, synchronization with the slave machine will be lost.

In order to solve this problem, conventional methods have been used to transfer variable tape speed data from the master machine's CPU to the slave machine's CPU.
By sending data to the PU and changing the frequency division value of the frequency divider, the master machine and slave machine can be synchronized even when using a voltage controlled crystal oscillator with a narrow variable range for one frequency.

(Problem to be solved by the invention) However, when synchronizing multiple digital tape recorders with each other by sending variable tape speed data from the master machine's CPU to the slave machine's CPU, it is difficult to synchronize the variable data from the master machine's CPTJ to the slave machine's CPU. Machine CP
When sending to U, there will be a delay in the slave machine for the time it takes for the CPU to issue the command. Therefore, there is a problem that the master machine and the slave machine become temporarily out of synchronization.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital cheap recorder synchronization system that can solve the above problems and constantly synchronize a plurality of digital tape recorders.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides a crystal oscillator,
a first variable frequency dividing means for dividing the signal from the crystal oscillator based on a set frequency dividing value to generate a first clock signal and outputting the first clock signal to the outside; and a speed setting means for setting a tape speed. , a first digital tape recorder comprising the first variable frequency dividing means and a frequency dividing value control means for outputting a signal for setting a frequency dividing value based on the signal from the speed setting means to the outside; A voltage controlled crystal oscillator that changes the frequency and outputs a signal; and a second clock signal that divides the signal from the voltage controlled crystal oscillator based on the frequency division value set by the signal that sets the frequency division value. A second variable frequency dividing means that generates a second variable frequency dividing means compares the phases of the first clock signal and an output signal of the second variable frequency dividing means, and outputs the error as a voltage to the voltage controlled crystal oscillator. a second digital tape recorder equipped with a phase comparison means, and controls the output signal of the voltage controlled crystal oscillator based on the comparison result of the phase comparison means to generate a first clock signal and a second clock signal. This is to synchronize the signals.

(Function) First, the frequency division value control means that receives a signal from the speed setting means of the first digital tape recorder, which is the master device, transmits the signal for setting the frequency division value to the first variable frequency division means. and sent to a second digital tape recorder.

As a result, the first variable frequency dividing means to which the frequency dividing value has been set divides the frequency of the signal from the crystal oscillator and outputs the divided signal.

This output signal becomes the first clock signal that controls the operation of the master machine, that is, serves as a reference for tape running and digital signal processing.

On the other hand, in a second digital tape recorder which is a slave machine, a second variable frequency dividing means whose frequency division value is set by a signal output from the frequency division value control means of the master machine,
The signal from the voltage controlled crystal oscillator is frequency-divided and the output signal is sent to phase comparison means.

The phase comparison means compares the phase of the signal output from the first variable frequency division means of the master machine and the signal output from the second variable frequency division means of the slave machine, and converts the error into a voltage. Output to voltage controlled crystal oscillator. Based on this voltage, the voltage controlled crystal oscillator changes its frequency and outputs a signal. The second variable frequency dividing means divides the frequency of this signal and
A second tally clock signal synchronized with the clock signal of the clock signal is generated.

(Example) Examples of the present invention will be described below with reference to the drawings.

The drawing shows the configuration of a synchronization system for a digital tape recorder according to this embodiment.

In the figure, 1 is a first digital tape recorder which is a master machine.

The first digital tape recorder 1 includes a crystal oscillator 2, a first variable frequency division means 3, a speed setting means 5, and a frequency division value control means 6.

Crystal oscillator 2 outputs a signal with a fixed frequency.

The first variable frequency dividing means 3 divides the frequency of the signal from the crystal oscillator 2 based on a set frequency dividing value.

The output signal of the first variable frequency dividing means 3 is a first clock signal and is sent to the first external output terminal 7.

The speed setting means 5 is a pitch controller or a tape speed switching device.

The frequency division value control means 6 sends a signal to the first variable frequency division means 3 and the second external output terminal 8 based on the signal from the speed setting means 5, and sends a signal to the first variable frequency division means 3 and the external output terminal 8. The frequency dividing value of the connected second variable frequency dividing means 11, which will be described later, is set.

A second digital tape recorder 9 is a slave machine, and its operation is controlled by the first digital tape recorder 1.

10 is a voltage controlled crystal oscillator (VCXO), which outputs a signal by changing the frequency based on the input voltage. 11
is a second variable frequency dividing means, and the first external input terminal 14
The signal from the voltage controlled crystal oscillator 10 is frequency-divided based on the frequency division value set by the signal from the voltage-controlled crystal oscillator 10.

The phase comparing means 13 compares the phase of the signal from the second external input terminal 15 and the output from the second variable frequency dividing means 11, converts the error into a voltage, and outputs the voltage to the voltage controlled crystal oscillator 10. . The second variable frequency dividing means 11 generates a second clock signal based on the output of the voltage controlled crystal oscillator 10,
This is sent to the phase comparison means 13.

In addition, a first external output terminal 7 and a second external input terminal 15
, the second external output terminal 8 and the first external input terminal 14 are connected to each other.

Next, the operation will be explained with reference to the drawings.

First, the frequency division value control means 6 that receives the signal from the speed setting means 5 sends a signal for setting the frequency division value to the first variable frequency division means 3 and the second external output terminal 8. . The first variable frequency dividing means 3, to which the frequency dividing value has been set, divides the frequency of the signal from the crystal oscillator 2 and outputs the divided signal. This output signal is the first
This becomes the clock signal.

On the other hand, the second digital tape recorder 9 takes in the signal from the frequency division value control means 6 via the first external input terminal 14 and the second external output terminal 8, 2 variable frequency dividing means 11 is a voltage controlled crystal oscillator 1
The signal from 0 is frequency-divided and the output signal is sent to the phase comparison means 13 as a second clock signal.

The phase comparison means 13 compares the signal outputted from the first variable frequency division means 3 with the signal outputted from the second variable frequency division means 11 via the second external input terminal 15 and the first external output terminal 7. It compares the phase with the second clock signal, and outputs the error as a voltage to the voltage controlled crystal oscillator 10. Based on this voltage, the voltage controlled crystal oscillator 10 changes the frequency and outputs a signal. The second variable frequency dividing means 11 divides the frequency of this signal and outputs it. This output signal becomes the second clock signal. The second clock signal is synchronized with the first clock signal and serves as a clock signal for the second digital tape recorder 9.

As described above, by simultaneously changing the frequency division values of each variable frequency division means of a plurality of digital tape recorders,
This enables synchronized operation using a pitch controller even in digital tape recorders that use voltage-controlled crystal oscillators with a narrow variable range.

[Effects of the Invention] Since the present invention has the above configuration, it provides a synchronization system for digital tape recorders in which the tape speed can be varied by a pitch controller while always maintaining synchronization between a plurality of digital tape recorders. be able to.

[Brief explanation of drawings]

The drawing is a block diagram for explaining the configuration of this embodiment. DESCRIPTION OF SYMBOLS 1... First digital tape recorder, 2... Crystal oscillator, 3... First variable frequency division means, 5... Speed setting means, 6... Frequency division value control means, 9. ... second digital tape recorder, 10... voltage controlled crystal oscillator, 11... second variable frequency dividing means, 13... phase comparison means.

Claims (1)

[Scope of Claims] A crystal oscillator; a first variable frequency dividing means for dividing a signal from the crystal oscillator based on a set frequency dividing value to generate a first clock signal and outputting the first clock signal to the outside; , speed setting means for setting a tape speed; and frequency division value control means for outputting a signal for setting a frequency division value based on the signal from the speed setting means to the first variable frequency division means and the outside. a first digital tape recorder; a voltage-controlled crystal oscillator that outputs a signal by changing the frequency according to a voltage; a second variable frequency dividing means that divides the signal to generate a second clock signal, and compares the phase of the first clock signal and the output signal of the second variable frequency dividing means, and calculates the error. a second digital tape recorder comprising phase comparison means for outputting a voltage to the voltage controlled crystal oscillator, and controlling the output signal of the voltage controlled crystal oscillator based on the comparison result of the phase comparison means; the first clock signal and the second clock signal
A synchronization system for a digital tape recorder, characterized in that it is synchronized with a clock signal of a digital tape recorder.