JPH0488713A - Delay circuit - Google Patents

Abstract

PURPOSE:To avoid the increase in an input terminal for selecting a delay element by using a counter output for a selective signal to select a desired delay element by the selective circuit. CONSTITUTION:A counter circuit 6 is brought into the initial state, that is, the state in which a delay element 3a is selected by inputting a reset signal to a reset terminal 7b. The output of the counter as a selective signal is counted up sequentially by inputting a clock signal to a control signal input terminal 7a. The counter output is inputted to a selective circuit 4 as the selective signal. For example, when the delay time of a delay element 3b is desired to be obtained, the clock is once inputted after resetting. The selection of the required delay element is implemented by two external input terminals, that is, the control signal input terminal 7a and the reset terminal 7b. Thus, increase in the number of input terminals for the delay element selection is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit, and particularly to a delay circuit whose delay time can be arbitrarily adjusted.

[Conventional technology]

Generally, when designing and developing an integrated circuit device, a sufficient margin is provided for the delay time by taking into account the prediction accuracy of the delay time of the integrated circuit at the time of design and the manufacturing variations during manufacturing. In recent years, micromanufacturing technology for integrated circuits has progressed rapidly, and the operating speed of integrated circuits has improved. However, with the adoption of this micromanufacturing technology, manufacturing technology tends to become more complex and manufacturing variations tend to increase. In addition, the difficulty of techniques for predicting the characteristics of microscopic elements is increasing, and prediction errors are also tending to increase.

Due to these factors, the margin required for delay time design has increased, and even though the basic performance of integrated circuits has improved, the problem has arisen that the ability cannot be fully utilized.

In order to solve this problem, a method has been adopted in which a delay circuit whose delay value can be changed after the integrated circuit is prototyped is installed in the integrated circuit device. By adopting this method, the design margin for delay time can be reduced, making it possible to develop high-performance integrated circuits.

Figure 3 shows, for example, a conventional delay circuit in which one of the four types of delay values described in the Proceedings of the 1989 Spring National Conference of the Institute of Electronics, Information and Communication Engineers (P5-249) can be selected. are data input terminals, 2 are data output terminals, and 3a, 3b, and 3c.

3d is a delay element that produces a different delay time; 4 is a selection circuit that selects one of the four delay elements based on a selection signal; 5a and 5b are selection signal lines for providing a selection input to the selection circuit; 8 is an OR circuit which takes the logical sum of the outputs of the four delay elements.

Next, the operation will be explained.

In FIG. 3, a selection circuit 4 selects one of the delay elements 3a, 3b, 3c, and 3d having a desired delay value in response to selection signals from selection signal lines 5a and 5b.

FIG. 4 shows the delay times caused by delay elements 3a, 3b, 3c, and 3d, respectively, t1. t2. t3. A specific example when t4 is shown. Input data from input terminal 1 is low
When the signal rises to High from t
If a delay time of l is required, the delay element 3a is selected. At this time, a Low signal is propagated to the other delay elements 3b, 3c, and 3d. Then, the OR circuit 8 calculates the logical sum of the outputs through these delay elements, and outputs data with a desired delay time from the output terminal 2. Similar operations are performed at t2. t3. This is also performed when a delay time of t4 is required. Here, the selection of the delay element is determined by the value of a 2-bit selection signal, for example, a logic value "1" is applied to the selection signal line 5a.
is performed by applying a logical value '0' to the selection signal line 5b.

In this way, delay elements are selected by a combination of logical values of selection signals.

[Problem H to be solved by the invention] Since the conventional delay circuit is configured as described above, the selection signal line for selecting a delay element is, for example, log, N, when the number of delay elements is N. There were problems such as an increase in the number of delay elements and an increase in the number of input terminals.

The present invention has been made to solve the above-mentioned problems, and aims to provide a delay circuit that can avoid an increase in the number of input terminals for selecting the elements due to an increase in the number of delay elements. There is.

(Means for Solving the Problems) A delay circuit according to the present invention includes a selection means for selecting a desired delay element based on a selection signal from among a plurality of delay elements each having a different delay value, and a control A counter circuit is provided for counting clock signals from a signal input terminal and outputting a counter output, and the cough counter output is inputted to the selection means as the selection signal.

[Effect]

In the present invention, a counter circuit is provided that counts clock signals from a control signal input terminal and outputs a counter output, and the counter output is used as a selection signal for selecting a desired delay element in a selection circuit. Therefore, the required delay elements can be selected using the signal input terminals to the counter circuit, and it is possible to avoid an increase in the number of input terminals for selecting delay elements due to an increase in the number of delay elements.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a delay circuit according to an embodiment of the present invention, in which 1 is a data input terminal, 2 is a data output terminal,
3a, 3b, 3c, and 3d are delay elements each having a different delay value; 4 is a selection circuit that selects one of the four delay circuits based on selection signals from selection signal lines 5a and 5b; 6; is a counter circuit having a control input signal terminal 7a and a reset terminal 7b, which counts the clock signal from the control input signal terminal 7a and uses the counter output as the selection signal on the selection signal line 5a.

5b, and the output is reset by a reset signal from the reset terminal 7b. Reference numeral 8 denotes an OR circuit for calculating the logical sum of the respective delay elements 3a to 3d.

Also, Figure 2 shows the number of clocks input after resetting,
An example of the relationship with selected delay elements is shown.

Next, the operation will be explained.

By inputting a reset signal to the reset terminal 7b, the counter circuit 6 is brought into an initial state, that is, a state in which the delay element 3a is selected.0 By inputting a clock signal from the control signal input terminal 7a, a selection signal is set. The output of the counter is sequentially counted and amplified. This counter output is input to the selection circuit 4 and functions as a selection signal 6. For example, if you want to obtain the delay time by the delay element 3b, input the clock once after resetting. The desired delay time can be created as well as in the prior art.

As described above, in this embodiment, the counter circuit 6 that counts the clock signal from the control signal input terminal 7a and outputs a counter output is provided, and the selection circuit 4 uses the counter circuit 6 as a selection signal for selecting a desired delay element. Since the output is used, the required delay element can be selected using two external input terminals.

That is, this can be done using the control signal input terminal 7a and the reset terminal 7b. As a result, the input terminals for the signals necessary for selecting delay elements can be fixed to the two signal input terminals 7a and 7b to the counter circuit.In other words, no matter how many delay elements increase, the selection can be made The input terminals required for this purpose are only the above two terminals, and an increase in the number of input terminals for selecting delay elements can be avoided.

In the above embodiment, the case where four delay elements are used is described, but the number of delay elements is not limited to this, and may be larger. Also, the number of clocks input to the counter and the amount of delay For example, by inputting the clock once, the delay amount of 1 can be
It is also possible to realize a delay circuit having a correspondence relationship such that a delay amount of two can be obtained by inputting a clock twice.

〔Effect of the invention〕

As described above, according to the delay circuit according to the present invention, a counter circuit that counts clock signals from a control signal input terminal and outputs a counter output is provided, and selection for selecting a desired delay element in the iA circuit is provided. Since the above counter output is used as a signal, the required delay element can be selected using the signal input terminal to the counter circuit, and as the number of delay elements increases, the input for selecting the delay element can be This has the effect of avoiding an increase in the number of terminals.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a delay circuit according to an embodiment of the present invention;
FIG. 2 is a diagram showing an example of the operation of the delay circuit in FIG. 1,
FIG. 3 shows a conventional delay circuit, and FIG. 4 shows the operation of the delay circuit. 1 is input terminal, 2 is output terminal, 3a, 3b, 3c, 3d
is a delay element, 4 is a selection circuit, 5a and 5b are selection signal lines,
6 is a counter circuit, 7a is a control signal input terminal, 7b is a reset terminal, and 8 is an OR circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 2

Claims (1)

[Claims] (1) A plurality of delay elements connected in parallel between a data input terminal and a data output terminal, each having a different delay value, and a selection means for selecting one of the delay elements according to a selection signal. A delay circuit configured to output data input from a data input terminal from a data output terminal after a lapse of time corresponding to a delay value of a selected delay element, the delay circuit having a control signal input terminal, and outputting data input from the data input terminal from the data output terminal after a lapse of time corresponding to the delay value of the selected delay element. 1. A delay circuit comprising: a counter circuit that counts and outputs a counter output; and the counter output is input to the selection means as the selection signal.