JPH0486123A - D-a converter - Google Patents

Abstract

PURPOSE:To prevent a spike voltage from being produced in an output voltage by providing m-sets of analog voltage generating circuits and using a switch section so as to output an analog output voltage switchingly. CONSTITUTION:Analog voltage generating circuits 3a, 3b and m-sets of latch circuits 2a, 2b are connected to an input terminal 1 and a control circuit 5 selects a switch section 4 to output an output of the analog voltage generating circuits 3a, 3b to an output terminal 6 sequentially. Moreover, an n-bit digital signal is inputted to the input terminal 1, where n, m are respectively an integral number being 2 or over. The latch circuits 2a, 2b are connected to the input terminal 1 and the control circuit 5 controls the latch circuits 2a, 2b so as to latch a digital input signal of the input terminal 1 alternately. Moreover, the output of the analog voltage generating circuits 3a, 3b is once short-circuited and operated switchingly. Thus, production of a spike voltage in an output voltage is prevented at switching of the input digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D-A converter in which the generation of spike voltages is avoided.

[Prior Art] As shown in FIG. 5, a conventional D-A converter has an input terminal 1 which is an input terminal for an n-bit signal, and an input terminal 1 which is an input terminal for an n-bit signal.
, an analog voltage generating circuit 3 connected to the latch circuit, and an output terminal 4 connected to the analog voltage generating circuit 3.

In this D-A converter, when a digital signal is applied to input terminal 1, latch circuit 2 latches this digital signal and transmits it to analog voltage generation circuit 3, and analog voltage generation circuit 3 outputs an analog output voltage. Output to terminal 4.

[Problems to be Solved by the Invention] However, in the conventional D-A converter described above, the lengths of the signal lines for each bit from the latch circuit 2 to the analog voltage generation circuit 3 may be different from each other. If the signal lines for each bit are different in this way, a difference will occur in delay time. Therefore, as shown in FIG. 6(a), when the input digital signal is switched, the signal in FIG.
), there is a problem in that a spike voltage occurs in the output analog voltage.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a D-A comparator that does not generate spike voltages in output analog voltages.

[Means for Solving the Problems] A D-A converter according to the present invention includes an input terminal into which an n (n; an integer of 2 or more) bits of digital signal is input;
m (m; an integer greater than or equal to 2) connected to each input terminal
m analog voltage generating circuits each connected to the latch circuits and generating analog voltages in proportion to the magnitude of the latched signal; The device is characterized in that it includes a switch section that switches and outputs to an output terminal, and a control circuit that controls the latch operation of the latch circuit and the switching operation of the switch section.

[Operation] In the present invention, m sets of latch circuits and analog voltage generation circuits are connected to input terminals, and a control circuit switches the switch sections to sequentially output the outputs of the analog voltage generation circuits to the output terminals. In this case, the control circuit can perform the switching operation by once shorting the outputs of the two analog voltage generation circuits to be switched, so that it is possible to prevent a spike voltage from occurring in the output voltage when switching the input digital signals. .

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a D-A converter according to a first embodiment of the present invention. The input terminal 1 has n input terminals corresponding to n-bit digital signals. Both of the two latch circuits 2 a + 2 b are connected to this input terminal 1 . Furthermore, the control circuit 5 is connected to the latch circuit 2.
A and 2b are controlled so that they alternately latch the digital input signal of input terminal 1. Analog voltage generation circuits 3a and 3b are connected to the latch circuits 2a and 2b, respectively.
Analog voltage generation circuits 3a and 3b are each latch circuit 2a.
, 2b, and generates an analog voltage proportional to the magnitude of the digital input signal. The switch section 4 switches the analog voltage under the control of the control circuit 5 and outputs it to the output terminal 6.

Next, we will discuss the operation of the D-A converter of this example in the first section.
The explanation will be made with reference to the timing chart of FIG. 2 in addition to the drawings.

As shown in FIGS. 2(a) and (b), at time t,
It is assumed that the switch section 4 outputs to the output terminal 6 an analog voltage obtained by converting the digital input signal latched by one of the latch circuits 2a by the analog voltage generating circuit 3a.

Next, when the input digital signal changes at time t+1, the control circuit 5 sends a latch signal to the other latch circuit 2b, causing this latch circuit 2b to latch the input digital signal. After this latch, this other latch circuit 2b
The analog voltage generation circuit 3b connected to
), it operates to approach the analog voltage value corresponding to the input digital signal and settles down to the final value. Subsequently, as shown in FIG. 2(e), the control circuit 5 connects the one analog voltage generating circuit 3a and the output terminal 6 to the other analog voltage generating circuit 3b with respect to the switch unit 4.
and output terminal 6. At this time, the switch unit 4 connects the output of one analog voltage generation circuit 3a to the output terminal 6, connects the output of the other analog voltage generation circuit 3b to the output terminal 6, and then generates both analog voltages. After short-circuiting the outputs of circuits 3a and 3b, the output of one analog voltage generating circuit 3a is disconnected.

By repeating the above operations, it is possible to obtain an output voltage in which no spike voltage occurs, as shown in FIG. 2(f).

FIG. 3 is a block diagram showing a D-A converter according to a second embodiment of the present invention. In this embodiment, the number of latch circuits 2c and analog voltage generation circuits 3c is increased by one set compared to the first embodiment.

The added latch circuit 2c latches the output signal of the control circuit 5, and outputs the output signal of the control circuit 5 to the analog voltage generation circuit 3c.

Next, the operation of the D-A converter according to this embodiment will be explained with reference to timing charts shown in FIGS. 3 and 6.

In this embodiment, the control circuit 5 controls the first latch circuit 2a and the second latch circuit 2b to alternately latch the input signal, as in the first embodiment, and
The control circuit 5 receives the input digital signal at time t and the input digital signal at time t+1.
The intermediate value of the input digital signal is controlled to be latched by the newly added third latch circuit 2C. After the analog voltage value has settled down to the final value, the control circuit 5 converts the analog voltage of the first analog voltage generating circuit 3a to the second analog voltage.
When switching to the analog voltage of the third analog voltage generation circuit 3b, the switch section 4 is controlled so that the analog voltage value of the third analog voltage generation circuit 3c is passed through one end. By repeating the above operation, the change in the signal at the time of switching becomes even smoother, and it is possible to avoid the occurrence of spike voltage.

Each of the above embodiments is equipped with two sets of latch circuits and analog voltage generation circuits, but if the number of latch circuits and analog voltage generation circuits is three or more each, the change in signal at the time of switching will be further reduced. It becomes even smoother.

[Effects of the Invention] As explained above, the present invention has m (m≧2) analog voltage generation circuits, and the analog output voltage is switched and outputted by the switch section, so there is no spike voltage in the output voltage. This has the effect of preventing the occurrence of Furthermore, by controlling the output voltage transition when switching the analog output voltage, the output voltage transition can be arbitrarily changed to a desired value.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a D-A converter according to a first embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a D-A converter according to a second embodiment of the present invention. FIG. 4 is a block diagram showing a conventional D-A converter, FIG. 4 is a timing chart thereof, FIG. 5 is a block diagram showing a conventional D-A converter, and FIG. 6 is a timing chart thereof. 1; Input terminal, 2+ 2ay 2b, 2c; Latch circuit, 3.3a+ 3b+ 3c; Analog voltage generation circuit, 4; Switch section, 5; Control circuit, 6; Output terminal

Claims (1)

[Claims] (1) An input terminal into which an n (n; an integer of 2 or more) bits of digital signal is input, m (m; an integer of 2 or more) latch circuits each connected to this input terminal, and this latch circuit. m analog voltage generation circuits that are connected to the latched signals and generate analog voltages in proportion to the magnitude of the latched signals, and a switch section that switches the analog voltages output from each of the analog voltage generation circuits and outputs them to the output terminals. and a control circuit that controls the latch operation of the latch circuit and the switching operation of the switch section.