JPH0486017A - Pseudo random signal generator - Google Patents

Abstract

PURPOSE:To easily restart operations even when a shift register is reset by obtaining a shift-in input through an EX-NOR gate to invert the output of an exclusive OR gate (EX-OR gate). CONSTITUTION:While inputting the reset signals, flip-flops (1-1)-(1-5) are forcedly set in a reset state. In this case, the Q output of a flip-flop 4 is defined as an input to an EXNOR gate 3 and according to the state of the Q output, however, the EX-NOR gate 3 is operated as an AND gate 5 or an inverter. While the flip-flop 4 is set in the reset state, the EX-NOR gate 3 is operated as the inverter and as the result, the output of an EX-OR gate 2 in an 'L' state is inverted by the EX-NOR gate 3 and inputted to the flip-flop 1-1 as a data input in an 'H' state. Thus, operations are restarted.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention specifically relates to an M-sequence pseudo-random signal generator, and in particular, even if a shift register as a component is reset, the pseudo-random signal generator The present invention relates to a pseudo-random signal generator whose operation can be easily restarted, and further to a pseudo-random signal generator which is configured so that a synchronization signal can be easily obtained.

[Prior art] The configuration of a pseudorandom signal generator to date is as follows.
Practical Electronic Circuit Handbook (4) J (November 1982)
Published on January 1st, Publisher: CQ Publishing Co., Ltd. Pages 255-2
59), it basically consists of a shift register and an exclusive OR gate (exclusive OR gate 2 or below, simply referred to as EX-OR gate). .

[Problem to be solved by the invention] However, in conventional pseudo-random signal generators, once the shift register, which is a component, is reset for the purpose of synchronizing during operation,
The operation as a pseudo random signal generator cannot be restarted.

This means that the specific parallel output in the shift register is
Although they are exclusive-ORed by the X-OR gate, when the shift register is reset, these specific parallel outputs are in the same bit state, so the EX
This is because the signal fed back from the -OR gate to the input side of the shift register also maintains the same bit state as the specific parallel output, so even if the operation is attempted, it cannot be restarted.

In addition to the above-mentioned problems, in conventional pseudo-random signal generators, when the number of flip-flops making up the shift register, that is, the number of stages, is n, the repetition period is generally assumed to be 2'-1. It has become sought after. Therefore, when measuring the output waveform with an oscilloscope or the like, it is difficult to obtain a synchronization signal or a trigger signal because the repetition period in pseudo-random signal generation is long.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pseudo-random signal generator whose operation can be easily restarted even when a shift register is reset.

Another object of the present invention is to provide a pseudorandom signal generator from which a synchronization signal or trigger signal required for measuring an output waveform can be easily obtained.

[Means for Solving the Problems] The above object is to configure an M-sequence pseudo-random signal generator including a shift register and an EX-OR gate, and to provide a reset signal to the shift register at the input side of the shift register. A flip-flop that is reset and placed in the set state by a shift clock to the shift register, and while the flip-flop is in the set state, the EX-OR gate output is passed through as is,
This is accomplished by providing an EX-NOR gate that inverts the EX-OR gate output while in the reset state.

Another object is achieved by detecting, using an appropriate gate, that the flip-flops constituting the shift register have a specific bit pattern as a whole.

[Operation] In a general M-sequence pseudorandom signal generator, EX
The -OR gate output is input as is to the shift register as a shift-in input, but the EX-OR gate output is connected to a newly installed flip-flop and an EX-N
It is intended to be controlled by an OR gate. That is, although the flip-flop is reset at the same time as the shift register is reset, it is immediately set to the set state by the first shift clock thereafter. Therefore, the output of this flip-flop is E
It is sufficient to control the output of the X-OR gate. More specifically, the EX-OR gate output cannot be obtained immediately as a shift-in input, but can be obtained as a shift-in input via the EX-NOR gate. When the flip-flop is reset, the EX-OR gate output is inverted by the EX-NOR gate and shifted into the shift register, so the shift register is released from its reset state immediately after being reset. The operation as an M-sequence pseudo-random signal generator can be restarted.

On the other hand, as soon as the inverted EX-OR gate output is shifted into the shift register, the flip-flop is subsequently placed in the set state, or while it is in the sent state,
Since the EX-OR gate output is directly shifted into the shift register via the EX-NOR gate, the normal circuit operating state can be restored.

Also, while operating as a pseudo-random signal generator, each of the plurality of flip-flops making up the shift register is placed in various states, or a specific bit pattern consisting of these states appears only once within a repetition period. Therefore, if this is detected using a gate, the detection output can be obtained as a synchronization signal or a trigger signal.

[Example] Hereinafter, the present invention will be explained with reference to the accompanying drawings.

The figure shows a specific configuration of an M-sequence pseudo-random signal generator according to an example of the present invention. As shown in the figure, the shift register 1 that performs a shift operation based on a shift clock is composed of five falling edge trigger D-type flip-flops 1-1 to 1-5 in this example, and is used to perform a normal M-series To configure a pseudorandom signal generator, the Q output of each of flip-flops 1-3.1-5 is EX
- It is only necessary to carry out an exclusive OR with the OR gate 2 and then input it to the flip-flop 1-1 as a data input. In this way, the desired M-sequence pseudo-random signal can be obtained as an output from the flip-flops 1-5.

Now, the EXNOR gate 3 and the falling edge trigger D-type flip-flop 4, which are components other than the above-mentioned components,
The AND gate 5 is newly added according to the present invention, and among these, the EX-NOR gate 3 and the falling edge trigger D-type flip-flop 4 are used for restarting operation after reset, and are also used as an AND gate. Reference numeral 5 is provided to obtain a synchronization signal or a trigger signal. First, restarting the operation after reset will be explained as follows.

That is, if a reset signal is input for some purpose while the shift register 1 is performing a shift operation based on the shift clock, the reset signal is input to the flip-flops 1-1 to 1-5.4. During this time, the device is forced to be in a reset state. In this case, the Q output of the flip-flop 4 is input to the EX-NOR gate 3, but depending on the state of the Q output, the EX-N.

The R gate 3 functions as an AND gate or an inverter. While the flip-flop 4 is in the reset state, the EX-NOR gate 2 and NOR gate 3 function as an inverter, so that the output of the EX-OR gate 2, which is in the "L" state, is inverted by the EX, -N OR gate 3. Above, flip-flop 1-1'
It is input as data input in the "H" state. In this state, if the input of the reset signal is eventually released, the "H" state is shifted into the flip-flop 1-1 at the falling edge of the first shift clock after that, and at the same time, the flip-flop 4 is shifted into the "H" state. As a result, the operation as an M-sequence pseudo-random signal generator is resumed.

If flip-flop 4 is set, E
X-NOR gate 3 functions as an AND gate, and at the same time, EX-OR gate 2 output remains as EX
- It is designed to be taken into the flip-flop 1-1 via the NOR gate 3.

Next, to explain the configuration for obtaining a synchronization signal or a trigger signal, while generating a pseudo-random signal, the states of each of the flip-flops 1-1 to 1-5 that make up the shift register 1 vary depending on the frequency of the shift register 1. Since a specific bit pattern as a whole that is changing or consists of these states appears only once at a specific point in the repetition period, the appearance of that specific bit pattern can be detected by various gates or decoders. It becomes. In this example, as shown in the figure, flip-flops 1-
A five-man powered AND gate 5 is used to detect the case where the Q output states of 1 to 1-5 are all "H" at the same time, but the invention is not limited to this, and the five-man powered Noah gate or Nantes It is also possible to use a gate, or even a combination of various types of gates. In any case, if the appearance of a specific bit pattern is detected within the repetition period, the detection output can be used as a synchronization signal or a trigger signal.

Since the pseudorandom signal generator according to the present invention is configured as described above, the configuration can be easily obtained as an IC. In addition, in the above explanation, the reset signal is used only as a reset signal, but when using it as an initial setting signal, it is possible to eliminate the need for additional flip-flops or gates, and use the flip-flops that constitute the shift register. By performing reset/preset control on each of them in a predetermined manner, it is possible to restart the operation after initial setting.

[Effects of the Invention] As described above, according to claim 1, even if the shift register is reset, the operation can be easily restarted, and according to claim 2, when measuring the output waveform, The synchronization signal or trigger signal required for this purpose can be easily obtained.

[Brief explanation of drawings]

The figure is a diagram showing a specific configuration of an M-sequence pseudo-random signal generator as an example according to the present invention. 1...Shift register, 1-1 to 1-5.4...(
Falling edge trigger D type) flip-flop, 2...
EX-OR gate, 3...EX-NOR gate, 5.
・and gate

Claims (1)

[Scope of Claims] 1. An M-sequence pseudo-random signal generator configured to include a shift register and an exclusive OR gate, the input side of the shift register being reset by a reset signal to the shift register; A flip-flop that is set to a set state by a shift clock to a register, and an exclusive NOR gate that allows an exclusive OR gate output to pass through as is while the flip-flop is in a set state, and inverts the exclusive OR gate output while it is in a reset state. A pseudo-random signal generator having a configuration in which the gate output is a shift-in input to a shift register. 2. The pseudo-random signal generator according to claim 1, further comprising a gate for detecting that the flip-flops constituting the shift register have a specific bit pattern as a whole.