JPH0485939A - Field effect semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of the crystals caused by lattice mismatching by inserting a lattice distortion absorbing layer between an n-type InAlAs electron supply layer and a GaAs leak current control layer. CONSTITUTION:By MBE method, a buffer layer 22 is grown on a substrate 21. Subsequently, an active layer 23 and a spacer layer 24 are grown, and an electron supply layer 25 doped with Si is grown. Subsequently, with an InAlAs layer and a GaAs layer as one unit, ten cycle stacking is carried out to form a superlattice structure, and it is made a lattice distortion absorbing layer 26. Subsequently, a leak current control layer 27 doped with Si is grown. Next, a source electrode 28 consisting of AuGe/Au and a gate electrode 30 consisting of Al are formed. Hereby, a Schottky gate electrode is formed at the GaAs leak current control layer, so the leak current from the gate is small, and the voltage applied to the semiconductor device can be elevated enough and the logical amplitude in a logical circuit can be taken large.

Description

[Detailed Description of the Invention] [Summary] ■ Regarding the improvement of a field effect semiconductor device using a -V group gold compound semiconductor material, a field effect semiconductor device having an InAlAs/InGaAs-based heterojunction structure has a large leakage current suppressing effect. GaAs
The aim is to avoid problems caused by lattice mismatch even when using a plurality of I nAj2As/I n
GaAs-based epitaxially grown compound semiconductor layer and the 1nAf! InAlAs/InGaAs formed on the surface of the As/InGaAs epitaxially grown compound semiconductor layer.
a lattice strain buffer layer having a multilayer thin film stacked structure made of GaAs, a GaAs leakage current suppression layer formed on the surface of the lattice strain buffer layer, a source electrode and a drain electrode conductively connected to the active layer, and the leakage current suppression layer. and a gate electrode formed on the layer.

[Industrial application field]

TECHNICAL FIELD The present invention relates to an improvement in a field effect semiconductor device using a metal compound semiconductor material belonging to the ■-■ group.

At present and in the future, increasing the speed of computer systems is a top priority in the field of electronic technology, and achieving this goal requires increasing the speed of field-effect semiconductor devices.

High-electron mobility transistors are high-speed field-effect semiconductor devices.
Many types have been developed, including ty transistor (HEMT), and each is gaining success.
There is still much room for improvement.

(Prior art) In general, HEMTs supply carriers from an electron supply layer to an active layer that has increased electron mobility by making it highly purified to generate a two-dimensional carrier gas layer, which is used as a channel at high speed. It is designed to allow carriers to move, and was initially realized using an AlGaAs/GaAs heterostructure.

In such a HEMT, AβGaAs doped with silicon (Si) is used for the electron supply layer, but it usually contains a DX center, which often poses a problem particularly during low-temperature operation. In other words, the DX center is
This causes a phenomenon called collapse (temporal fluctuation) in which the drain current decreases during HEMT operation, which hinders stable operation.

In order to solve the above-mentioned problems in the ARG a As / Ga As type HEMT, I no, szA lo, asA S / I are formed on a semi-insulating InP substrate.
no, szGa 0.47A In the case of a HEMT formed with an S-based heterostructure, a DX center is not included, and it is suitable for low-temperature operation, and I no, which becomes an active layer,
s3Gao, 47A S is superior in high speed compared to GaAs. Therefore, at present, T n
o, szA Ao, asA S/I na, 5zG
a,...7As-based HEMTs are attracting attention as ultra-high speed semiconductor devices. In addition, in this specification, simply I n
AI! , As, or InGaAs, Ino, 5zAffi, 1 is lattice matched to the InP substrate.
．． aAs, or I n O, S:IG a o,
It refers to a7A S.

Figure 3 is InAj! 1 is a cross-sectional side view of essential parts for explaining a conventional example of an As/1nGaAs HEMT.

In the figure, 1 is a semi-insulating 1nP substrate, 2 is a non-doped InGaAs active layer, and 3 is a non-doped InGaAs active layer.
! As spacer layer 4 is Si-doped n-type 1n
AρAs electron supply layers 1 and 5 are non-doped T nAlA
s leakage current suppression layer, 6 is an InGaAs ohmic electrode contact layer, 7 is a source electrode, 8 is a drain electrode, 9
indicate Schottky gate electrodes, respectively.

In the illustrated conventional example, non-doped InAfAs
The reason for inserting the leakage current suppression layer 5 is that the n-type In, Aj!
This is to reduce leakage current since forming the Schottky gate electrode 9 directly on the As electron supply layer 4 increases leakage current.

However, even if the non-doped InAρAs leakage current suppression layer 5 as described above is provided, leakage current still occurs. Therefore, C;a doped with Si in this leakage current suppression layer.
The use of As is being considered (if necessary, W, P
, Hong, P., Bhattacharyal EEE.
Electron Device Letter
s 9 (1988) pp 352-354). The structure of this HEMT is similar to that of the HEMT described with reference to FIG. 3, except that the material of the leakage current suppressing layer 5 is replaced with Si-doped GaAs, and other features are almost the same.

[Problem to be solved by the invention] InAlAs/InGaAs explained with reference to FIG.
In the HEMT system, non-doped 1nlj! Despite the provision of the As leakage current suppression layer 5, A I Ga
The leakage current is large compared to As/GaAs type HEMTs, so the applied voltage must be limited, and when a logic circuit is configured, problems such as the inability to obtain a large logic amplitude occur. .

Furthermore, when GaAs is used as the leakage current suppression layer, the lattice mismatch with the underlying InAfAs electron supply layer is approximately 3.7.
(%) is very large. Therefore, when forming a GaAs leakage current suppression layer on an InAfAs electron supply layer, many layers are formed in the layer and at the interface due to lattice mismatch strain before the layer grows to a thickness sufficient to suppress leakage current. dislocation occurs. Even if a HEMT is completed by forming a gate electrode on a layer in which such dislocations have occurred, the stability and reliability of the HEMT will be significantly impaired due to destruction of the crystal due to lattice mismatch.

As described above, the HEMT provided with the leakage current suppression layer made of InAj2As or GaAs has various drawbacks.

The present invention prevents problems caused by lattice mismatch even when GaAs, which has a large leakage current suppression effect, is used in a field effect semiconductor device having an InAj2As/InGaAs-based heterojunction structure.

[Means to solve the problem]

Experiments regarding Schottky gate electrodes conducted by the present inventor will be described.

That is, molecular beam epitaxy is performed on a semi-insulating TnP substrate.
By applying the F:MBE) method, an InAf!As layer containing about I x 1018 (cm-':l) of Si as a dopant is grown, and then a non-doped InAfAs layer is grown on it. When a Schottky electrode made of An was formed on it, the Schottky barrier height was about 0.6 (e
V). Moreover, the same <
By applying the MBE method, GaAs1i containing about 1×10"(c") of Si as a dopant was grown, and a Schottky electrode made of An was formed on it, and the Schottky barrier height was Approximately 0.8 [e
■]

Here, the Schottky barrier height was measured by the differential capacitance-voltage method at room temperature. That is, an electrode pattern of 200 (μm) φ was formed on an approximately 5 [1] (2 [inch]) wafer on which the required layers had been grown by the MBE method as described above, and then vacuum evaporation of An2 was performed. A Schottky electrode is formed by lifting it off, and its 200 [μm]φ
A reverse bias voltage was applied to the Schottky electrode, and a forward bias voltage was applied to the other parts, and the capacitance C was measured when the applied voltage (2) was varied. Thereafter, the Schottky barrier height was obtained from the voltage value at which the 1/C2 vs. ■ curve cuts the voltage axis.

As described above, the Schottky barrier height of the Schottky electrode formed on the GaAs layer is about 0.2 (eV) higher than that of the Schottky electrode formed on the InAfAs layer. Since the Schottky forward current in the Schottky junction decreases exponentially with the Schottky barrier height, the above 0
．． The difference in Schottky barrier height of 2 (eV) is large. Therefore, it is clear that it is preferable to use GaAs as the leakage current suppressing layer, but to do so, the problem of lattice mismatch must be solved.

FIG. 1 is a cross-sectional side view of a main part of a field effect semiconductor device for explaining the present invention in detail.

In the figure, 11 is a semi-insulating InP substrate, 12 is a non-doped InAj2As buffer layer, 13 is a non-doped InGaAs active layer, and 14 is a non-doped InGaAs buffer layer.
nAfAs spacer layer, 15 an n-type nAfAs electron supply layer doped with impurities such as Si, 16 a lattice strain buffer layer, 17 a GaAs leakage current suppression layer, 18 a source electrode, 19 a drain electrode, and 20 a Schottky electrode. Each gate electrode is shown.

As can be understood from the illustrated field effect semiconductor device, in the present invention, the n-type 1nAfAs electron supply layer 15 and the GaAs
A major feature is that a lattice strain buffer layer 16 is interposed between the leakage current suppressing layer 17, and this lattice strain buffer layer 16 is composed of a thin non-doped In, 61AS layer and a non-doped GaAs layer. It has a superlattice structure in which many of these are alternately stacked.

From the above, in the field effect semiconductor device according to the present invention, (1) an active N layer is formed on a semi-insulating 1nP substrate (for example, semi-insulating 1nP substrate 11) to generate a channel;
(e.g. non-doped InGaAs active layer 13)
based epitaxially grown compound semiconductor layer, and the 1 nAl
A lattice strain buffer layer (for example, a lattice strain buffer layer having a superlattice structure N16) having a multi-N thin film stacked structure made of InA1As/GaAs formed on the surface of an As/InGaAs-based epitaxially grown compound semiconductor layer, and a lattice strain buffer layer having a superlattice structure formed on the surface of the lattice strain buffer layer. GaAs leakage current suppression layer (for example, G
an aAs leakage current suppression layer 17), a source electrode and a drain electrode (for example, a source electrode 18 and a drain electrode 19) conductively connected to the active layer, and a gate electrode (for example, a gate electrode) formed on the leakage current suppression layer. 20) or (2) in (1) above, a plurality of rnA/! As/I
The nGaAs epitaxially grown compound semiconductor layer contains I.
It is made of nGaAs and has two-dimensional carriers near the surface.
An active layer in which a gas layer is generated (e.g. non-doped I n
It is characterized in that it includes a GaAs active layer 13) and a carrier supply layer (eg, n-type InAfAs electron supply layer 15) made of InAfAs and supplying carriers to the active layer.

[Function] By adopting the above method, the Schottky gate electrode is formed on the GaAs leakage current suppression layer, so the Schottky barrier height is higher than when it is formed on the InAffiAs leakage current suppression layer. The leakage current from the gate is small, so the voltage applied to the semiconductor device can be made sufficiently high, for example, the logic amplitude in the logic circuit can be increased, and the degree of freedom in circuit design is expanded.

Furthermore, even if such a leakage current suppression layer made of GaAs is provided, since a lattice strain buffer layer with a multilayer thin film periodic structure is interposed between the InAfAs layer and the InAfAs layer, crystal breakdown due to lattice mismatch will not occur. This does not occur, and the stability and reliability of the semiconductor device are improved. Furthermore, compared to the leakage current suppression layer made of InAffiAs, the material activity of the leakage current suppression layer made of GaAs is lower, so that the difficulty of the manufacturing process is reduced.

〔Example〕

FIG. 2 shows InAj! for explaining one embodiment of the present invention. A
1 shows a cutaway side view of essential parts of an s/InGaAs HEMT.

In the figure, 21 is a semi-insulating 1nP substrate, 22 is a non-insulating 1nP substrate, and 22 is a non-insulating 1nP substrate.
Doped InAlAs buffer layer, 23 is non-doped I
nCyaAs active layer, 24 is non-doped InAlAs
25 is an n-type TnAj2As electron supply layer doped with impurities such as Si, 26 is a lattice strain buffer layer, 27 is an n-type GaAs leakage current suppression layer, 28 is a source electrode, 29 is a drain electrode, and 30 is a Schottky electrode. Each gate electrode is shown.

The case of manufacturing the embodiment shown in FIG. 2 will be described.

(1) By applying the MBE method, a buffer l1i22 with a thickness of, for example, 0.5 [μm] is placed on the substrate 21.
grow. This buffer [22 is inserted to electrically isolate the substrate 21 and the active layer 23.

(2) Subsequently, an active layer 2 having a thickness of, for example, 0.1 [μm]
Grow 3.

(3) Next, add a spacer Ji with a thickness of, for example, 50 [in].
! Grow 24.

(4) Continue to increase the concentration to, for example, 2 x 10'' (C
For example, the Si-doped thickness is 400 m-”).
The [in] electron supply layer 25 is grown.

(5) Continue to use InAlAs with a thickness of, for example, 12 (fills).
The unit is a GaAs layer with a thickness of, for example, 12 [layers],
The lattice strain buffer layer 26 is formed by laminating, for example, 10 periods to form a multilayer thin film periodic structure, that is, a superlattice structure.

(6) Continue to increase the concentration to, for example, 5×10” (C
The thickness doped with Si as 111-') is, for example, 3
00 [ON] leakage current suppression layer 27 is grown.

(7) By applying a resist process, vacuum evaporation method, lift-off method, etc. in ordinary photolithography technology, source electrodes 28 and 29 made of AuGe/Au, gate made of A1, etc. Electrodes 30 are formed.

In this embodiment, the region from the semi-insulating InP substrate 21 to the n-type InAj2As electron supply layer 25 is lattice matched to InP. However, the n-type GaAs leakage current suppression layer 27 on the surface has a lattice constant significantly different from that of InP. Therefore, in order to alleviate the strain, the lattice strain buffer layer 26 composed of an InAlAs/GaAs superlattice made of a thin film sufficiently thinner than the critical film thickness is used as an n-type TnAj! As electron supply layer 25 and n-type GaAs leakage current suppression Ji! It is inserted between 27 and 27. In the absence of this lattice strain buffer 1i26, if the leakage current suppression layer 27 is formed thicker than the critical film thickness, dislocations will occur due to lattice strain, and the dislocations will penetrate to the surface and form a cross hatch pattern, forming a homogeneous epitaxial growth layer. In addition, if the thickness of the leakage current suppression layer 27 is suppressed to within the critical thickness, for example, about 30 [in], the generation of dislocations can be suppressed, but the thickness at which tunnel current can flow is suppressed. Therefore, even if a Schottky junction is formed in such a thin film, a sufficient effect in suppressing leakage current cannot be obtained.

In the HEMT described above, the component controlling the two-dimensional electron gas characteristics, that is, the semi-insulating 1nP substrate 2
1 to the n-type TnAffiAs electron supply layer 25 are In
Because it is lattice matched to P, conventional TnAfAs/InG
The ultrahigh speed performance of aAs-based HEMT is not impaired at all. In addition, since the lattice mismatch with the underlying n-type InAlAs electron supply layer 25 is sufficiently alleviated by the lattice strain buffer layer 26, the n-type GaAs leakage current suppression layer 27 is free of dislocations and has excellent homogeneity. can be formed.

Furthermore, since the Schottky barrier height of the n-type GaAs leakage current suppression layer 27 with respect to the gate electrode 30 is naturally higher than that with respect to the conventional InAlAs metal gate electrode, leakage from the gate is reduced. Current can be significantly reduced.

(Effects of the Invention) In the field effect semiconductor device according to the present invention, a plurality of InAfAs/I n, Ga
an s-based epitaxially grown compound semiconductor layer, and the 1 n
A/! InA I As / InGaAs formed on the surface of the epitaxially grown compound semiconductor layer
a lattice strain buffer layer having a multilayer thin film stacked structure made of GaAs; a CaAs leakage current suppression layer formed on the surface of the lattice strain buffer layer; a source electrode and a drain electrode conductively connected to the active layer; and a gate electrode formed on the leakage current suppression layer.

By employing the above structure, the Schottky gate electrode is formed on the GaAs leakage current suppression layer, so the Schottky barrier height is higher than when it is formed on the InAlAs leakage current suppression layer. Leakage current is small, and therefore, the voltage applied to the semiconductor device can be made sufficiently high to allow, for example, a large logic amplitude in a logic circuit, and the degree of freedom in circuit design is expanded. Also,
Even if such a leakage current suppression layer made of GaAs is provided, crystal breakdown due to lattice mismatch will occur because a lattice strain buffer layer with a multilayer thin film laminated structure is interposed between the InAfAs layer and the InAfAs layer. However, the stability and reliability of the semiconductor device are improved. Furthermore, since the leakage current suppression layer made of GaAs has a lower material activity than the leakage current suppression layer made of InAlAs, the difficulty of the manufacturing process is reduced.

[Brief explanation of drawings]

FIG. 1 is a cutaway side view of a main part of a field effect semiconductor device for explaining the present invention in detail, FIG. 2 is a cutaway side view of a main part of a field effect semiconductor device for explaining one embodiment of the present invention, and FIG. 3 each shows a cutaway side view of a main part of a field effect semiconductor device for explaining a conventional example. In the figure, 11 is a semi-insulating 1nP substrate, and 12 is a non-insulating 1nP substrate.
Doped 1nAj2As buffer layer, 13 non-doped InGaAs active layer, 14 non-doped InAfAs
a spacer layer, 15 an n-type 1nAIAs electron supply layer doped with impurities such as Si, 16 a lattice strain buffer layer,
17 is a GaAs leakage current suppression layer, 18 is a source electrode, 1
9 indicates a drain electrode, and 20 indicates a Schottky gate electrode. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani

Claims (2)

[Claims] (1) A plurality of InAlAs/InG layers formed on a semi-insulating InP substrate and including an active layer in which a channel is to be generated.
an aAs-based epitaxially grown compound semiconductor layer; and an InAlAs/GaAs formed on the surface of the InAlAs/InGaAs-based epitaxially grown compound semiconductor layer.
a lattice strain buffer layer having a multilayer thin film laminated structure consisting of: a GaAs leakage current suppression layer formed on the surface of the lattice strain buffer layer; a source electrode and a drain electrode conductively connected to the active layer; and the leakage current suppression layer. A field effect semiconductor device comprising: a gate electrode formed thereon; (2) The plurality of InAlAs/InGaAs epitaxially grown compound semiconductor layers include an active layer made of InGaAs and in which a two-dimensional carrier gas layer is generated near the surface, and a carrier supply layer made of InAlAs and supplying carriers to the active layer. 2. The field effect semiconductor device according to claim 1, further comprising: