JPH0485938A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0485938A
JPH0485938A JP19928090A JP19928090A JPH0485938A JP H0485938 A JPH0485938 A JP H0485938A JP 19928090 A JP19928090 A JP 19928090A JP 19928090 A JP19928090 A JP 19928090A JP H0485938 A JPH0485938 A JP H0485938A
Authority
JP
Japan
Prior art keywords
film
substrate
gate
hld
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19928090A
Other languages
Japanese (ja)
Inventor
Fumio Oba
富美男 大庭
Hiroki Kenjo
見上 浩樹
Tsutomu Ohori
大堀 努
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Akita Electronics Systems Co Ltd
Original Assignee
Hitachi Ltd
Akita Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Akita Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP19928090A priority Critical patent/JPH0485938A/en
Publication of JPH0485938A publication Critical patent/JPH0485938A/en
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To prevent substrate surface pollution by using an HLD film as the channel through film at formation of the source and drain regions of a MOS field effect transistor. CONSTITUTION:A gate material is formed through a thermal oxide film on one main surface of an Si substrate 1, and this is patterned to form a MOS gate 2, and the pollutant on the surface is removed and cleaned by the means such as dry etching, etc., and then it is heat-treated. Next, an HLD film 5 is made on the whole face. This HLD film 5 wraps the gate part 2, and is formed as a thin insulating film at the surface of the substrate 1. And after deposition of the HLD film, heat treatment is performed, and then ions of impurities are implanted into the surface of the substrate through the HLD film, and source and drain regions are diffused. Next, an interlayer insulating film or an HLD film 6 as a passivation film is formed thick at the whole face. And an window is made in the interlayer film 6, etc., and an Al electrode 7 is made at the source and drain regions. Hereby, the pollution of the surface of the substrate can be prevented, and the inferiority such as surface leak reduced, and the reliability of a product improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMO3電界効果トランジスタのごとき半導体装
置の製造にあたって、ソース・ドレイン領域表面の汚染
防止技術に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for preventing contamination on the surfaces of source and drain regions during the manufacture of semiconductor devices such as MO3 field effect transistors.

〔従来の技術〕[Conventional technology]

半導体基板(ウェハ)表面にMOSトランジスタを形成
するプロセスで従来より採られている方法の一つは、基
板表面に熱酸化膜を介してポリシリコンないし金属等の
導体を単独にまたはM層して形成し、これをマスクパタ
ーンの一部としてゲートパターニング加工を行って絶縁
ゲートを形成し、基板表面の洗浄処理後、ライト酸化に
よるうすい熱酸化膜を全面に形成し、このうすい熱酸化
膜を通して不純物を半導体表面にイオン打込みすること
によりソース・ドレイン領域を形成するものである。
One of the conventional methods for forming MOS transistors on the surface of a semiconductor substrate (wafer) is to apply a conductor such as polysilicon or metal to the substrate surface via a thermal oxide film, either singly or in M layers. This is used as part of a mask pattern to perform gate patterning to form an insulated gate. After cleaning the substrate surface, a thin thermal oxide film is formed on the entire surface by light oxidation, and impurities are removed through this thin thermal oxide film. The source/drain regions are formed by ion implantation into the semiconductor surface.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

−上記した従来技術の方法によれば、ゲートにはリン処
理をして導体化したポリシリコン等が使われ、ゲート加
工後の熱処理によりこのゲートのリンがアウトディフェ
ージョンを起してゲートM%の残っていない基板表面に
取り込まれ、n反転を起こして表面リークの原因となっ
た。
- According to the above-mentioned conventional method, polysilicon or the like that has been treated with phosphorus to make it conductive is used for the gate, and the phosphorus in the gate causes out-difference due to heat treatment after gate processing, resulting in gate M % was incorporated into the surface of the substrate, causing n inversion and causing surface leakage.

また、従来はゲートのドライエッチ加工時に基板に一定
以上のゲート膜を残すエッチ技術で対処L7ているが、
この方法ではゲート加工後にゲートの一部を構成するW
(タングステン)など重金属汚染が基板表面で発生しや
すく、この汚染物除去洗浄において、残り酸化を考慮し
なければならずその際の洗浄条件が限定される。
In addition, conventionally, the solution was to use an etch technique that leaves a certain amount of gate film on the substrate during gate dry etching, but
In this method, the W that forms part of the gate after gate processing is
Heavy metal contamination such as tungsten (tungsten) is likely to occur on the substrate surface, and when cleaning to remove this contaminant, residual oxidation must be taken into consideration, which limits the cleaning conditions.

本発明は上記した1点を解消するためになされたもので
あり、その目的は半導体装置を表面汚染から保護するこ
とにあり、また、他の目的はMOSトランジスタ等にお
いて、欠陥および汚染が原因してリーク不良等の半導体
装置の欠陥の発生を防止することにある。
The present invention has been made to solve the above-mentioned problem, and its purpose is to protect semiconductor devices from surface contamination.Another purpose of the present invention is to protect semiconductor devices from surface contamination. The purpose of this invention is to prevent defects in semiconductor devices such as leakage defects.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するための本発明は、半導体承板の一+
1面上に絶縁ゲートを形成し、表面の汚染除去洗浄後に
、この絶縁ゲートをうすい半導体酸化物堆積膜で覆い、
然る後に上記うすい酸化物堆積膜を通して半導体基板表
面に不純物を拡散してソース・ドレイン領域を形成する
ことを特徴とする半導体装置の製造方法に関するもので
ある。
To achieve the above object, the present invention is one of the semiconductor substrates.
An insulated gate is formed on one surface, and after the surface is cleaned to remove contamination, the insulated gate is covered with a thin semiconductor oxide deposited film.
The present invention relates to a method of manufacturing a semiconductor device, characterized in that impurities are then diffused onto the surface of the semiconductor substrate through the thin oxide deposited film to form source/drain regions.

本発明は上記半導体装置の製造方法において、上記半導
体酸化物堆積膜は化学反応により高圧低温条件下で生成
するものである。
The present invention provides the method for manufacturing a semiconductor device, wherein the semiconductor oxide deposited film is produced under high pressure and low temperature conditions through a chemical reaction.

本発明はまた、上記半導体装置の製造方法において、ソ
ース・ドレイン領域後全面を高圧低温条件下で化学反応
により生成した厚い半導体酸化物堆積膜で覆うものであ
る。
The present invention also provides the above method for manufacturing a semiconductor device, in which the entire surface behind the source/drain regions is covered with a thick semiconductor oxide deposited film produced by chemical reaction under high pressure and low temperature conditions.

〔作用〕[Effect]

半導体基板上に絶縁ゲート加工し、基板表面の汚染除去
洗浄後に熱酸化を行うことな(、HLD(高圧低温デポ
ジション)技術によろうすい酸化膜で全面を覆うことに
より、ゲートよりの不純物や重金属等による新たな汚染
を住しることなく用導体表向で従来の熱饋化腺と同しく
不側屯物十F込み時に不純物透過膜として通用ができ、
・ノーストレイン@域の形成を口J能とする。
An insulated gate is processed on a semiconductor substrate, and impurities and heavy metals from the gate are removed by covering the entire surface with a waxy oxide film using HLD (high pressure low temperature deposition) technology. It can be used as an impurity-permeable membrane when the surface of the conductor is filled with non-contaminated materials like conventional heat-oxidized glands, without introducing new contamination due to
・The formation of the North Train @ region is considered to be a function of the mouth.

〔実施例〕〔Example〕

以−ト、本発明の一実施例を回向を参照しながら説明す
る。
Hereinafter, one embodiment of the present invention will be described with reference to the present invention.

第1図は従来仕様によるMO8電界効果トランジスタの
製造プロセスのフローチャートであってこれと対照し、
て本発明を説明するためのものである。
FIG. 1 is a flowchart of the manufacturing process of MO8 field effect transistor according to conventional specifications, and in contrast,
This is for explaining the present invention.

第2図(a)〜(c)は第1図のプロセスに対応する要
部工程断面図である。
FIGS. 2(a) to 2(c) are cross-sectional views of main parts corresponding to the process of FIG. 1.

従来の仕様では、まず、第2図(a)にボすようにSi
基板lの一主表面上に、熱酸化膜を介してゲート材料を
形成しこれをバターニング加工してMOSゲート2を形
成し、ドライエッチ等の手段で表面の汚染物除去、洗浄
を行ったのち、熱処理を行う。この例ではゲート部分2
はポリSi膜の上にWSiz膜を重ねた2層構造のもの
を使用している。この場合、次の表向酸化lIQ杉成王
稈でゲート部のWSiz層が剥離することのないように
接着性向上のため熱処理を行なうものである。
In the conventional specification, first, as shown in Fig. 2(a), Si
A gate material was formed on one main surface of the substrate 1 via a thermal oxide film, and the MOS gate 2 was formed by patterning, and the surface was cleaned and contaminants were removed by means such as dry etching. Afterwards, heat treatment is performed. In this example, gate part 2
uses a two-layer structure in which a WSiz film is stacked on a poly-Si film. In this case, heat treatment is performed to improve adhesion so that the WSiz layer at the gate part does not peel off in the next surface oxidized lIQ cedar culm.

次の工程でライト熱酸化により基板表面にうすい熱酸化
ff3(100人程程度を形成する。この熱処理中にW
Sizなどの汚染が基板内に取り込まれるおそれがあっ
た。
In the next step, light thermal oxidation is performed to form a thin thermal oxidation ff3 (approximately 100 layers) on the substrate surface. During this heat treatment, W
There was a risk that contamination such as Siz would be introduced into the substrate.

このあと、上記ゲート部をマスクとして熱酸化膜3を通
して不純物を基板1内にイオン打込み、ないし拡散して
、ソース・ドレイン領域を形成するものである。
Thereafter, using the gate portion as a mask, impurities are ion-implanted or diffused into the substrate 1 through the thermal oxide film 3 to form source/drain regions.

第3図は、本発明仕様によるMO3電界劾果トランジス
タの製造プロセスのフローチャー1・である。
FIG. 3 is a flowchart 1 of the manufacturing process of an MO3 electric field transistor according to the specifications of the present invention.

第4図(a)〜(d)は第3図のプロセスに対応する要
部工程断面図である。
FIGS. 4(a) to 4(d) are cross-sectional views of main parts corresponding to the process shown in FIG. 3.

本発明仕様では、第4図(a)でポされるM OSゲー
ト加エエ稈及び汚染除去洗浄工程は従来プロセスと同様
であるが、このあとに第4図(b)に示すように、HL
、 D欣(商圧低塩化学的堆積によるシリコン酸化1t
り5を全面に形成する。このHl、DI*5はゲート部
2を包みこむとともに、基板1の表面に厚さ150人程
程度うすい絶縁膜とし7て形成される。この程度の厚さ
の欣であれば、H1,I) Heデボ後に熱処理を実施
しても汚染防止かできるとともに、ゲートへのダイレク
トインプラを阻止することができ、ゲートのWSiz表
面でのインブラントダメージ低減によるWSi2剥れ防
止の効果もあり、また、この膜を通して不純物を基板内
にインブラント(イオン打込み)を行うことも可能であ
る。
According to the specifications of the present invention, the MOS gate processing and contamination removal cleaning steps shown in FIG. 4(a) are the same as in the conventional process, but after this, the HL
, Dxin (silicon oxide 1t by commercial pressure low salt chemical deposition)
5 is formed on the entire surface. The Hl and DI*5 wrap around the gate portion 2 and are formed as an insulating film 7 on the surface of the substrate 1 with a thickness of approximately 150 mm. With a thickness of this level, it is possible to prevent contamination even if heat treatment is performed after H1, I) He deposition, and direct implantation to the gate can be prevented, and implantation on the WSiz surface of the gate can be prevented. This has the effect of preventing WSi2 peeling due to damage reduction, and it is also possible to implant impurities (ion implantation) into the substrate through this film.

本発明仕様では、HL D 膜デボジンヨンの後、熱処
理を行い、しかる後、第4図(c)に示すように上記H
L D M%を通して基板表面に不純物イオン打込みを
行い、ソース・ドレイン領域4を拡散するものである。
According to the specifications of the present invention, heat treatment is performed after HLD film debossing, and then the HLD film is heated as shown in FIG. 4(c).
Impurity ions are implanted into the substrate surface through L D M % to diffuse the source/drain regions 4 .

なお、上記プロセスの後、第4図(d)に示すように、
全面に屓間絶縁股、またはパンヘーション腟とし7てH
LD膜6を充分に厚く形成するごとになる。
Note that after the above process, as shown in FIG. 4(d),
7. H with insulation crotch or panhesion vagina on the entire surface
Each time the LD film 6 is formed sufficiently thick.

第5図は前掲の層間枠6等を窓関し、ソース・ドレイン
領域に、抵抗接触するAA電極7を形成U7たトランジ
スタ完成時の形態を示す断面図である。
FIG. 5 is a sectional view showing the completed form of a transistor in which AA electrodes 7 are formed in resistive contact with the source/drain regions using the interlayer frame 6 and the like as a window.

第6図は本発明の応用実施例をボすもので、ゲートにH
L、 D等による側壁(スペーサ)8を形成したLDD
型デバイスに本発明を通用した場合の例を示すものであ
る。
Figure 6 shows an applied embodiment of the present invention, in which H is connected to the gate.
LDD with side walls (spacers) 8 formed by L, D, etc.
This figure shows an example in which the present invention is applied to a type device.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように構成されているので、以下
に記載されるような効果を奏する。
Since the present invention is configured as described above, it produces the effects described below.

HLDItlをMO3電界効果トランジスタのソース・
ドレイン領域形成時のチャネルスルー膜として用いるこ
とにより、従来の熱酸化膜形成の際に生じるような基板
表面汚染を防止することができる。
HLDItl is the source of the MO3 field effect transistor.
By using it as a channel through film when forming a drain region, it is possible to prevent substrate surface contamination that occurs when forming a conventional thermal oxide film.

また、ゲートの一部にWなどの応力の大きい金属を用い
る場合には、HLD膜がインプラスルーH9として働(
ために表向のはがれなどのダメージの)1しるのを1債
止することができ、応力緩和の効果がある。さらに基板
表面の汚染防止の効果により、M OS電界効果トラン
ジスタの表面リークなどの不良を低減し、製品の信頼性
を向上を期待することができる。
In addition, when a metal with high stress such as W is used for a part of the gate, the HLD film acts as an implant through H9 (
Therefore, damage such as peeling of the surface can be prevented by one bond, and it has the effect of stress relaxation. Furthermore, due to the effect of preventing contamination on the substrate surface, defects such as surface leakage of MOS field effect transistors can be reduced, and product reliability can be expected to be improved.

■・・・f導体基抛、 2・・・絶縁ゲート、:3・・
・熱酸化膜、  4・・・ソース・ドレイン′iif!
域、5・−・うすイHL、 I) g*、 6−#、 
イHL l) Hl
■...f conductor base, 2...insulated gate, :3...
・Thermal oxide film, 4...source/drain'iif!
Area, 5--Light HL, I) g*, 6-#,
IHL l) Hl

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来仕様のMO3半導体装置の製造プロセスの
フローチャートである。 第2図(a)〜(c)は第1図のプロセスに対応する工
程断面図である。 第3図は本発明仕様によるMO3半導体装置の製造プロ
セスのフローチャートである。 第4図(a)〜(d)は第3図のプロセスに対応する工
程断面図である。 第5図は第4図(d)の工程にひきつづいて行われる電
極形成時の断面図である。 第6図は本発明の応用実施例を示す1.、 D D型半
導体装置の要部断面図である。 第 図 1−4 J−イ、r+1−r9 2−矛ゼ3−に仔・−ト 3−41へaレイL−Ilう? 4−−、、/ −、Z   ト= L 、r >j−セ
エ5つD−ttjr’−:6−専 、\HLDロー(
FIG. 1 is a flowchart of the manufacturing process of a conventional MO3 semiconductor device. 2(a) to 2(c) are process cross-sectional views corresponding to the process of FIG. 1. FIG. 3 is a flowchart of the manufacturing process of an MO3 semiconductor device according to the specifications of the present invention. 4(a) to 4(d) are process sectional views corresponding to the process of FIG. 3. FIG. 5 is a cross-sectional view during electrode formation performed subsequent to the step of FIG. 4(d). FIG. 6 shows an applied embodiment of the present invention.1. , DD is a sectional view of a main part of a D-type semiconductor device. Fig. 1-4 J-I, r+1-r9 2-Ray L-Il to 3-41? 4--,, / -, Z t = L , r > j-se 5 D-ttjr'-: 6-special, \HLD low (

Claims (1)

【特許請求の範囲】 1、半導体基板の一主面上に絶縁ゲートを形成し、表面
の汚染除去洗浄後にこの絶縁ゲートを含む基板表面をう
すい半導体酸化物堆積膜で覆い、然る後に上記うすい酸
化物堆積膜を通して半導体基板表面に不純物を拡散して
ソース・ドレイン領域を形成することを特徴とする半導
体装置の製造方法。 2、請求項1に記載の半導体装置の製造方法において、
上記半導体酸化物堆積膜は化学反応により高圧低温条件
下で生成するものである。 3、請求項1または2に記載の半導体装置の製造方法に
おいて、ソース・ドレイン領域形成後に全面を高圧低温
条件下で化学反応により生成した厚い半導体酸化物堆積
膜で覆う。
[Claims] 1. An insulated gate is formed on one main surface of a semiconductor substrate, and after the surface is cleaned to remove contamination, the surface of the substrate including the insulated gate is covered with a thin semiconductor oxide deposited film, and then the thin film is deposited. 1. A method of manufacturing a semiconductor device, comprising the step of diffusing impurities onto the surface of a semiconductor substrate through an oxide deposited film to form source/drain regions. 2. In the method for manufacturing a semiconductor device according to claim 1,
The semiconductor oxide deposited film is produced under high pressure and low temperature conditions through a chemical reaction. 3. In the method of manufacturing a semiconductor device according to claim 1 or 2, after forming the source/drain regions, the entire surface is covered with a thick semiconductor oxide deposited film produced by chemical reaction under high pressure and low temperature conditions.
JP19928090A 1990-07-30 1990-07-30 Manufacture of semiconductor device Pending JPH0485938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19928090A JPH0485938A (en) 1990-07-30 1990-07-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19928090A JPH0485938A (en) 1990-07-30 1990-07-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0485938A true JPH0485938A (en) 1992-03-18

Family

ID=16405168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19928090A Pending JPH0485938A (en) 1990-07-30 1990-07-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0485938A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467357B1 (en) * 2002-09-24 2005-01-24 삼성전자주식회사 Method for manufacturing a mos transister

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467357B1 (en) * 2002-09-24 2005-01-24 삼성전자주식회사 Method for manufacturing a mos transister

Similar Documents

Publication Publication Date Title
KR20040019949A (en) Manufacture method of semiconductor device with gate insulating films of different thickness
US5130264A (en) Method of making a thin film transistor
JPS5946107B2 (en) Manufacturing method of MIS type semiconductor device
KR20020002593A (en) Method for manufacturing semiconductor device using damascene process
US5924001A (en) Ion implantation for preventing polycide void
JPH0485938A (en) Manufacture of semiconductor device
US6040238A (en) Thermal annealing for preventing polycide void
JPH06132243A (en) Manufacture of semiconductor device
JPH1064898A (en) Manufacturing method of semiconductor device
JPH04154162A (en) Manufacture of mos-type semiconductor device
JPH05267665A (en) Thin-film transistor
KR100323736B1 (en) Thin film transistor and fabricating method thereof
JPH04162519A (en) Manufacture of mos semiconductor device
KR100261172B1 (en) Method for fabricating semiconductor device
KR100438768B1 (en) Method for selectively forming silicide to form silicide only on gate electrode without using photolithography process
JPH04334029A (en) Manufacture of semiconductor device
JPH05226647A (en) Manufacture of semiconductor integrated circuit device
JPH07169728A (en) Manufacture of semiconductor device
JPH0637113A (en) Manufacture of semiconductor device
KR100250686B1 (en) Manufacturing method of a semiconductor device
KR19980058438A (en) Silicide Formation Method of Semiconductor Device
KR100215778B1 (en) A fabrication method of thin film transistor for liquid crystal display
JPH0513697A (en) Manufacture of semiconductor device
JPH03120838A (en) Manufacture of semiconductor device
JPH02248048A (en) Manufacture of semiconductor device