JPH0485810A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0485810A JPH0485810A JP19879290A JP19879290A JPH0485810A JP H0485810 A JPH0485810 A JP H0485810A JP 19879290 A JP19879290 A JP 19879290A JP 19879290 A JP19879290 A JP 19879290A JP H0485810 A JPH0485810 A JP H0485810A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- stress
- trenches
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Dicing (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体基板、特にシリコン基板の大口径化もし
くは高集積化にともなった、高歩留まりで寓品質な半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor devices with high yield and high quality as semiconductor substrates, especially silicon substrates, become larger in diameter or more highly integrated.
[従来の技術]
従来、大量かつ安価な半導体装置を製造するために半導
体基板の大口径化が進み近年では直径6インチの基板を
用いた製造プロセスが主流となっている。これにより製
造工程、特に熱処理工程に伴った半導体基板の反りが著
しく増大するようになっている。こうした半導体基板の
反りは基板結晶にストレスを与え、製造工程に於て基板
表面にたくさんの結晶欠陥を発生する要因となっている
。[Prior Art] Conventionally, in order to manufacture semiconductor devices in large quantities and at low cost, the diameter of semiconductor substrates has been increasing, and in recent years, manufacturing processes using substrates with a diameter of 6 inches have become mainstream. As a result, the warpage of the semiconductor substrate during the manufacturing process, particularly during the heat treatment process, has significantly increased. Such warping of the semiconductor substrate applies stress to the substrate crystal, and is a factor in generating many crystal defects on the substrate surface during the manufacturing process.
例えば第3図に示すように基板が反りを生じた場合、素
子を集積する基板表面301には303に示すようなス
トレスが加わる。こうして基板表面に加わったストレス
によって導入される結晶欠陥はデバイスの特性を劣化さ
せ、結果として半導体装置の製造において低歩留まりと
なる大きな原因の一つとなってきている。 また、半
導体基板の大口径化にともない微細加工技術も進歩し半
導体装置の高集積化も進んでいるため単位デバイス当り
に存在する結晶欠陥の数は増大する傾向にある。For example, when the substrate is warped as shown in FIG. 3, stress as shown at 303 is applied to the substrate surface 301 on which elements are integrated. Crystal defects introduced by the stress applied to the substrate surface deteriorate the characteristics of devices, and as a result become one of the major causes of low yields in the manufacture of semiconductor devices. In addition, as semiconductor substrates become larger in diameter, microfabrication technology advances and semiconductor devices become more highly integrated, so the number of crystal defects present per unit device tends to increase.
[発明が解決しようとする課題]
本発明の目的はかかる課題を解決するためのもので、半
導体基板の反りに起因した結晶欠陥の発生を最小限に抑
制し、高集積かつ高歩留まりな半導体装置の製造方法を
提供するものであるを持ち、低コストで集積度の高い半
導体装置を開発することにある。[Problems to be Solved by the Invention] The purpose of the present invention is to solve the above problems, and to provide a highly integrated and high-yield semiconductor device that minimizes the occurrence of crystal defects caused by warpage of a semiconductor substrate. The purpose of the present invention is to develop a low-cost, highly integrated semiconductor device by providing a manufacturing method for the same.
[課題を解決するための手段]
本発明における半導体装置の製造方法においては、半導
体基板のスクライブラインとなる領域に溝を形成する工
程を含むことを特徴とする。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is characterized by including a step of forming a groove in a region of a semiconductor substrate that will become a scribe line.
[実施例コ
以下本発明を添付の図面並びに具体例を参照してさらに
詳細に説明する。[Examples] The present invention will now be described in more detail with reference to the accompanying drawings and specific examples.
第1図は本発明による半導体基板の断面を示す。FIG. 1 shows a cross section of a semiconductor substrate according to the invention.
図に示すように素子が形成される基板表面101は、ス
クライブラインに形成された溝103により各チップ毎
に各々独立した島を形成している。As shown in the figure, a substrate surface 101 on which elements are formed forms independent islands for each chip by grooves 103 formed in scribe lines.
従って基板が反った場合には、従来、基板表面に加わっ
ていたストレスは主としてスクライブラインに形成され
た溝の底部104に加わるため、素子が形成される基板
表面にかかるストレスは抑制される。Therefore, when the substrate warps, the stress that would conventionally be applied to the substrate surface is mainly applied to the bottom 104 of the groove formed in the scribe line, so the stress applied to the substrate surface on which elements are formed is suppressed.
溝の形成方法としては第2図に示すように従来のスクラ
イブラインとなる領域上に例えばフォトリソ技術を用い
て数μmから数十μmの幅を持つようにレジストのバタ
ーニング201を施しドライエツチングにより数十μm
から100μm程度の深さ程度に半導体基板をエツチン
グする。As shown in FIG. 2, the conventional method for forming grooves is to apply resist patterning 201 on the area that will become the scribe line using, for example, photolithography to have a width of several μm to several tens of μm, and then dry etching. Several tens of μm
The semiconductor substrate is etched to a depth of about 100 μm.
溝の形成は例えば製造工程の第一工程として行なう。ま
た層間絶縁膜等の薄膜形成直後で熱処理工程の前に行な
うことによりストレスの緩和に対してより効果的に作用
する。Formation of the grooves is performed, for example, as the first step of the manufacturing process. Further, by performing the process immediately after forming a thin film such as an interlayer insulating film and before a heat treatment process, stress can be more effectively alleviated.
[発明の効果コ
以上述べたように本発明によれば、
半導体基板の反りに起因したストレスは主としてスクラ
イブラインに形成された溝の底部に加わるため、素子が
形成される基板表面にかかるストレスは抑制される。従
って結晶欠陥の発生を抑制し、高集積かつ高歩留まりな
半導体装置の製造を行なうことが可能となった。[Effects of the Invention] As described above, according to the present invention, the stress caused by the warpage of the semiconductor substrate is mainly applied to the bottom of the groove formed in the scribe line, so the stress applied to the surface of the substrate on which elements are formed is reduced. suppressed. Therefore, it has become possible to suppress the occurrence of crystal defects and to manufacture semiconductor devices with high integration and high yield.
第1図は、本発明による半導体基板の主要断面図。
第2図は、本発明にかかる溝を形成するためのレジスト
パターンを示す図。
第3図は、従来の半導体基板の主要断面図。
図中
101゜
102゜
103゜
104、。
基板表面
基板裏面
スクライブライン上に形成した溝
本発明の基板に加わるストレス
悼1風
201、、、基板表面
202、、、フォトレジスト
301゜
302゜
303゜
、基板表面
、基板裏面
、基板表面に加わるストレス
′4−za
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三部 他1名
茅3in
30之FIG. 1 is a main cross-sectional view of a semiconductor substrate according to the present invention. FIG. 2 is a diagram showing a resist pattern for forming grooves according to the present invention. FIG. 3 is a main cross-sectional view of a conventional semiconductor substrate. In the figure: 101°102°103°104. Groove formed on the scribe line on the front surface of the substrate, the back surface of the substrate Stress applied to the substrate of the present invention 201, ..., the surface of the substrate 202, ..., the photoresist 301゜302゜303゜, the front surface of the substrate, the back surface of the substrate, the front surface of the substrate Stress'4-za Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki and 1 other person Kaya 3in 30
Claims (1)
る工程を含むことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising the step of forming a groove in a region of a semiconductor substrate that will become a scribe line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19879290A JPH0485810A (en) | 1990-07-26 | 1990-07-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19879290A JPH0485810A (en) | 1990-07-26 | 1990-07-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0485810A true JPH0485810A (en) | 1992-03-18 |
Family
ID=16396985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19879290A Pending JPH0485810A (en) | 1990-07-26 | 1990-07-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0485810A (en) |
-
1990
- 1990-07-26 JP JP19879290A patent/JPH0485810A/en active Pending
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