JPH0483485A - Recording/reproducing device for digital image signal - Google Patents

Abstract

PURPOSE:To prevent the execution of digital dubbing by selecting a storage medium storing the 2nd buffering table corresponding to a video software to be reproduced at the time of loading the storage medium, and inhibiting the output of a digital image signal. CONSTITUTION:This recording/reproducing device is provided with a memory 18 storing the 1st buffering table for self-recording/ reproducing, a loading part 19 for loading the storage medium storing the 2nd buffering table corresponding to a video software to be reproduced and generating a detection signal F2 indicating the loading, a means SW3 for selecting the 1st or 2nd buffering table in accordance with the detection signal F2 at the time of reproducing, and a means SW2 for selectively outputting the reproduced digital image signal in response to the detection signal F2. When the detection signal F2 is generated at the time of loading an IC card, the output of a digital reproduced signal of the video software is interrupted. Thus, the digital dubbing of the video software can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is effective for recording and reproducing devices for digital image signals, particularly for preventing dubbing of video software.

[Summary of the invention]

This invention converts image data into a block structure, detects the dynamic range of the block, and converts pixel data normalized by the maximum or minimum value of the block according to the dynamic range as a highly efficient encoding of image data. , the number of bits is selected from the buffering table in order to keep the amount of data generated in a predetermined period approximately constant by using encoding that quantizes with a variable number of bits smaller than the original number of bits. In a digital image signal recording/playback device having a buffering circuit controlled by a threshold value, a first buffering table for self-recording and playback, and a second buffering table corresponding to video software to be replayed. Apart from this, when the storage medium storing the second buffering table is installed, the second buffering table is selected, and at the same time, the output of the reproduced digital image signal is prohibited. , can effectively prevent digital dubbing.

[Conventional technology]

As an encoding method for compressing the amount of transmitted data of a video signal, the applicant of the present application has proposed encoding adapted to dynamic range (referred to as ADRC).

In ADRC, image data is converted into a two-dimensional or three-dimensional block structure, and the dynamic range D of each block is
R (difference between maximum value MAX and minimum value MIN) is calculated for each two-dimensional block consisting of, for example, (8 lines x 8 pixels = 64 pixels). Furthermore, the minimum level (minimum value) MIN within the block is removed from the input pixel data. The pixel data after the minimum value has been removed is converted into a code signal.

In this quantization, the detected dynamic range DR is equally divided into four level ranges corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits, and the level range to which each pixel data in the block belongs is detected. This is a process of generating a code signal indicating this level range.

[Problem to be solved by the invention]

Digital VTR that compresses image data using ADRC
In this case, it is desirable to have a function to prevent dubbing of video software, especially digital dubbing, from the viewpoint of copyright protection.

An object of the present invention is to provide a digital image signal recording/reproducing apparatus that has a function of preventing digital dubbing by utilizing ADRC buffering.

[Means to solve the problem]

This invention converts image data into a block structure, detects the dynamic range of the block, and converts pixel data normalized by the maximum or minimum value of the block according to the dynamic range as a highly efficient encoding of image data. , the number of bits is selected from the buffering table in order to keep the amount of data generated in a predetermined period approximately constant by using encoding that quantizes with a variable number of bits smaller than the original number of bits. In a digital image signal recording/playback device having a buffering circuit controlled by a threshold value, a memory (18) in which a first buffering table for self-recording/playback is stored, and video software to be played back. A storage medium storing a corresponding second buffering table is mounted, and a mounting unit (
19); Means SW3 for selecting the I-th buffering table and the second buffering table in response to the detection signal F2 during re-passing; and selecting the reproduced digital image signal in response to the detection signal F2. This is a digital image signal recording/reproducing device comprising means SW2 for outputting digital image signals.

[Effect]

When playing commercially available or rental video software, a buffering table optimal for the software is stored in a storage medium such as an IC card, and this IC card is inserted into the card reading section 19. The video software processes the playback signal based on the buffering table from the IC card.In addition, when the IC card is inserted, a detection signal F2 is generated, and the digital reciprocating signal of the video software is output from the switching circuit. This is blocked by SW2.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description is given in the following order.

a. Recording/playback circuit A. ADRC encoder and decoder C. Buffering circuit d. Modification a. Recording/playback circuit FIG. 1 shows the entire recording/playback circuit of an embodiment of the present invention. be. An analog video signal is supplied to an input terminal indicated by 1. The A/D converter 2 converts the analog video signal into a digital video signal in which one sample is quantized to 8 bits, for example. This digital video signal is supplied to the input terminal a of the switching circuit SWI.

Input terminal 3 to other input terminals of switching circuit SWI
A digital video signal is supplied from the The output signal of the switching circuit SWI is supplied to the encoder 4 of ADRC. The encoded output of the ADRC encoder 4 is supplied to a parity generation circuit 5, where error detection and error correction code encoding is performed. The output of the parity generation circuit 5 is supplied to the recording circuit 6. The recording circuit 6 includes digital modulation, a recording amplifier, and the like. In addition, in the recording circuit 6, the terminal 7
The dubbing prevention flag F1 is supplied from
1 is added to the recording signal.

A recording signal from the recording circuit 6 is taken out to an output terminal 8. Although not shown, a rotary head is connected to the output terminal 8, and recorded digital signals are recorded as diagonal tracks on the magnetic tape. As the recording medium, in addition to the magnetic table, a disk-shaped medium such as a rewritable optical disk may be used.

A digital reproduction signal reproduced from the magnetic tape is supplied from an input terminal 11 to a reproduction circuit 12.

The reproducing circuit 12 includes a reproducing amplifier, a digital demodulation circuit, etc., and the output signal of the reproducing circuit 12 is connected to an ADRC decoder 1.
3. The decoded output of decoder 13 is supplied to error correction and modification circuit 14 . The error correction and modification circuit 14 detects and corrects errors that occur during the recording/reproducing process, and corrects uncorrectable errors by means of average value interpolation or the like. The output signal of the error correction and modification circuit 14 is a D/A
It is supplied to the input terminal C of the converter 15 and the switching circuit SW2. No signals are applied to the other input terminals of the switching circuit SW2. A reproduced analog signal from the D/A converter 15 is taken out to an analog output terminal 16. A reproduced digital video signal from the input terminal C of the switching circuit SW2 is taken out to the digital output terminal 17.

The ADRC encoder 4 includes a buffering circuit as described below to keep the amount of data constant during a predetermined period, for example, one frame. A threshold table for buffering used for self-recording/playback is stored in ROM1B. A buffering table is connected to the ADRC decoder 13 via a switching circuit SW3. R through terminal e of switching circuit SW3
The OM18 is connected to the ADRC decoder 13, and the card reading section 19 is connected to the ADRC decoder 1 through its terminal f.
Connected to 3.

The card reading section 19 is provided to read a buffering table stored in an IC card (not shown). Further, when the IC card is inserted into the card reading section 19, a detection signal F2 of "1" is generated from the card reading section 19. The switching circuit SW2 is controlled by the dubbing prevention flag F1 or the detection signal F2 separated by the reproduction circuit 12.

IC cards can be purchased together with video software that cannot be dubbed, such as commercially available video software and rental video software. In the case of rental, it is preferable that the IC card's power supply be consumed in about two to three days.

FIG. 2 shows an example of creating video software.

First, the video obtained by shooting (step 21) is edited in the next step 22 to be used as a video source. The data of this video source is analyzed (step 23), and a buffering table optimal for the video source is created (step 24). Analysis of this video source can be performed, for example, by simulation using a computer. This buffering table is stored in the memory of the IC card (step 25). Also, ADRC encoding (step 2) is performed using the created buffering table.
6) is done. The encoded output is recorded on the master tape (step 27).

Video software is created from the master tape in the same way as before.

In the embodiment described above, switching circuits SWI, SW2 and SW3 are controlled according to mode 1, mode 2 and mode 3 of the digital VTR. Mode 1 is an operation in which signals other than broadcast video signals are recorded and played back on the same VTR, a so-called self-recording/playback operation. During recording in mode 1, analog input or digital input is selected by switching circuit SWl. The ADRC encoder 4 performs ADRC encoding and buffering using a buffering table stored in the ROM 1B. In addition, the flag F1 is an "On" bit that means that dubbing is possible, and this flag Fl(-"0
”) is recorded on the magnetic tape.

During reproduction in mode 1, a reproduced digital signal from the magnetic tape is supplied to the input terminal 1, and the reproduced digital signal is supplied to the ADRC decoder 13 via the reproduction circuit 12. (F1="O"), and since no IC card is inserted, the input terminal C of the switching circuit SW2 is selected. Therefore, an analog video signal is obtained at the output terminal 16, and a digital video signal is obtained at the output terminal 17. In mode 1, analog dubbing and digital dubbing can be performed.

Mode 2 is a self-recording and reproducing mode similar to mode 1, but is a mode for recording and reproducing broadcast signals.

In this case, the flag F1 inserted at the time of recording is "do" which means that digital dubbing is not possible.

Therefore, during playback, since the flag F1 is "1", the switching circuit SW2 selects the terminal d, and in mode 2, where no digital output is obtained, analog dubbing is allowed, but digital dubbing is prohibited. If digital dubbing of broadcast signals is allowed, use mode 2.
It is not necessary to provide

Mode 3 is an operation for reproducing video software previously created by a specialized company such as a movie company as shown in FIG. In the case of video software, an IC card is inserted into the card reading section 19 when playing the video software. Therefore, A
The DRC decoder 13 can restore high-quality reproduced images using the optimal buffering table stored in the IC card. The detection signal F2 from the card reading section L9 becomes 1", the switching circuit SW2 selects the terminal d, and the digital output of the video software cannot be obtained. Therefore, analog dubbing is possible, but digital dubbing is prohibited. be done.

b. ADRC encoder and decoder Figure 3 shows the ADRC encoder and decoder.
' An example of the RC encoder 4 is shown in which video data from an input terminal indicated by 28 is sent to a blocking circuit 29 where the data arrangement is converted from the order of scanning lines to the order of blocks.

One frame or one field of screen is subdivided into blocks of (4 lines x 4 pixels=16 pixels), as shown in FIG. 4, for example. The output signal of the blocking circuit 29 is supplied to a detection circuit 30 and a delay circuit 31.

The detection circuit 30 detects the minimum value MIN and maximum value MA of the block.
Dynamic range DR, which is the difference between X and the minimum value MIN
Detect. The delay circuit 31 delays data for a time to detect the minimum value MIN and dynamic range DR. In the subtraction circuit 32, the minimum value MIN is subtracted from the video data from the delay circuit 31, and video data from which the minimum value has been removed is obtained from the subtraction circuit 32.

The output data of the subtraction circuit 32 is supplied to a quantization circuit 34 via a delay circuit 33. The quantization circuit 34 is supplied with the dynamic range DR via the delay circuit 35, and is also supplied with the allocated bit number n from the bit number determination circuit 37. A code signal DT having a number of bits n smaller than the original number of bits (8 bits) is obtained from the quantization circuit 34. The quantization circuit 34 performs quantization adapted to the dynamic range DR. In other words, the dynamic range DR is 2
``The video data from which the minimum value has been removed is divided by the equally divided quantization step Δ, and the value obtained by rounding down the quotient and converting it into an integer is used as the code signal DT.The quantization circuit 34 is composed of a division circuit or a ROM. can.

The bit number determining circuit 37 receives the dynamic range DR (=MAX-MIN) passed through the delay circuit 35 and the threshold values T1 to T4 (TI<7) from the buffering circuit 36.
2<73<74) are supplied. The number of allocated bits n is determined based on the relationship between the dynamic range DR and the threshold values T1 to T4.

In variable-length ADRC, efficient encoding can be performed by reducing the number of allocated bits n for blocks with a small dynamic range DR, and increasing the number of allocated bits n for blocks with a large dynamic range DR. In other words, the code signal is not transmitted to the block with (DR<TI), and the dynamic range DR and average value M
Only IN is transmitted, blocks with (Tl≦DR<T2) are set to (n=1), blocks with (T2≦DR<73) are set to (n=2), and (T3≦DR<T4). ) blocks are set to (n=3), and blocks where (DR≧74) are set to (n=4).

In such variable length ADRC, the amount of generated information can be controlled (that is, buffering) by changing the threshold values T1 to T4. Therefore, the amount of generated information per field or frame can be set to a predetermined value. Even for transmission lines such as digital VTRs that require variable length
DRC can be applied.

In the buffering circuit 36, as described later, a buffering table including a plurality of sets of threshold values (Tl, T2, T3, T4), for example, 32 sets, is prepared, and these sets of threshold values are used as parameter codes. Pi (i=o, 1
,2. ..., 31). It is set so that the amount of generated information decreases monotonically as the number i of the parameter code Pi increases. However, as the amount of generated information decreases, the quality of the restored image deteriorates.

The parameter code Pi, the minimum dynamic range DR1 value MIN, and the code signal DT are supplied to the framing circuit 38, and the transmission data is taken out to the output terminal 39. The framing circuit 38 has a parameter code Pi and a dynamic range DR.

The minimum value MIN and the code signal DT are arranged byte serially to form transmission data to which a synchronization signal is added.

Although not shown, the ADRC decoder 13 has the above-mentioned ADRC
Processing is performed in the reverse order of encoder 4.

That is, by frame decomposition, the parameter code Pi, the dynamic range DR1 minimum value MIN, and the code signal D
Let T be a separate signal. The parameter code Pi identifies the same set of thresholds used in the ADRC encoder 4 and the thresholds are read from the buffering table. The level corresponding to the code signal of each pixel is decoded using the set of threshold values, dynamic range DR, and code signal DT. This decoded output has a minimum value M
A restored value is obtained by adding IN.

This restored value is supplied to a block decomposition circuit and converted into scan order data.

C. Buffering Circuit FIG. 5 shows an example of the buffering circuit 36. The buffering circuit 36 is provided with a memory (RAM) indicated by 41 in order to create a frequency distribution table and a cumulative frequency distribution table, and an address is supplied to this memory 41 via a multiplexer 42. The dynamic range D is input from the input terminal 43 as one input of the multiplexer 42.
R is supplied, and the address from the address generation circuit 50 is supplied as the other input. The output signal of the adder circuit 44 is input to the memory 41, and the output data of the memory 41 and the output of the multiplexer 45 are added together by the adder circuit 44.

The output of the adder circuit 44 is supplied to a register 46, and the output of the register 46 is supplied to a multiplexer 45 and a comparator circuit 47. The multiplexer 45 is supplied with O and +1 in addition to the output of the register 46. When an arithmetic operation is performed on the amount of information generated by 0, the amount of information Ai generated in the I frame period is determined from the output of the register 46, for example. .

In the comparison circuit 47, the generated information amount Ai is compared with the target value Q from the terminal 48, and the output signal of the comparison circuit 47 is supplied to the parameter code generation circuit 49 and the register 51. Parameter code Pi from parameter code generation circuit 49 is supplied to address generation circuit 50 and register 51. The parameter code Pi taken into the register 51 is supplied to the framing circuit 38 as described above, and is also supplied to the ROM 1B in which a buffering table for self-recording and playback is stored. The ROM 1B generates a set of threshold values (Tl i, T2 i, T31, T4 i) corresponding to the parameter code Pi input as an address. This threshold value is supplied to the bit number determination circuit 37 as described above.

FIG. 6 is a flowchart showing the operation of the buffering circuit 36. In a first step 61, the memory 41,
Register 46 is cleared to zero.

For clearing the memory 41 to zero, the multiplexer 42
selects the address generated by the address generation circuit 5o,
The output of the adder circuit 44 is always 0. The address is (
0, 1, 2, ..., 255), and the memory 41
0 data is written to all addresses.

In the next step 62, the dynamic range D of one frame, which is a unit period buffered in the memory 41, is
A frequency distribution table of R is created. The multiplexer 42 is
The dynamic range DR from the terminal 43 is selected, and the multiplexer 45 translates +1 to:111. Therefore, when one frame period ends, the frequency of occurrence of each DR is stored in each address of the memory 4 corresponding to the dynamic range DR. The frequency distribution table of this memory 41 is shown in FIG.
As shown in , the horizontal axis is DR and the vertical axis is power.

Next, the frequency distribution table is converted into a cumulative frequency distribution table (step 63). When creating the cumulative frequency distribution table, the multiplexer 42 selects the address from the address generation circuit 50, and the multiplexer 45 selects the address from the register 46. Select. The address decrements sequentially from 255 to 0.

The readout output of the memory 41 is supplied to an adder circuit 44,
The adder circuit 44 adds the contents of the register 46. The output of the adder circuit 44 is written to the same address as the read address of the memory 41, and the contents of the register 46 are updated to the output of the adder circuit 44. In the initial state where the address of the memory 41 is set to 255, the register 46 is cleared to zero. When the frequencies are accumulated for all addresses in the memory 41, the memory 41 stores the information shown in FIG. 7B.
The cumulative frequency distribution table shown in is created.

For this cumulative frequency distribution table, a set of threshold values (T1 i,
The occurrence information NAi when 'I'2 i, T3 i, T4 i) is applied is calculated (step 64).

When calculating the generated information amount Ai, the multiplexer 42 selects the output of the address generation circuit 50, and the multiplexer 4
5 selects the output of register 46.

The parameter code generation circuit 49 generates a parameter code that changes sequentially from PO to P31. The parameter code pt is supplied to the address generation circuit 50,
Addresses corresponding to each threshold value (Tl i, T2 i, T3 f, , T4i) are generated sequentially. Values read from addresses corresponding to each threshold value are accumulated by an adder circuit 44 and a register 46. This cumulative value corresponds to the occurrence information 1iAi when the set of thresholds specified by the parameter code Pi is applied. That is, in the cumulative frequency distribution table shown in FIG. 7B, the thresholds TI, T2, T
3. Value A read from the address corresponding to T4
1, A2, A3, A4 total (i!!(A1+A2+A
3+A4) multiplied by the number of pixels in the block (16) is the amount of generated information (number of bits). However, since the number of pixels is constant, the 16 multiplication process is omitted in the buffering circuit 36 shown in FIG.

This generated information amount Ai is compared with the target value Q (step 65). The output of the comparison circuit 47 that occurs when (At≦Q) is satisfied is supplied to the parameter code generation circuit 49 and the register 51, the increment of the parameter code Pi is stopped, and the parameter code Pi is taken into the register 51. . The parameter code Pi from the register 51 and the set of threshold values generated in the ROM 1B are output (step 66).

At step 65 of determination in the comparison circuit 47, (Ai≦
When Q) does not hold, the parameter code Pi is changed to the next one, P i+1, and the address corresponding to P i+1 is generated from the address generation circuit 50. The generated information amount Ai+1 is calculated in the same manner as described above, and compared with the target value Q in the comparison circuit 47. Until (Ai≦Q) holds,
The above operation is repeated.

During self-recording and playback, the parameter code Pt separated from the playback data is supplied to the ROM1B, and the threshold values ITI to T4 specified by the parameter code Pi are input to the RO.
Read from M1B.

This set of threshold values T1 to T4 and the dynamic range DR
The number n of bits allocated to the block is determined from the following. When playing video software, I instead of ROM1B
A table of C cards is selected.

d. Modification The storage medium for video software is not limited to an IC card, but an optical card or the like can be used.

〔Effect of the invention〕

According to this invention, high-quality recording and playback and high-quality dubbing are possible during self-recording and playback, and high-quality playback images can be viewed when playing back video software. Digital dubbing of software can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a route diagram used to explain an example of a method for creating video software, and FIG. 3 is a block diagram of an example of an ADRC encoder. Figure 4 is a route map used to explain the blocks.
Figure 5 is a block diagram of an example of a buffering circuit, Figure 6 is a block diagram of an example of a buffering circuit.
7 and 7 are route maps used to explain the operation of the buffering circuit. Description of main symbols in the drawings SWI to SW3 F switching circuit, 4: ADRC encoder, 11: ADRC decoder, 1st: ROM in which a buffering table is stored. 19: Card reading section, 36: Buffering circuit.

Claims (1)

[Claims] As high-efficiency encoding of image data, the image data is converted into a block structure, the dynamic range of the block is detected, and the pixel data normalized by the maximum or minimum value of the block is converted into the block structure. Using encoding that quantizes with a variable number of bits smaller than the original number of bits depending on the dynamic range, the number of bits is set to approximately a constant value in order to keep the amount of data generated in a predetermined period by the above encoding to an approximately constant value. In a digital image signal recording and reproducing apparatus having a buffering circuit controlled by a threshold value selected from a buffering table, a memory storing a first buffering table for self-recording and reproducing, and a memory to be reproduced. A storage medium storing a second buffering table corresponding to video software is mounted thereon, and a mounting unit generates a detection signal indicating this mounting;
A digital image signal recording/reproducing apparatus comprising: means for selecting a buffering table of the buffering table in response to the detection signal; and means for selectively outputting the reproduced digital image signal in response to the detection signal.