JPH0480291U - - Google Patents
Info
- Publication number
- JPH0480291U JPH0480291U JP12405090U JP12405090U JPH0480291U JP H0480291 U JPH0480291 U JP H0480291U JP 12405090 U JP12405090 U JP 12405090U JP 12405090 U JP12405090 U JP 12405090U JP H0480291 U JPH0480291 U JP H0480291U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- clock signals
- types
- switching elements
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Description
第１図は本考案の一実施例の構成図、第２図は
第１図の動作を示すタイムチヤート、第３図は本
考案の一実施例の応用例の構成図、第４図は第３
図の動作を示すタイムチヤート、第５図は従来例
の構成図である。
Ｃ１，Ｃ２…………コンデンサー、Ｒ１，Ｒ２
……抵抗、Ｄ１，Ｄ２……保護ダイオード、１…
…信号発生器、４，５……スイツチング素子、６
……トランス、２，３，７，８，９……Ｃ−ＭＯ
Ｓバツフア、１０，１１……アンド（Ｃ−ＭＯＳ
）。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart showing the operation of Fig. 1, Fig. 3 is a block diagram of an application example of an embodiment of the present invention, and Fig. 4 is a 3
A time chart showing the operation shown in FIG. 5 is a configuration diagram of a conventional example. C1, C2……Capacitor, R1, R2
...Resistor, D1, D2...Protection diode, 1...
... Signal generator, 4, 5 ... Switching element, 6
...trans, 2, 3, 7, 8, 9...C-MO
S bus, 10, 11...and (C-MOS
).
Claims (1)
位相の２種のクロツク信号とし、これらのクロツ
ク信号をＣ−ＭＯＳロジツクを介して２個のスイ
ツチング素子を交互に駆動し、直流信号を交流信
号に変換するインバータにおいて、 前記互いに２種のクロツク信号をそれぞれ積分
回路を介してＣ−ＭＯＳロジツクに与え、前記２
個のスイツチング素子がともにオフになる期間を
持つようにしたことを特徴とするインバータ。[Claims for Utility Model Registration] A clock signal generated by a signal generator is made into two types of clock signals having mutually opposite phases, and these clock signals are used to alternately drive two switching elements via a C-MOS logic. , in an inverter that converts a DC signal into an AC signal, the two types of clock signals are respectively applied to the C-MOS logic via an integrating circuit,
An inverter characterized in that each of the switching elements has a period in which both are turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12405090U JPH0480291U (en) | 1990-11-26 | 1990-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12405090U JPH0480291U (en) | 1990-11-26 | 1990-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480291U true JPH0480291U (en) | 1992-07-13 |
Family
ID=31871724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12405090U Pending JPH0480291U (en) | 1990-11-26 | 1990-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480291U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008161052A (en) * | 2003-06-11 | 2008-07-10 | Seiko Epson Corp | Charging system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5316492A (en) * | 1976-07-29 | 1978-02-15 | Masaru Yoshimura | Tray capable of cutting together with tooth model |
| JPS5632912A (en) * | 1979-08-28 | 1981-04-02 | Hiroichi Furukawa | Digger for root crops |
-
1990
- 1990-11-26 JP JP12405090U patent/JPH0480291U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5316492A (en) * | 1976-07-29 | 1978-02-15 | Masaru Yoshimura | Tray capable of cutting together with tooth model |
| JPS5632912A (en) * | 1979-08-28 | 1981-04-02 | Hiroichi Furukawa | Digger for root crops |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008161052A (en) * | 2003-06-11 | 2008-07-10 | Seiko Epson Corp | Charging system |
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