JPH0479791A - Three-phase pwm voltage generating method - Google Patents

Abstract

PURPOSE:To suppress distortion of output waveform remarkably through a simple constitution, when a basic wave voltage is outputted, by substituting a closest command voltage vector in PWM controllable region for a command voltage vector existing at the outside of the PWM controllable region. CONSTITUTION:When a command voltage vector V exists at the outside of PWM controllable region, a holding time calculating circuit 11 calculates holding times T0, T1, T2 in which the holding time T0 of zero vector exhibits a negative value. A command voltage vector substituting means 14 adds a comparison value A to the holding time T2 provided from the holding time calculating means 11 thus producing a comparison value B. Since the comparison value A is negative, the comparison value B is lower than the holding time T2. The zero vector holding time T0 is then split equally into two and subtracted, respectively, from the holding times T1, T2 and the command voltage vector V is moved to a point P at which a normal to the side (m) representing the border of the PWM controllable region crosses, thus substituting a PWM controllable command voltage vector V' for the command voltage vector V.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a PWM voltage generation method in a three-phase inverter device.

(Prior Art) Conventionally, a PWM voltage generation method in a voltage source inverter device compares a triangular wave carrier and a sinusoidal modulated wave, and outputs a voltage pulse when the modulated wave is larger than the carrier. Ta.

As a result, a substantially sinusoidal output current is obtained, thereby supplying AC power at a predetermined frequency to a load such as a motor.

(Problem to be Solved by the Invention) However, in the method described above, when outputting a fundamental wave voltage that is higher than the maximum value that can be modulated by a sine wave, as shown in FIG. PWM by making the amplitude of the carrier larger than the amplitude of the triangular wave carrier.
Since a voltage is generated, the modulated wave is output continuously near its peak value, resulting in a disadvantage that the output waveform is highly distorted.

The present invention has been made in view of the above circumstances, and its purpose is to minimize the distortion of the output waveform while having a simple configuration when outputting a fundamental wave voltage higher than the maximum value that can be modulated by a sine wave. An object of the present invention is to provide a three-phase PWM voltage generation method that can generate a three-phase PWM voltage.

[Configuration of the Invention (Means for Solving the Problems) The three-phase PWM voltage generation method of the present invention converts a DC power source into a three-phase PWM voltage signal when a command voltage vector is given. Targeting inverter equipment that outputs
The command voltage vector is PW in the voltage vector plane
The feature is that when the command voltage vector exists outside the M controllable region, the command voltage vector is replaced with the nearest command voltage vector in the PWM controllable region, thereby converting it into a three-phase PWM voltage signal and outputting it.

(Function) According to the three-phase PWM voltage generation method of the present invention, when a phase command value and a voltage command value are given as command voltage vectors, the corresponding basic output within the PWM controllable region on the voltage vector plane is A two-phase PWM voltage signal is generated by time-ratio control of the vector. and,
When the command voltage vector is outside the PWM controllable region, a three-phase PWM voltage signal is generated in the same manner as described above by replacing the command voltage vector with the nearest command voltage vector within the PWM controllable region. Therefore, even in such a case, a fundamental wave voltage higher than the maximum fundamental wave voltage that can be modulated by a sine wave can be converted to P with extremely low distortion.
It can be output as a WM waveform and can be realized with a simple configuration.

(Example) Hereinafter, a first example of the present invention will be described with reference to FIGS. 1 to 7.

First, the configuration of the inverter device targeted in this embodiment will be briefly described. In FIG. 2, the inverter main circuit 1 includes six switching elements such as transistors 3u, 3v, 3w, 3x,
3y and 3z are connected in a well-known bridge configuration. A power supply voltage V is applied between the main circuit busbars 2a and 2b, respectively.
/2 DC power supplies 4a and 4b are connected in series, and a smoothing capacitor 5 is also connected. A drive signal is given to each of the switching elements 3u to 3z from a switching control circuit 6, and three-phase power is supplied to a motor 7 as a load in response to this. In the above-mentioned inverter main circuit 1, since the switching elements in each arm la, Ib, and IC pair are given a drive signal to turn on only one of them, there are 23 combinations of these switching modes. - There are 8 switching modes, and depending on these switching modes, the voltage of each phase with respect to the virtual neutral point of the load is ±V/2
You will have to choose one of the following. Therefore, among the voltage space vectors that give an instantaneous vector expression to the output voltage of the inverter device by considering the phase difference between each phase, those that can be output instantaneously can be made to correspond to the switching mode described above as follows. Express. That is, the switching element 3u on the positive side of each phase.

When 3v 3w is on, set Sa, Sb, Sc to "
1", the negative side switching element 3x.

If 3y and 3z are on, it is expressed as "0", then (S a,
S b, S c), and when these are illustrated, as shown by the solid line in FIG. Zero vector (0,0,0), (1,1
,1).

Now, the three-phase PWM signal generating circuit 8 for controlling the switching of each switching element in the inverter device has a configuration shown in FIG.

When the phase command value θ8 is given, the phase command value classification means 9 classifies it into each unit area obtained by dividing the electrical angle 2π into 12 equal parts, and provides the classification result to the switching mode determination means 0 as 4-bit information. At the same time, the advance angle θ in the unit area is calculated and output. The switching mode determining means 10 divides the phase command value θ8 classified by the phase command value classification means 9 into two types of basic output vectors (voltage space hectors) each having a phase of π/3, depending on the unit area to which the phase command value θ8 belongs. The corresponding switching mode and the switching mode corresponding to the zero vector are determined, and in principle, two types of basic output vectors, the phase command value θ8 and the closest phase in FIG. 5, are determined. That is,
For example, when the phase command value θ8 is at the position shown in Figure 5, the basic output vector and therefore the switching mode are (
1°0.0) and (1,1,0) will be determined.

By the way, in the waveform forming method in this embodiment, a voltage space vector of arbitrary size and phase is outputted by controlling the time ratio between the basic output vector (voltage space vector) and the zero vector whose phases are different from each other by π/3. In this case, the voltage space vector that can be output should exist inside the hexagon connecting the tips of the six basic output vectors in FIG. However, considering the sine wave approximation, the maximum output voltage varies depending on the phase angle, so
The limit area of sinusoidal modulation that can be realized by controlling the time ratio between the basic output vector and the zero vector is inside the inscribed circle of the hexagon. Therefore, within this limit region, a polar coordinate system can be used to realize an arbitrary voltage space vector.
Considering symmetry, the discussion can be limited to the π/6 region.

Figure 6 shows the basic output vectors (1,0,0), (11,0
) and the zero vector are shown enlarged. Here, in order to output the voltage space vector corresponding to the phase command value θ8 and the voltage command value v1, the basic output vector (
1, 0, 0), Tr (1°10), and zero vector output times, respectively.

When T 2 and T o are given, since the advance angle of the phase command value θ8 is θ, it is clear that the following equation should be satisfied by geometrical analysis as shown in the figure.

-”r, : T2 : To
(1) Therefore, in this embodiment, the retention time calculation circuit 11 is configured as shown in FIG. That is, the lead angle θ data from the phase command value classification means 9 is input into the ROM table 12.13, and the lead angle θ corresponding to the lead angle θ is
Find (π/6±θ). Then, one control period TsW
is multiplied by the voltage command value v8, and further sin (π/6
-θ) to obtain the holding time T1 of the switching mode corresponding to the basic output vector (1, 0, 0), which is also 1
Further s is added to the value obtained by multiplying the control period T5W by the voltage command value V8.
The basic output vector (1,
Holding time T2 of the switching mode corresponding to 1, 0)
shall be.

Further, by subtracting these T + and T 2 from the control period Tsw, the holding time T of the switching mode corresponding to the zero vector can be obtained. shall be. Then, the output from the holding time calculation circuit 11 is given to the command voltage vector replacement means 14.

Now, the command voltage vector replacement means 14 performs the above-mentioned switching mode holding times T, , T2 . T.

is given, the actual retention time T11. T2□, Too, which is the zero vector holding time T when a particularly high voltage command value v8 is given. An operation based on the substitution program is performed when is a negative value.

The time measuring means 15 includes a presettable counter 16, a switch 17, and a D-type flip-flop 18, and the data input terminal DATA of the presettable counter 16 receives each holding time T in response to switching of the switch 17. Or
TII+T22 is input to the clock terminal CK, and a clock signal fCK is input to the clock terminal CK. And switch 1
7 switches to the presettable counter 16 each time the holding time given to it is completed, and the next holding time is input, and the flip-flop 18 outputs the corresponding switching mode until each holding time is completed. The state is held and output to the switching control circuit 10 of the switching element in the inverter device.

Next, the operation of the above configuration will be described by dividing it into three regions shown in FIG. 4 depending on the region where the command voltage vector V exists. That is, the PWM shown in FIG.
There are three areas: area I which is a controllable area, area (2) which is a part perpendicular to each side outside area I, and area (2) which is the remaining part except these areas I and (2).

First, as shown in FIG. 6, when the command voltage vector V corresponding to the phase command value θ8 and the voltage command value V8 is in region I, that is, within the PWM controllable region, the following operation is performed. . The phase command value classification means 9 classifies the unit area according to the phase command value θ8 at that time, outputs the classification result to the switching mote determination means 10, and also outputs the data of the advance angle θ to the retention time calculation circuit 11. Output to. The retention time calculation circuit 11 calculates the equation (1) as described above.
) and calculate the holding time T, , T2 . for each basic output vector. T3 is given to the command voltage vector replacement means 14.

In response to this, the command voltage vector replacement means 14 starts a program according to the flowchart shown in FIG. First, the retention time T of the zero vector given from the retention time calculation circuit 11. is divided by 2 and the value is stored as comparison value A (step Sl). Next, the command voltage vector substitution means 14 determines whether the comparison value A just calculated is greater than or equal to zero (step S2). In this case, as described above, the command voltage vector V is within the PWM controllable region. For this reason, the retention time T5. Since it is a positive value,
It is determined that rYEsJ, and the process moves to step S3. Step S3 is the actual holding time T. 0T11. It determines T2□, which in this case is the retention time T. Assign a value obtained by doubling the comparison value A (that is, equal to To) as 0,
Substitute T, , T2 as is for the holding time Tll+T2□. As a result, in this case, the retention time from the retention time calculation circuit 11 is output as is as the actual retention time. In this way, the retention time T. . ,T,,
, T22 is output, the timer 15 applies a signal to the switching elements 3u to 3z via the switching control circuit 6 for a time corresponding to each holding time, and the basic output vector is controlled by time ratio to obtain a command. A voltage corresponding to the voltage vector ■ can be obtained.

Now, if the command voltage vector V is in the region ■, that is, P
When it is outside the WM controllable area, it operates as follows. First, in this case, the retention time calculation circuit 11 calculates the retention time T according to equation (1) in the same manner as described above. ,T,
, T2, the retention time T of the zero vector. becomes a negative value. Figure 7 shows the locus of the command voltage vector V in such a case with a broken line g.
It is a figure when it is classified as being in the phase region. As can be seen from a comparison with FIG. 6, when the zero vector retention time T0 is calculated according to the ratio shown in equation (1), it becomes a negative value that is actually impossible. The command voltage vector replacement means 14 uses such a negative holding time T. When , it is determined in step S2 that rNOJ is given, and the process moves to step S4. Here, the command voltage vector replacement means 14 adds the comparison value A calculated in step S1 to the holding time T2 given from the holding time calculation means 11 to obtain a comparison value B. Here, since the comparison value A is a negative value, the comparison value B is a value smaller than the holding time T2. Next, in step S4, it is determined whether the comparison value B is greater than or equal to zero, and in this case, since it is positive, it is determined as ``YESJ'' and the process moves to step S5. It was determined that the voltage vector V exists in region n (see Figure 4).In step S5, the comparison value B is set to the actual holding time T2□, and the holding time T10 is set to T1. Substitute the value obtained by adding the comparison value A and set the holding time Too of the zero vector to zero.Thereby, the command voltage vector ■ becomes the corrected command voltage vector V'
(See Figure 7). The physical meaning of the above process is the retention time T of the zero vector. By dividing into two equal parts and subtracting them from the respective holding times T, T2, the command voltage vector V is moved to a point P where it intersects with a commonly drawn perpendicular line that indicates the boundary of the PWM controllable region,
The command voltage vector V', which is the closest to PWM controllable, is substituted.

Next, when rNOJ is determined in the above-mentioned step S4, that is, when the command voltage vector V exists in the region ■, the process moves to step S6, where the holding time T11 is set as the control period Tsw, and the holding time T22 and T' Let oo be Cero. As a result, when the command voltage vector V is in the region (3), the basic output vector is substituted for all command voltage vectors, thereby replacing it with the nearest command voltage vector V' (not shown).

As a result of the above, when the command voltage vector V shown in FIG. 7 is given, the nearest command voltage vector V along the edge of the PWM controllable region for the inverter device
By replacing it with ' and outputting it, it is possible to obtain an output voltage with the distortion suppressed to a minimum.

FIG. 8 shows a second embodiment of the present invention, which is composed of a logic circuit so as to function as a part of the holding time calculation circuit 11 and the command voltage vector replacement means 14 in the first embodiment. A command voltage vector replacement means 19 is shown. In this embodiment, each input data is parallel 1
It is assumed that processing is performed using 0-bit digital data.

In FIG. 8, the adder 20 has a holding time T1 and a holding time T1.
2 is added and given to the subtracter 21 as a subtraction value. The subtracter 21 subtracts the subtracted value from the adder 2O from the control period Tsw and outputs the result to the AND circuits 22 and 23. Subtractor 21
has a sign judgment terminal CX1, which outputs a judgment signal of the rHJ level when the subtraction result is a negative value, and this judgment signal is given to the other input terminal of the AND circuit 22 and is inverted. AND circuit 2 via circuit 24
3 to the other input terminal. The output of the AND circuit 23 is the holding time T of the actual zero vector. It is set to 0. The subtracter 25 is supplied with the output of the AND circuit 22 and a subtracted value via a divider 26 that divides the output of the AND circuit 22 into two, and outputs the subtraction result to the adder 27 .

The adder 27 adds the output of the subtracter 25 and the holding time T1 and outputs the result. The adder 28 adds the output of the divider 26 and the holding time T2 and provides the result to the AND circuit 29. Also,
The adder 28 has a sign determination terminal CY2, and supplies an rLJ level determination signal to the other input terminal of the AND circuit 29 when the addition result is a negative value.

Then, the output of the AND circuit 29 is the actual holding time T22.
It is said that The changeover switch 30 always sets the output of the adder 27 as the actual holding time T11, and outputs rLJ from the adder 28.
Holding time T when the level judgment signal is output,
1 is set as the control period T5W.

According to the above configuration, the operation is performed as follows depending on the region where the command voltage vector {circle around (2)} exists.

First, when the command voltage vector is in the region ■, the subtracter 21 subtracts the addition result (T1+T2) given from the adder 20 from the control period T5W.

Since (-Tsw TI T2) is not negative,
The determination signal becomes rLJ level. As a result, the output of the AND circuit 23, that is, the subtraction result T of the subtracter 2]. is the retention time T. Output as 0. Also, at this time, AND circuit 2
Since the determination signal of the subtracter 2] is at the rLJ level, the output is cut off, and the inputs to the adders 27 and 28 become zero. The output of the adder 28 is output as it is at T2 (>O) or via the AND circuit 29 for a holding time T2°.

On the other hand, the output of the adder 27 is also changed to the selector switch 3.
0, and at this time, the judgment signal of the AND circuit 28 is r
Since it is at the LJ level, the changeover switch 30 directly outputs T1 as the holding time T]1.

Next, when the command voltage vector V is in the region (3), the subtractor 21 performs subtraction in the same manner as described above, and the result becomes negative, so the output of the AND circuit 23 is cut off.
Zero vector retention time T. . becomes zero, and the AND circuit 22 outputs a negative subtraction result (To). As a result, the adder 27 outputs T and T. The adder 28 outputs the result of adding /2 and adds T2 to T2. The result of adding /2 will be output. At this time, since the output of the adder 28 is not negative, it is output as is as the holding time T2□, and the output of the adder 27 is outputted as the holding time T,1 via the changeover switch 30.

Furthermore, when the command voltage vector V is in the region ■,
Since the addition result of the adder 28 described above becomes a negative value, the output of the AND circuit 29 is cut off, and the determination signal becomes rLJ level, so that the changeover switch 30 is switched. As a result, the holding time T11 is set as the control period Tsw, and the holding time T. . and T11 will be output as zero.

Therefore, the second embodiment also provides the same effects as the first embodiment.

Now, FIGS. 9(a) and 9(b) are waveform diagrams calculated by simulation of the output of the inverter device obtained by the above first or second embodiment, and the same load torque is applied to the three-phase induction motor. The phase currents at the time are compared, and FIG. 11(a) is the one according to the conventional method, and FIG. 6(b) is the one according to the embodiment of the present invention. As can be seen from this result, when the two are compared, it can be seen that the current peak value and current effective value are smaller in the example of the present invention. This is because the magnetic flux generated inside the motor has a high fundamental wave output voltage, which means that torque can be generated with a small amount of current, resulting in high torque efficiency.

In each of the above embodiments, the case where the application is applied to an inverter device with open-loop control has been explained, but it goes without saying that it can also be applied to an inverter device with current control, and in that case, high current tracking performance is required. You will get it.

[Effects of the Invention] As explained above, according to the three-phase PWL1 voltage generation method of the present invention, when the command voltage vector exists outside the PWN1 controllable region, the command voltage vector is subjected to PWM control. Since the command voltage vector is replaced with the closest command voltage vector in the possible range, it has the advantage of being able to output a fundamental wave voltage higher than the maximum fundamental wave voltage that can be modulated by a sine wave as a PWM waveform with extremely low distortion with a simple configuration. It has a great effect.

[Brief explanation of drawings]

1 to 7 show a first embodiment of the present invention.
The figure is a block diagram of the three-phase PWM signal generation circuit, Figure 2 is an electrical configuration diagram of the inverter device, Figure 3 is a flowchart of the command voltage vector replacement program, and Figure 4 is an explanation of dividing the existence area of the command voltage vector. Figure 5 is a vector diagram of the voltage space hector, Figure 6 is a vector diagram of the voltage space vector showing only a part of the area enlarged, and Figure 7 is when the command voltage vector is outside the PWM controllable area. FIG. 8 is a diagram equivalent to FIG. 1 showing the second embodiment of the present invention, and FIGS. 9(a) and 9(b) are waveforms calculated by simulation of the output current. It is a diagram. FIG. 10 is a waveform diagram for explaining the problems of the conventional example. In the drawing, 1 is the inverter main circuit, 3u, 3v3w, 3x
, By, 3z are switching elements, 6 is a switching control circuit, 7 is a motor, 8 is a three-phase PWM signal generation circuit, 9
10 is a phase command value classification means, 10 is a switching mode determination means, 11 is a holding time calculation circuit, 14.19 is a command voltage vector replacement means, 15 is a time measurement means, 16 is a presettable counter, 17 is a switch, and 18 is a flip-flop. It is. ko) <>>iN Agent Patent Attorney Rules Noriyuki Chika Diagram Diagram 〒 4th (1, 1, 1) Diagram Diagram

Claims (1)

[Claims] 1. In an inverter device that converts a DC power source into a three-phase PWM voltage signal and outputs the signal when a command voltage vector is given, when the command voltage vector exists outside the PWM controllable region on the voltage vector plane. A three-phase PWM voltage generation method characterized in that the command voltage vector is replaced with the nearest command voltage vector in a PWM controllable region, thereby converting the command voltage vector into a three-phase PWM voltage signal and outputting the signal.