JPH0479770A - 3-phase pwm signal generating circuit of inverter - Google Patents

Abstract

PURPOSE:To facilitate a high maximum output voltage of an inverter without giving a distortion to the output waveform of the inverter by a method wherein holding periodes of two types of switching modes corresponding to a voltage space vector determined in accordance with a phase command value and a voltage command value and of a switching mode corresponding to a zero vector are respectively calculated. CONSTITUTION:A voltage space vector corresponding to a phase command value theta* and a voltage command value V* is outputted by a time ratio control of two basic output vectors (voltage space vectors) among six basic output vectors having a phase difference of pi/3 between each other and a zero vector. If the holding period of a switching mode corresponding to the one basic output vector is denoted by t1 and the holding period of a switching mode corresponding to the other basic output vector is denoted by t2, a period obtained by subtracting t1 and t2 from a control period TSW is the holding time t0 of a switching mode corresponding to the zero vector. A switch 21 is switched so as to repeat the cycle of the holding periods of (t1 t0 t1) (t2 t0 t2).

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention provides an inverter device that controls the switching mode of each switching element in a time ratio in order to supply a sine wave output from the inverter device to a three-phase load. The present invention relates to a three-phase PWM signal generation circuit.

(Prior Art) An example of a conventional PWM signal generation circuit in an inverter device is shown in FIG. The figure shows a block diagram for one phase, where 1 is a comparator, 2 is a modulated wave generation circuit that outputs a modulated wave (for example, a triangular wave), and 3 is a reference corresponding to the voltage command value ■8 and frequency command value f8. This is a reference signal generation circuit that outputs a signal. The comparator 1 outputs an ON signal during a period in which the signal is greater than the reference signal or the modulated wave, and conversely outputs an OFF signal in a period in which the signal is smaller than the reference signal or the modulated wave. Here, a sine wave signal is generally given as the reference signal, and as shown in Fig. 10, when the amplitude of the reference signal a is set equal to the modulating wave, the output voltage of the inverter device becomes maximum. .

(Problem to be solved by the invention) However, even when using the reference signal a shown in FIG. 10, the output voltage of the inverter device is only (T/2 times the maximum voltage that can be controlled by PWM Furthermore, if a reference signal whose maximum amplitude exceeds the modulation wave is used to obtain an even larger output voltage, distortion will occur in the output waveform of the inverter device.

The present invention was made in view of the above circumstances, and its purpose is to make it possible to increase the maximum output voltage without distorting the output waveform of the inverter device, and to reduce current ripples and torque ripples for the load. The present invention provides a three-phase PWM signal generation circuit for an inverter device.

[Structure of the Invention] (Means for Solving the Problems) The three-phase PWM signal generation circuit of the present invention controls the switching mode of six switching elements in the inverter device in a time ratio, thereby generating a three-phase load from the inverter device. This system is for supplying a sine wave output to the system, and classifies the given phase command value into each unit area obtained by dividing the electrical angle 2π into six equal parts, and calculates the lead angle of the phase command value in that unit area. Based on the phase command value classification means, the unit region to which the phase command value belongs, and the past switching mode, two types of switching modes corresponding to voltage space vectors whose phases differ by π/3 from each other and a switching mode corresponding to a zero vector are determined. two types of switching modes and a zero vector corresponding to the voltage space vector determined by the switching mode determining means based on the lead angle of the phase command value within the unit area and the given voltage command value; a holding time calculating means for calculating each holding time of each switching mode corresponding to the holding time; and a timing means for holding the output state of each switching mode until the holding time of each switching mode calculated by the holding time calculating means elapses. The present invention is characterized in that the zero vector is inserted once even when any one of the two switching modes is being output.

(Function) The switching mode determining means determines the switching mode corresponding to two types of voltage space vectors and the switching mode corresponding to the zero vector according to the phase command value, and the holding time calculating means determines the progress of the phase command value in the unit area. The holding time of each switching mode is calculated based on the angle and voltage command value. Then, the output state of each switching mode is sequentially held by the clock means until the respective calculated holding times have elapsed. This results in
Switching of each switching element in the main circuit of the inverter device is controlled, so that a voltage space vector corresponding to an arbitrary phase command value and voltage command value is output, and the maximum output voltage of the inverter device can be increased. Further, in this case, since the zero vector is inserted once during the output period of the switching mode corresponding to the two types of space vectors, current ripple and torque ripple are reduced.

(Example) Hereinafter, a first example of the present invention will be described with reference to FIGS. 1 to 5.

First, the schematic configuration of the main circuit in the inverter device to which the present invention is applied is as shown in FIG.
This is a well-known configuration in which V, 13W, 13X, 13Y + 13Z are connected in a bridge manner.

Here, since only one of the upper and lower switching elements of each arm is turned on, there are 23-8 switching modes, and the voltage of each phase relative to the virtual neutral point is determined according to these switching modes. takes either ±V/2. Therefore, among the voltage space vectors that give an instantaneous vector expression to the output voltage of the inverter device by considering the phase difference between each phase, those that can be instantaneously output are the switching elements 13u, 13v on the positive side of each phase, If Sa, Sb, and Sc are represented as "1" when 13w is on, and "0" when negative side switching elements 13x, 13y, and 13z are on, then (Sa, Sb, SC). Also, when these are illustrated, as shown by the solid line in Figure 3,
It can be expressed as six basic output vectors (0, 0, 0) and (1, 1, 1) that differ in phase from each other by π/3 and have the same size.

Now, the three-phase PWM signal generation circuit for controlling the switching of each switching element in the above-mentioned inverter device has the configuration shown in FIG. Here, ]4 is a phase command value classification means, which classifies the given phase command value θ3 into each unit area obtained by dividing the electrical angle 2π into six equal parts, and outputs the classification result as 3-bit information. At the same time, the advance angle θ in that unit area is calculated and output. Reference numeral 15 denotes a switching mode determining means, which divides the phase command value θ1 classified by the phase command value classification means 14 into two types of basic output vectors (voltage space vectors) whose phases differ by π/3 from each other depending on the unit region to which they belong. The switching mode corresponding to the zero vector and the switching mode corresponding to the zero vector are determined, and in principle, two types of basic output vectors are determined: the phase command value θ and the closest phase in FIG. That is, for example, when the phase command value θ8 is at the position shown in FIG. 3, the basic output vector and thus the switching mode are determined to be (1, 0, 0) and (1, 1, 0). In addition, as will be made clear from the explanation of the action described later, there are two types of zero vectors (1, 1,
1) and (0,0°0) is selected by referring to past switching modes so as to minimize the number of switchings.

By the way, in the present invention, a voltage space vector of arbitrary size and phase is outputted by time ratio control of a basic output vector (voltage space vector) whose phase is different from each other by π/3 and a zero vector. In this case, the voltage space vector that can be output should exist inside the hexagon connecting the tips of the six basic output vectors in FIG. However, considering the sine wave approximation, the maximum possible output voltage differs depending on the phase angle, so the limit area of sine wave modulation that can be achieved by controlling the time ratio between the basic output vector and the zero vector is the inscribed circle of the above hexagon. It becomes inside. Therefore, a polar coordinate system can be used to realize an arbitrary voltage space vector within this limit region, and considering symmetry, discussion can be limited to the π/3 region only. FIG. 4 shows an enlarged view of the basic output vectors (1, 0, 0), (1, 1, 0), and the zero vector. Here, in order to output the voltage space vector corresponding to the phase command value θ1 and the voltage command value V11, the basic output vector (1, 0, 0
), (1, 1, 0), and the zero vector output time are respectively tl + 2 + tO. Since the advance angle of the phase command value θ1 in the unit area to which the phase command value θ8 belongs is θ, as shown in the figure. It is clear from the above geometrical analysis that the following equation should be satisfied.

V"5jn(--θ):V"sjnθ:1-V"fsin(-10) 10sinθ)1
1. : 12 : 1o...
(1) Therefore, in this embodiment, the retention time calculation means 16 is configured as shown in FIG. That is, the lead angle θ data from the phase command value classification means 14 is stored in the ROM table 1.
7.18, and sin (
π/3−θ) and sInθ are determined.

Then, the value obtained by multiplying one control cycle Tsw by the voltage command value V1 is further multiplied by sin (π/3-θ) to obtain the holding time t1 of the switching moat corresponding to the basic output vector (1, 0, 0), and also Voltage command value v in one control period Tsw
The value obtained by multiplying x is further multiplied by sjnθ to obtain the holding time t2 of the switching mode corresponding to the basic output vector (1, 1, O). Then, by subtracting these tl+t2 from the control period TSV, the holding time t of the switching mode corresponding to the zero vector is obtained. shall be.

]9 is a clock means. This is a presettable counter 20. The presettable counter 20 is equipped with a switch 21 and a D-type flip-flop 22, and the data input terminal DATA of the presettable counter 20 receives each holding time t in accordance with the switching of the switch 21. .

tl+t2 is input, and a clock signal f_ck is input to the clock terminal CK. And switch 2]
is switched each time the measurement of each holding time given to the presettable counter 20 is completed, and data for the next holding time is input, and the flip-flop 22 is switched to the corresponding switching mode until the timing of each holding time is completed. The output state is held and output to the switching control circuit of the switching element in the inverter device.

Next, the operation of the above configuration will be explained. FIG. 5 shows the locus of the magnetic flux vector W generated in a three-phase induction motor, which is a three-phase load, due to the output of the inverter device, and the flat line indicates the average locus, which draws a circular orbit. Here, the magnetic flux vector force is expressed as a time integral of the voltage space vector, and since each basic output vector is a constant value, its direction is equal to the basic output vector, and the magnitude is proportional to the retention time of that basic output vector. .

Figure 5 shows that one zero vector is inserted while outputting one of two switching modes corresponding to voltage space vectors that differ in phase or π/3 from each other, and while outputting the other switching mode. This is to insert another zero vector into . In other words, the retention time is (1
, -1°+t)→(t2-to→t2.) The switch 21 is switched so as to repeat the cycle. To describe the operation shown in FIG. 5 in more detail, for example, if the switching mode corresponding to the basic output vector (1, 0, 0) is maintained for a time t1, then the zero vector (0, 0, 0 ) is the switching mode corresponding to time t
. After that, the basic output vector (1,0
, 0) is held for a time t, then the switching mode corresponding to the basic output vector (1, 1, 0) is held for a time t2, then the zero vector (1, 1, 1 ) corresponding to the switching mode or time t. After that, the switching mode corresponding to the basic output vector (1, 1, 1) is held again for a time t2. In this way, a zero vector is always inserted once while the switching mode corresponding to the same basic output vector is output twice.

In this case, when transitioning from the basic output vector (1, 0, 0) to the zero vector, the switching mode determining means 1
5 as a zero vector instead of (1, 1, 1) (
The reason why I choose (0,0,0) is (1,0,0)
) to (0,0,0) requires only one switching, and the purpose is to minimize switching loss and perform efficient operation.

As described above, according to this embodiment, the maximum voltage ("f/
The maximum output voltage of the inverter device, which was twice as high, can be increased until it becomes equal to the maximum voltage that can be controlled by PWM. In addition, the phase command value θ1 is classified into six unit regions, and a zero vector is always inserted once during the output period of the switching mode corresponding to the two types of basic output vectors, so the output of the inverter device As a result, current ripple or torque ripple to the load can be reduced.

Next, FIG. 6 shows a second embodiment in which the present invention is applied to a V/F constant control type inverter device.
3 is a three-phase PWM embodying the present invention as shown in FIG.
Corresponds to a signal generation circuit.

Here, when the frequency command value f8 is given, the function generator 24 generates a voltage command value V8 corresponding to the frequency command value f8.
The phase signal generator 25 outputs a phase command value θ8 to the three-phase PWM signal generating circuit 23 as well.

FIG. 7 shows a third embodiment in which the present invention is applied to a current tracking type inverter device. Here, when the detected current value 1 and the current command value 11 are given from the current detector 26 to the conversion circuit 27, these are converted into the voltage command value V8 and the phase command value θ8, and the three-phase PWM signal generation circuit of the present invention 23. According to the present invention, a voltage space vector of arbitrary voltage and phase can be realized in a time twice as long as the control period Tsv, so that it can also be applied to high-speed current control by using high switching frequency elements.

FIG. 8 shows a fourth embodiment, which differs from the first embodiment in that the retention time calculation means 16 is converted into a function table using a ROM. In this case, input the voltage command value ■8 with 8 bits, the lead angle θ with 7 bits, and input tO+
Even if I+i2 is output with 10 bits each, the ROM
The memory capacity required for this is 960 bits, which can be easily realized with a single 1M bit memory IC.

In addition, the present invention is not limited to the embodiments described above and shown in the drawings; for example, the switch 21 in FIG.
The functions of the switching mote determination means 15 can be converted into a table and replaced with ROM or software, etc., without departing from the spirit of the invention.

[Effects of the Invention] As described above, according to the present invention, an appropriate switching mode and its holding time are determined according to an arbitrary phase command value and voltage command value, and the output state of each switching mode is determined by the timing means. is held until the holding time elapses, so the maximum output voltage of the inverter device can be increased to the maximum voltage that can be controlled by PWM. Since the switching mode corresponding to one zero vector is inserted in the switching mode, an excellent effect is achieved in that current ripple or torque ripple can be reduced.

[Brief explanation of the drawing]

1 to 5 show a first embodiment of the present invention.
The figure is an overall block diagram, Figure 2 is a circuit diagram of the main circuit of the inverter device, Figure 3 is a vector diagram of voltage space vectors,
FIG. 4 is a vector diagram of voltage space vectors showing only a part of the region enlarged, FIG. 5 is a vector diagram showing the locus of magnetic flux vectors, and FIG. 6 is a block diagram showing a second embodiment of the present invention. , FIG. 7 is a block diagram showing a third embodiment of the invention, and FIG. 8 is a block diagram showing a fourth embodiment of the invention. FIG. 9 is a block diagram showing a conventional three-phase PWM signal generation circuit, and FIG. 10 is a voltage waveform diagram of the same. In the drawing, 13u, 13v, 13w, 13x, 13y, 1
3z is a switching element, 14 is a phase command value classification means,
15 is a switching mode determining means, 16 is a holding time calculating means, and 19 is a clocking means.

Claims (1)

[Claims] 1. A device for supplying a sine wave output from the inverter device to a three-phase load by time-ratio control of the switching modes of six switching elements in the inverter device, and converts a given phase command value into an electrical angle. 2π
a phase command value classification means that classifies the phase command value into six equal unit areas and calculates the advance angle of the phase command value in the unit area; and two types based on the unit area to which the phase command value belongs and the past switching mode. are in phase with each other
/3 Switching mode determining means for determining a switching mode corresponding to a different voltage space vector and a switching mode corresponding to a zero vector, and said switching based on a lead angle of a phase command value within said unit area and a given voltage command value. retention time calculation means that calculates each retention time of two types of switching modes corresponding to the voltage space vector determined by the mode determination means and the switching mode corresponding to the zero vector, and each retention time calculated by the retention time calculation means and a timer for holding the output state of each switching mode until the holding time of the switching mode elapses, and the zero vector is set once when either of the two switching modes is being output. A three-phase PWM signal generation circuit for an inverter device, characterized in that the circuit is inserted into the inverter device.