JPH0479584A - Television system conversion circuit - Google Patents

Abstract

PURPOSE:To convert a television system to a different one with simple constitution by substituting an interpolation signal generated by an interpolation signal generating means for image information insufficient in a second television system compared with a first television system. CONSTITUTION:This circuit is comprised of a clock generating means 22 which generates a clock with frequency according to a selected system out of the first and second television systems, and a video signal forming means 26 which forms a video signal from a signal read out from a memory means 20 according to a signal generated from the clock generating means 22 and the interpolation signal generated from the interpolation signal generating means 24. The clock generating means 22 reads out storage data in the memory means 20 at a prescribed timing when output with the second television system is issued, and a signal which generates the interpolation signal is generates in a period equivalent to an insufficient picture element. Thereby, it is possible to attain television system conversionability to obtain the video signals of plural television system from one image pickup device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television format conversion circuit for obtaining video signals of a plurality of television formats from one imaging device.

[Prior art] Television systems include NTSC system and PAL.
There are two methods, such as the SECAM method, and these have different video synchronization signal standards. For example, as shown in Figure 2,
The PAL standard has 625 scanning lines and a horizontal scanning period of 64 μs, while the NTSC standard has 5 scanning lines.
There are 25 lines, and the horizontal scanning period is 63.5 μs.

Because of these differences, video equipment, such as movie cameras, electronic still cameras, video recording and playback devices, etc., are manufactured in accordance with one television system.

Therefore, one imaging device cannot obtain video signal outputs of different systems.

However, in recent years, as people have become more mobile, there has been a demand for inexpensive video equipment and format conversion devices that can output from multiple television formats.

Therefore, it is an object of the present invention to provide a television format conversion circuit for obtaining video signals of a plurality of television formats from one imaging device.

[Means for Solving the Problems] A television system conversion circuit according to the present invention outputs video signals of a first television system and a second television system that has a larger number of pixels than the first television system. An imaging device capable of freely selecting a number of pixels, comprising: an imaging means having a number of pixels corresponding to a first television system; and a memory means for storing an output image of the imaging means at a frequency corresponding to the first television system. , interpolation signal generation means for outputting an interpolation signal that is insufficient when outputting the second television system, and clock generation means for generating a clock having a frequency according to the system selected from the first and second television systems. and a video signal forming means for forming a video signal from a signal read out from the memory means according to a signal generated by the clock generating means and an interpolated signal generated from the interpolating signal generating means as necessary, The means reads the data stored in the memory means at a predetermined timing when outputting in the second television format;
The present invention is characterized in that the interpolation signal generating means generates a signal for generating an interpolation signal during a period corresponding to the missing pixel.

[Operation] In the means described in (1) above, the second television system is used for the first television system.
Insufficient image information in the television system is replaced by an interpolation signal generated by the interpolation signal generation means.

Therefore, compared to the N1]4 configuration in which the entire screen is enlarged or reduced, format conversion can be realized with a relatively simple, old, and inexpensive circuit configuration.

The image portion formed by the interpolation signal will appear like a frame at the edge of the screen, for example, or the originally required number of pixels will be secured, so there will be no problem in terms of image resolution.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention applied to a video camera. 10 is a photographing lens, 12 is a solid-state image sensor, and 14 is a sample hold (S/J-J
) circuit, 6 is an automatic gain adjustment circuit (AGC), 8 is an A/D converter, 20 is a memory, 21 is an NTSC/PA that specifies the output television system (NTSC or P△L)
Input terminal for L mode signal, 22 is clock generation circuit, 2
4 is an interpolation memory for storing interpolation data, 28 is a brightness processing circuit, 30 is a color processing circuit, and 32 is a composite video signal of the NTS C television system formed from the outputs of the brightness processing circuit 28 and the color processing circuit 30. N T
A composite video signal of the PAL television system is formed from the outputs of the SC encoder 34 and the brightness processing circuit 28 and the color processing circuit 80.
It is an AL encoder.

The main purpose of this embodiment is to convert from a television system with a small number of pixels to a television system with a large number of pixels, and for missing information, for example, interpolation data prepared in advance is placed at the bottom left and right edges of the screen. Try to supplement it by applying it. In the television format playback image after conversion, "-
An image based on interpolation data will appear at the bottom left and right edges, and you can change the color, pattern, etc. to your liking by selecting the interpolation data. For example, when converting the television system from the NTSC system to the FAI system, the PAL system has more image information in both the horizontal and vertical directions than the NTSC system. If it is considered that there is no need for an image at the edge of the screen, the missing image information may be interpolated with black, gray, white, or any other suitable color or pattern at the edge of the screen. This interpolation data is stored in the interpolation memory 24 in advance.

First, the basic operation shown in FIG. 1 will be explained. The image sensor 12 converts the optical image formed by the photographing lens 10 into an electrical signal, and the output thereof is sampled and held by the S/H circuit 14, and then automatically adjusted to an appropriate gain by the AGC circuit 16, and then converted into an A/D converter. is applied to the device 18. The A/D converter 18 receives the clock WCK from the clock generation circuit 22.
The output signal of the C circuit 16 is converted into a digital signal and written into the memory 20. Note that this clock wCI is also supplied at the same time to the input clocks of the image pickup device 2, the S/I-I circuit 14, the A/D converter 18, and the memory 2o. Also, the clock wcK is NTS
It is a clock with a frequency that complies with the C system, and the operation from the image sensor 12 to writing to the memory 2o is NTSC.
Compliant with C method.

Although the details will be described later, the clock generation circuit 22 inputs the read clock RCK1 of the frequency and timing according to the television system specified by the NTsC/PAL mode 1' signal input to the input terminal 21 to the read clock input of the memory 20. and, if necessary, supplies the read clock RCK 2 to the interpolation memory 24. The clock generation circuit 22 further includes the NTS C/PA 1. ,,
A sunblink clock SCK having a frequency corresponding to the television system specified by the mode signal is supplied to the D/A converter 26. The data read from the memory 2O and the interpolation memory 24 by the clocks RCKI and RCK2 is converted into an analog signal by the D/A converter 26, and subjected to brightness processing and color processing by the brightness processing circuit 28 and color processing circuit 30, respectively. and NTSC encoder 32
P is converted into an NTSC composite video signal by
The AL encoder 34 converts the signal into a PA-1 composite video signal.

Although not shown, the NTSC/
A switch may be provided to change the output of encoder 3234 depending on the PAL mote signal, or one of encoders 32, 34 may be activated.

Next, the processing characteristics of each television system will be briefly explained. In general, the sampling frequency of the image sensor should be set to an integer multiple of the color subcarrier frequency fsc so that the beat disturbance between the sampling clock and the color video signal is minimized, and the It is easier to perform image processing if the sample points of the images match vertically and horizontally as well as between frames. Therefore, the sampling frequency is fs
It is often an even number multiple of c. For example, when the sampling frequency is 4fsc, in the PAL method widely used in Europe, the color subcarrier frequency f psc4
．． For 43MHz, 4 f psc = 17.73
On the other hand, in the NTC system used in Japan and the United States, the color subcarrier frequency f n5
4 f n5c = 14 for c = 3.58 MHz
．． 43) +tHz is chosen. The number of horizontal pixels for the JUTTE, PAL, and NTSC systems is 4f psc, respectively.
X 64 p s = 1135, and 4 f n5c
X63.5 μs = 910, and the number of horizontal scanning lines is 625 (PAL) and 525 (N T S C
).

FIG. 3 shows circuits 1 to 1 of the clock generation circuit 22. 40 is an oscillator that generates a clock for the PAL system, and 42 is an oscillator that generates a clock for the NTSC system.

44 is an OR gate, and 46 is an OR gate I. In response to the output pulse S2 of 44, counting of horizontal synchronizing pulses of the PΔI method is started, and the count value is the number of horizontal scanning lines in one field of the NTSC method, 525/ A counter 48 that outputs a signal S3 when the value reaches 2 is the output pulse S3 of the counter 46.
Start counting PAL horizontal synchronization pulses in response to
This counter outputs a signal S4 when the count value reaches 100/2, which is the value obtained by subtracting the number of horizontal scanning lines in one field in the PAL system, 625/2, by the number of horizontal scanning lines in one field in the NTSC system, 525/2. 5052 is an RS flip-flop. The output S4 of the counter 48 is OR.
A start pulse S1, which is not shown in the figure or is formed from the first vertical synchronizing signal of the NTSC system detected immediately after the start of system conversion, is applied to the gate 44 and to another input of the OR gate 44. be done. These circuits 4
4 to 52 form a mask signal that masks the output clock of the PAL oscillator 40 in the vertical direction.

54 is an OR gate, 56 starts counting the output clocks of the PAL clock oscillator 40 in response to the output pulse S8 of the OR gate 54, and the count value is the number of clocks corresponding to one horizontal scanning period of 635 μs in the NTSC system, i.e. 91
A counter 58 that outputs a signal S9 when it reaches 0 starts counting the tl count of the output tarlock of the PAL clock oscillator 40 in response to the output j=10 pulse S9 of the counter 56, and when the count value is PAT, the horizontal Remaining scan period: 126 μs (=64-514
), that is, 225, the signal S
This is a counter that outputs IO. 60.62 is an RS flip-flop. Output S of counter 58 1. O
is applied to the OR gate 54, and the other input to the OR gate 54, although not shown, is the first horizontal open signal 1IJ1 of the NTSC system detected immediately after the start of system conversion.
A start pulse S7 formed from the signal is applied. These circuits 54-62 are PA1. Oscillator 40
A mask signal is formed to mask the output clock of the output clock in the horizontal direction.

Others: 64 is an and gate, 66 is an or gate,
68 is an AND gate, and 70 is N′I″SC/
1) This is a switch that is switched by the A'+-mote signal.

First, the case where the output method is the NTSC method will be explained. The image sensor 12 has an NTSC sampling frequency of 4 f.
Driven by n5c=14.43M1lz, also 4f
The data is converted into a digital ray word using the nsc sampling clock and stored in the memory 20. IKTS
When using the CNTSC system, the switch 70
Connected to the a contact side by PAL mode signal, memory 20
The frequency of the read clock RCKI to the D/A converter 26 and the sampling clock SCK to the D/A converter 26 are 4 f n
It becomes sc. Since interpolation using the interpolation data of the interpolation memory 24 is not necessary, the reading of the interpolation memory 24 is
, CK 2 is fixed at - (or high). memory 2
The stored data of 0 is directly converted into an analog signal by the D/A converter 26, processed by the brightness processing circuit 28 and color processing circuit 30, and converted into a composite video signal by the N'SC encoder 32 and output. .

Next, the operation at the time of PAL format output will be explained. FIG. 4 shows the vertical timing chart 1. FIG. 5 shows the horizontal timing chart 1. Figures 4 and 5
The signals 81 to SIO in the figure are the signals 81 to S in FIG. 3, respectively.
] Corresponds to 0.

First, the vertical direction will be explained. When a start pulse S1 is applied to counter 46 via OR gate 44,
The counter 46 indicates that the number of horizontal scanning lines in one field in the PAT method is 625/2, and the number of horizontal scanning lines in the NTSC method is 52,572 (1, F A X,...).

The horizontal synchronization signal of the system is counted 17 and a signal S3 is output.

The counter 48 starts counting in response to the signal S3, and 625
/ 2 - 525 / 2 = 100 / 2 old enemies, output signal S4. Signal S4 is fed through an OR gate 44 to a counter 46;
A pulse S2 is applied to the counter 46 every period.

RS flip-flop 50 is set by signal S2 and reset by signal S3. Further, the R,S flip-flop 52 is set and separated by the signal S3, and the signal S
It is reset by 4. In this way, a mask signal S5 is obtained from the RS flip-flop 50 that masks the output clock of the PAL oscillator 42 so as to read only the data stored in the memory 20, and a mask signal S5 is obtained from the RS flip-flop 52 to mask the output clock of the PAL oscillator 42 so as to read only the data stored in the memory 20. A mask signal S6 is obtained which masks the output clock of the PAL oscillator 42 so that only the interpolated data stored in the PAL oscillator 24 is read out.

As can be seen from FIG. 4, the mask signal 85. S6 has a waveform that complements each other's masked portions. Therefore, after the first vertical synchronization signal is input manually, 525/
21-T period is the NTSC written in the memory 20.
During the remaining 100/2 H], interpolation data written in advance in the interpolation memory 24 is read out, and one field of the P A,L method can be obtained.

Next, the horizontal operation will be explained with reference to FIG. After the start of system conversion, when the pulse signal S7 that detects the first horizontal synchronization signal triggers the counter 56 via the OR gate 54, the counter 56 receives 514 μs of the 64 fts of one horizontal scanning period of the PAL system. period (i.e., N
The output clocks of the PAL oscillator 40 (910 clocks corresponding to 635 μs of one horizontal scanning period in the TSC system) are counted and the Norculus signal S9 is output. Counter 58 is activated by signal S9 = 14 = 64 - 51.4 = 12.6 μS]
When the output clocks of FAT and oscillator 40 are recorded during (225 clocks), a pulse signal S10 is output. Since SlO is supplied to the counter 56 as a signal 88 via the OR gate 54, the OR gate 5
The output signal S8 of No. 4 becomes a pulse signal with a period of 64 μS from the first horizontal synchronization signal of the NTSC system after the start of system conversion.

RS flip-flop 60 is set by signal S8 and reset by signal S9. Further, the RS flip-flop 62 is set by the signal S9, and the RS flip-flop 62 is set by the signal S9.
It is reset by O. In this way, from the RS flip-flop 60, a mask signal 81.1 is obtained which masks the output clock of the PΔL oscillator 42 so as to read only the data stored in the memory 20, and from the RS flip-flop 62, a mask signal 81.1 is obtained that masks the output clock of the PΔL oscillator 42 so as to read only the data stored in the memory 20. A mask signal S,+,2 is obtained which masks the output clock of the AL oscillator 42 so as to read only the interpolated data stored in the I) AL oscillator 42. As can be seen from FIG. 5, the mask signal Sco],
, S12 have waveforms that complement each other's masked portions. Therefore, during the period of 635 μs after the input of the first horizontal open] signal, the N written in the memory 20 is
Read TSC method data, remaining 05μS
During the period, the interpolation data in the interpolation memory 24 is read out, and the
One horizontal scanning period of the AL method can be obtained.

The AND gate 64 receives the mask signal S5 and the mask signal Sll obtained as described above, and the PA and L oscillators 42.
From the output clock of
A clock R, CK:I is formed from which reading is performed from the beginning, and reading is not performed otherwise. Also, or
A circuit consisting of a gate 66 and an AND gate 68 reads out data from the interpolation memory 24 at a point other than the line 14 in FIG. The clocks R and CK2, which are not read out, are formed in the shaded areas. The output of the ant gate 64 is sent to the memory 20 via the switch 70 as the read clock RCKI. The output of AND gate 68 is supplied to interpolation memory 24 as read clock RCK 2 via switch 70 .

In the above embodiment, the data stored in the interpolation memory 24 for missing pixels is used to supplement the data stored in the interpolation memory 24. However, if the DC component of black, white, or gray is sufficient to compensate for the missing pixels, the interpolation memory 24 shown in FIG. The part can be simplified as shown in FIG. 7
2 is the logical OR of the signal IS6 and 812 in Figure 3.
Gate 1-374 is a switch that is closed by the output of OR gate 74, and 76 is a battery that generates a DC component for the interpolation portion.

OR gate 72 closes switch 74 during the pulse period shown at 86 in FIG. 4 and 812 in FIG.

As a result, the output voltage of the battery 74 is applied to the brightness processing circuit 28 and the color processing circuit 30 during the period of the image portion to be interpolated.

In the first embodiment, the sampling frequency was set to 4fsc, which is four times the color subcarrier frequency fsc, for both the NTSC system and PAL, but the present invention is not limited to this. For example, the aspect ratio of the Go pixel is set to 1: The frequency that makes it 1 (NT
SC system], 2.29 MHz, FA T- system, 14.74 MHz) may be selected, or other frequencies may be selected. In addition, in a series of examples,
The NTS C image is always played back and displayed on the left side of the screen, and the interpolated data image is displayed on the right and bottom edges of the screen, but the initial jυj values of counters 46, 48, 56.58, etc. are changed. By doing this, you can save memory 2 to any location on the screen.
o stored images can be located.

Furthermore, although the conversion from the NTSC system to the Y)Δ■7 system has been described, the conversion from the NTSC system to the S E CAM system can also be realized in the same way.

[Effects of the Invention] As can be easily understood from the explanation given below, according to the present invention, it is possible to convert to a different television system with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the configuration of an embodiment of the present invention, Fig. 2 is a screen configuration diagram of the NTS C system and PAL system, and Fig. 3 is a block diagram of the configuration of an embodiment of the present invention.
The diagram shows the circuit of the clock generation circuit 22 in Figure 1) 1111'
8° configuration example, Figure 4 is a vertical timing diagram when converting from NTSC to PAL format, Figure 5 is NTSC
The horizontal timing diagram in FIG. 6 when converting from the PAL method to the PAL method is an alternative example of the interpolation memory 24. 10: Photographic lens 12: Image sensor 14: Sample
Hold circuit 16 Automatic gain adjustment circuit (AGC)
18: A/D converter 20: Memory 21: NTSC
/PΔL mote signal input terminal 22, clock generation circuit
24. Interpolation memory 28: Brightness processing circuit 30: Color processing circuit 32: NTSC encoder 34: PAL encoder 40: PAT-oscillator 42: NTSC oscillator
445466 Or Gate 46 48: Counter
50, 52: RS '7'J flip flop 5658: Counter 6062・RS flip flop 64 68: And goo 1-fu 0: Swissochi

Claims (1)

[Claims] An imaging device capable of selecting a video signal output of a first television system and a second television system having a larger number of pixels than the first television system, the imaging device having a number of pixels corresponding to the first television system. a memory means for storing an output image of the imaging means at a frequency corresponding to the first television system; and an interpolation signal generator for outputting an interpolation signal that is insufficient when outputting the second television system. a clock generating means for generating a clock having a frequency according to a selected one of the first and second television systems; a signal read from the memory means in accordance with a signal generated by the clock generating means; and a video signal forming means for forming a video signal from the interpolation signal generated by the interpolation signal generating means, if necessary, and the clock generating means outputs data from the memory means at a predetermined timing when outputting in the second television system. 1. A television system conversion circuit, characterized in that it reads stored data and generates a signal for generating an interpolation signal from the interpolation signal generation means during a period corresponding to the missing pixels.