JPH0478128A - Formation of fine structure of semiconductor - Google Patents
Formation of fine structure of semiconductorInfo
- Publication number
- JPH0478128A JPH0478128A JP19073490A JP19073490A JPH0478128A JP H0478128 A JPH0478128 A JP H0478128A JP 19073490 A JP19073490 A JP 19073490A JP 19073490 A JP19073490 A JP 19073490A JP H0478128 A JPH0478128 A JP H0478128A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- thin film
- grown
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000010408 film Substances 0.000 claims abstract description 21
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 239000012792 core layer Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000011148 porous material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 21
- 238000005530 etching Methods 0.000 abstract description 15
- 239000013078 crystal Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 1
- 230000005284 excitation Effects 0.000 description 6
- 238000010884 ion-beam technique Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- -1 ion beam Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001741 metal-organic molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Drying Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明は、電子デバイス、光デバイス等の半導体デバイ
スに利用される半導体微細構造を作製するの半導体微細
構造作製技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor fine structure manufacturing technique for manufacturing semiconductor fine structures used in semiconductor devices such as electronic devices and optical devices.
[従来の技術]
一般に、半導体の微細構造の作製には、以下のようなエ
ツチング、または、選択成長等の技術を適宜用いる必要
がある。[Prior Art] In general, the following techniques such as etching or selective growth must be appropriately used to fabricate semiconductor fine structures.
これらの技術には、大別して、マスクパターンを用いな
い方法と用いる方法とがあり、それぞれ以下のようなも
のである。These techniques can be broadly classified into methods that do not use a mask pattern and methods that use a mask pattern, and the methods are as follows.
マスクパターンを用いないエツチングは、光、電磁波、
電子線、イオンビーム等を適当な手段により収束させ、
エツチングしようとする部位にのみ直接照射して何等か
の励起を与え、その部位のエツチングを促進する。ここ
でいう励起とは、例えば、エツチングガスのプラズマと
光との相互作用による反応種の励起作用を利用したエッ
チングの促進現象や、半導体表面の自然酸化膜層を電子
線及びイオンビームなどにより局所的に除去し、酸化膜
を除去した清浄表面のみをガスエツチングする現象をも
含んでいる。Etching without using a mask pattern uses light, electromagnetic waves,
Focus electron beams, ion beams, etc. by appropriate means,
Direct irradiation is applied only to the area to be etched to provide some kind of excitation to promote etching in that area. Excitation here refers to, for example, an etching acceleration phenomenon that utilizes the excitation effect of reactive species due to the interaction between etching gas plasma and light, or a localized phenomenon in which a natural oxide film layer on a semiconductor surface is irradiated with an electron beam or an ion beam. It also includes the phenomenon of gas etching only the clean surface from which the oxide film has been removed.
また、マスクパターンを用いる場合には、溶液、イオン
線、または、ガス等を用いる。この場合にも光、電磁波
等によるエツチング現象の促進(例えば反応性イオンエ
ツチング法など)や、イオンビーム照射によるスパッタ
リング作用を用いたエツチング(イオンミリング)等、
何等かの形で励起を伴うことが多い。このマスクパター
ンヲ用イる場合は、微細加工において励起を局所的に限
定して行わない。即ち、この場合においては、エツチン
グする場所はマスクパターンで指定する。このため、マ
スクパターンを用いる方法は、ウェハー全面に亘って一
度にエツチングが進行するという特徴を有しており、大
量生産技術に向いている。Furthermore, when using a mask pattern, a solution, ion beam, gas, or the like is used. In this case, the etching phenomenon can be accelerated by light, electromagnetic waves, etc. (for example, reactive ion etching method, etc.), etching using sputtering effect by ion beam irradiation (ion milling), etc.
It is often accompanied by some form of excitation. When this mask pattern is used, excitation is not locally limited during microfabrication. That is, in this case, the location to be etched is designated by a mask pattern. Therefore, the method using a mask pattern has the characteristic that etching progresses over the entire wafer at once, and is suitable for mass production technology.
これら以外の半導体微細構造の作製技術として、選択成
長を用いた微細加工技術がある。As a manufacturing technique for semiconductor fine structures other than these, there is a fine processing technique using selective growth.
この方法は、上述のエツチングを用いる方法とは逆に、
所定の場所のみに結晶を成長させるものである。二の方
法でもマスクパターンを用いる場合と、マスクパターン
を用いずに局所的に励起を行い選択成長を行う場合とか
ある。This method is the opposite of the method using etching described above.
Crystals are grown only in predetermined locations. In the second method, there are cases where a mask pattern is used and cases where selective growth is performed by locally excitation without using a mask pattern.
さらに他の半導体微細構造の作製技術として、超格子構
造の半導体ウェハーに、イオン注入法とアニール法を組
み合わせた処理を加えて、超格子構造を不規則化させ、
所定の部位に混晶化を起こさせる微細構造形成方法や、
Fvl B E法なとにより、微傾斜基板上に原料種を
交互に供給し、原子層ステップにおける吸着状態の原子
種依存性を用いて微細構造を作製する方法などがある。Furthermore, as another technique for manufacturing semiconductor microstructures, a semiconductor wafer with a superlattice structure is subjected to a process that combines ion implantation and annealing to make the superlattice structure irregular.
A microstructure formation method that causes mixed crystallization in a predetermined region,
There is a method such as the Fvl BE method in which raw material species are alternately supplied onto a slightly inclined substrate and a fine structure is produced using the dependence of the adsorption state on the atomic species in the atomic layer step.
従来は、上記の技術を用いて、半導体基板上に微細構造
を作製し、その後、埋め込み成長等を行って、半導体デ
バイスを得ている。Conventionally, a fine structure is created on a semiconductor substrate using the above-mentioned technique, and then buried growth or the like is performed to obtain a semiconductor device.
〔発明が解決しようとする課題]
しかしながら、従来の方法では以下のような問題点かあ
る。[Problems to be Solved by the Invention] However, the conventional method has the following problems.
マスクパターンを用いるエツチング及び選択成長では、
その精度がマスクパターンの精度に依存するため、ある
程度以上の微細化ができないという問題点がある。In etching and selective growth using mask patterns,
Since the accuracy depends on the accuracy of the mask pattern, there is a problem that it is not possible to achieve fineness beyond a certain level.
マスクパターンを用いないエツチング方法及び選択成長
方法は、収束したビームを所定の範囲にのみ照射するた
めに除振装置、ビームを広範な領域に走査させるための
特別なビーム走査装置または基板保持装置などの複雑な
装置を必要とするという問題点がある。また、ビームの
走査に時間が掛かるため、大量生産には向かないという
問題点もある。さらに、イオンビームを用いた場合には
エツチング後に損傷を回復させることが非常に困難であ
るために、作製された素子の特性に与える影響が心配さ
れる。Etching methods and selective growth methods that do not use a mask pattern require a vibration isolator to irradiate a focused beam only to a predetermined area, a special beam scanning device or substrate holding device to scan a beam over a wide area, etc. There is a problem in that it requires complicated equipment. Another problem is that it takes time to scan the beam, making it unsuitable for mass production. Furthermore, when an ion beam is used, it is very difficult to recover from damage after etching, so there is concern about the effect it will have on the characteristics of the fabricated device.
超格子構造の半導体ウェハーに、イオン注入法とアニー
ル法を組み合わせ、所定の部位に混晶化を起こさせる方
法では、イオンスパッタによる損傷の影響や、アニール
によるイオンの拡散の制御性などの問題点がある。The method of combining ion implantation and annealing in a semiconductor wafer with a superlattice structure to cause mixed crystal formation in a predetermined location has problems such as damage caused by ion sputtering and controllability of ion diffusion by annealing. There is.
微傾斜基板を用いた方法は、結晶成長条件に敏感で、広
範囲に亘る均一な構造、及びnmオーダーの精度で微細
構造を形成することか困難であるという問題点かある。The method using a slightly tilted substrate has problems in that it is sensitive to crystal growth conditions and it is difficult to form a uniform structure over a wide range and a fine structure with nanometer-order precision.
本発明は、複雑な装置を必要としない、加工精度の高い
、大量生産が可能な半導体微細構造作成方法を提供する
ことを目的とする。An object of the present invention is to provide a semiconductor microstructure fabrication method that does not require complicated equipment, has high processing accuracy, and is capable of mass production.
[課題を解決するための手段]
本発明は、多孔質薄膜を形成する第1の工程と、前記多
孔質薄膜の孔の内部に半導体コア層を選択成長する第2
の工程と、前記多孔質薄膜を除去する第3の工程と、前
記コア層を埋め込む埋込層を成長する第4の工程と、を
含むことを特徴とする半導体微細構造作製方法である。[Means for Solving the Problems] The present invention includes a first step of forming a porous thin film, and a second step of selectively growing a semiconductor core layer inside the pores of the porous thin film.
, a third step of removing the porous thin film, and a fourth step of growing a buried layer for burying the core layer.
[実施例] 以下に、図面を参照して本発明の詳細な説明する。[Example] The present invention will be described in detail below with reference to the drawings.
GaAs%Aj!GaAs系を用いたいわゆるスーパー
アトムの作製方法について説明する。GaAs%Aj! A method for producing a so-called super atom using GaAs will be explained.
ここで、スーパーアトムとは、量子箱の一種で、バンド
ギャップが大きい半導体からなる極めて狭い領域に不純
物を閉じ込めると、その周りに不純物の数に等しい電子
がクーロン力で束縛され、あたかも巨大化した人工原子
のように働くというものである。Here, a super atom is a type of quantum box. When an impurity is confined in an extremely narrow region made of a semiconductor with a large band gap, electrons equal to the number of impurities are bound around it by the Coulomb force, making it appear as if it had become gigantic. It works like an artificial atom.
まず、第1図(a)に示すように、P−GaAs基板1
1上にノンドープGaAs結晶層12をバッファ層とし
て数千へ成長させる。そして、成長させたGaAs結晶
層12上に、p−5i層13を約4OA、2段階成長法
等により成長させる。First, as shown in FIG. 1(a), a P-GaAs substrate 1
1, a non-doped GaAs crystal layer 12 is grown to a thickness of several thousand as a buffer layer. Then, on the grown GaAs crystal layer 12, a p-5i layer 13 is grown at about 4 OA by a two-step growth method or the like.
次に、陽極酸化法を用いて第1図(b)に示す様に、p
−5i層13を多孔質化し、バッファ層12に達する複
数の孔14を設ける。このときの孔14の分布を第1図
(C)に示す。Next, as shown in FIG. 1(b), p
-5i layer 13 is made porous and a plurality of holes 14 reaching buffer layer 12 are provided. The distribution of the holes 14 at this time is shown in FIG. 1(C).
陽極酸化法は、一般に成膜方法として知られている方法
と同じである。即ち、弗化水素酸水溶液中で、p−8i
層13に正、白金に負の直流電流を流すというものであ
る。この方法のよって形成される孔14の径と深さ、及
び、孔14の分布密度は、p−Si層13の電気伝導度
、印加される電圧及び電流等によって決定される。複数
の孔14の径のばらつきは、例えば径が〜40人てあれ
ば、±5人程度と、電子線リソグラフィー等による加工
の場合の理論限界に近い精度(理論的には数10人程度
、実用的には約100への精度である。)か実現できる
。The anodic oxidation method is the same as a method generally known as a film forming method. That is, in a hydrofluoric acid aqueous solution, p-8i
A positive direct current is passed through the layer 13 and a negative direct current is passed through the platinum layer. The diameter and depth of the holes 14 formed by this method and the distribution density of the holes 14 are determined by the electrical conductivity of the p-Si layer 13, the applied voltage and current, etc. For example, if the diameter of the holes 14 is ~40, the variation in the diameter of the holes 14 is about ±5 people, which is close to the theoretical limit for processing by electron beam lithography (theoretically, it is about several dozen people, In practice, an accuracy of about 100) can be achieved.
次に、この多孔質化されたp−5i層13を有するウェ
ハーを酸素雰囲気中に置き、第1図(d)に示すように
表面に5in2膜15、及び、GaAs酸化膜16を形
成する。Next, the wafer having the porous p-5i layer 13 is placed in an oxygen atmosphere, and a 5in2 film 15 and a GaAs oxide film 16 are formed on the surface as shown in FIG. 1(d).
酸化膜を形成した後、真空中にて、このウェハーを昇温
しでいくと、550℃前後でGaAs酸化膜16のみが
除去される。After forming the oxide film, when the temperature of the wafer is raised in a vacuum, only the GaAs oxide film 16 is removed at around 550°C.
この後、GaAs酸化膜16が除去されたウェハー表面
にMOMBE法等を用いてp型All。After that, p-type All-in-all is formed on the wafer surface from which the GaAs oxide film 16 has been removed using MOMBE method or the like.
G a 0.7 A 5層17を結晶成長させる。この
とき、第1図(e)に示すように、5in2膜上では結
晶成長は起こらず、GaAsバッファ層上でのみ成長か
進行する。即ち、孔14の内部にのみ結晶が成長する。G a 0.7 A 5 layer 17 is grown as a crystal. At this time, as shown in FIG. 1(e), crystal growth does not occur on the 5in2 film, and growth progresses only on the GaAs buffer layer. That is, crystals grow only inside the holes 14.
このp型AD O,3G a o、、A s層17は、
スーパーアトムのコア部となる。This p-type ADO,3G ao,,A s layer 17 is
It becomes the core part of Super Atom.
次に、このウェハーを弗酸溶液等に浸して5in2膜1
5を除去し、さらにCF4 +O□系のガスエツチング
等によって、Si層13を除去する。これによって、ス
ーパーアトムのコア部である複数の円柱型p−Aj7G
aAs層17か表面に突出する。Next, this wafer is immersed in a hydrofluoric acid solution etc. to form a 5in2 film 1.
5 is removed, and the Si layer 13 is further removed by CF4+O□-based gas etching or the like. As a result, multiple cylindrical p-Aj7G, which is the core part of the super atom,
The aAs layer 17 protrudes from the surface.
最後に、表面にノンドープGaAs埋込層18を成長さ
せて、第1図(f’)に示すようにp−11?GaAs
層17を埋め込み、スーパーアトムとする。Finally, a non-doped GaAs buried layer 18 is grown on the surface, and as shown in FIG. 1(f'), p-11? GaAs
Layer 17 is embedded to form a super atom.
このように、本実施例によれば、径〜4〇人、高さ〜4
0Aのp−AgGaAs層17をコア部とするスーパー
アトム(量子箱)を大量に、精度良く作製することがで
きる。In this way, according to this embodiment, the diameter is ~40 people and the height is ~4
Super atoms (quantum boxes) having the 0A p-AgGaAs layer 17 as a core part can be manufactured in large quantities with high precision.
なお、上記実施例ではGaAs/Aj? GaAs系を
材料とするスーパーアトムの作製方法に付いて説明した
が、これに限られるものではない。In addition, in the above embodiment, GaAs/Aj? Although the method for producing a super atom using GaAs-based material has been described, the method is not limited thereto.
また、薄膜もSi膜に限らず、多孔質化が精度良く容易
にできるものであればよく、例えばCaF等の弗化物系
の膜でも良い。Further, the thin film is not limited to a Si film, and may be any film that can be easily made porous with high precision, for example, a fluoride film such as CaF.
さらに、薄膜を多孔質化する方法も、薄膜を制御良く多
孔質化できる方法であれば、陽極酸化法に限るものでは
ない。Furthermore, the method of making the thin film porous is not limited to anodization, as long as it is a method that can make the thin film porous with good control.
[発明の効果]
本発明によれば、多孔質薄膜を形成し、薄膜の孔の内部
に半導体コア層を選択成長させた後、多孔質薄膜を除去
し、その後、コア層を埋め込む埋込層を成長するように
したことで、複雑な装置を必要とせず、高精度に大量の
量子箱を容易に作製することができる。[Effects of the Invention] According to the present invention, after forming a porous thin film and selectively growing a semiconductor core layer inside the pores of the thin film, the porous thin film is removed, and then a buried layer in which the core layer is embedded is formed. By growing quantum boxes, it is possible to easily produce large quantities of quantum boxes with high precision without the need for complicated equipment.
第1図は本発明の一実施例の作製工程を説明するための
図である。
11・・・p−GaAs基板、12・・・ノンドープG
aAsバッファ層、13 ・= p型Si薄膜、14・
・・孔、15−5in2膜、16− G a A s酸
化膜、17−p型Ajt o、i G a o7A s
層、18−=ノンドープGaAs埋込層。
第
(a)
1ム
(b)
(C)
(d)
(e)
(f)FIG. 1 is a diagram for explaining the manufacturing process of an embodiment of the present invention. 11... p-GaAs substrate, 12... non-doped G
aAs buffer layer, 13.= p-type Si thin film, 14.
...hole, 15-5in2 film, 16-GaAs oxide film, 17-p type Ajto, iGao7As
layer, 18-=undoped GaAs buried layer. Section (a) 1 (b) (C) (d) (e) (f)
Claims (3)
る第2の工程と、 前記多孔質薄膜を除去する第3の工程と、 前記コア層を埋め込む埋込層を成長する第4の工程と、 を含むことを特徴とする半導体微細構造作製方法。1. a first step of forming a porous thin film; a second step of selectively growing a semiconductor core layer inside the pores of the porous thin film; a third step of removing the porous thin film; and a third step of removing the porous thin film. A method for manufacturing a semiconductor microstructure, comprising: a fourth step of growing a buried layer that embeds the .
極酸化法によりを多孔質化することを特徴とする請求項
1記載の半導体微細構造の作製方法。2. 2. The method of manufacturing a semiconductor microstructure according to claim 1, wherein in the first step, after forming the thin film, the thin film is made porous by an anodic oxidation method.
記載の半導体微細構造の作製方法。3. Claim 2, wherein the thin film is a Si film.
A method for fabricating the semiconductor microstructure described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19073490A JPH0478128A (en) | 1990-07-20 | 1990-07-20 | Formation of fine structure of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19073490A JPH0478128A (en) | 1990-07-20 | 1990-07-20 | Formation of fine structure of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0478128A true JPH0478128A (en) | 1992-03-12 |
Family
ID=16262893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19073490A Pending JPH0478128A (en) | 1990-07-20 | 1990-07-20 | Formation of fine structure of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0478128A (en) |
-
1990
- 1990-07-20 JP JP19073490A patent/JPH0478128A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1402567B1 (en) | Film or layer made of semi-conductive material and method for producing said film or layer | |
US7517776B2 (en) | Method for controlling dislocation positions in silicon germanium buffer layers | |
JPS62140485A (en) | Semiconductor structure and manufacture thereof | |
JPH022102A (en) | Manufacture of semiconductor device | |
JP3763021B2 (en) | Electron beam micromachining method | |
JPH0478128A (en) | Formation of fine structure of semiconductor | |
JP4803513B2 (en) | Ion beam micromachining method | |
JPH07202164A (en) | Manufacture of semiconductor micro-structure | |
JP4052430B2 (en) | Ion beam microfabrication method of inorganic multilayer resist and semiconductor device, quantum device, micromachine component and microstructure by this method | |
JP2003179031A (en) | MACHINING METHOD OF Si SEMICONDUCTOR FINE STRUCTURE DUE TO ION BEAM IMPLANTATION LITHOGRAPHY OF INORGANIC MULTILAYER RESIST AND INTEGRATED CIRCUIT, DEVICE, AND MICROMACHINE COMPONENT THEREBY | |
US6037198A (en) | Method of fabricating SOI wafer | |
JP3201793B2 (en) | Processing method of Si substrate | |
JPWO2003054973A1 (en) | Ion beam microfabrication method of inorganic multilayer resist and semiconductor device, quantum device, micromachine component and microstructure by this method | |
JPS6060725A (en) | Forming method of pattern | |
CN116313756A (en) | Method for implanting oxygen atoms into monocrystalline silicon surface layer, preparation method and detection method of silicon nano channel | |
JPH04239789A (en) | Fabrication of fine structure | |
JP2998336B2 (en) | Method for etching compound semiconductor and method for forming semiconductor structure | |
JP2717165B2 (en) | Method for forming structure of compound semiconductor | |
JPS58112324A (en) | Manufacture of semiconductor device | |
JPS63281488A (en) | Manufacture of optical component | |
JPH038320A (en) | Formation of pattern | |
JP2004273610A (en) | Method of manufacturing fine facet shape on surface of semiconductor substrate | |
JPH01232715A (en) | Manufacture of semiconductor structure | |
JPH02177430A (en) | Method of processing compound semiconductor | |
JPH0729973A (en) | Dielectric isolation |